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[173.79.56.208]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6d39643b678sm77555456d6.97.2024.11.12.15.47.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 12 Nov 2024 15:47:58 -0800 (PST) Date: Tue, 12 Nov 2024 18:47:35 -0500 From: Gregory Price To: Dan Williams Cc: x86@kernel.org, linux-kernel@vger.kernel.org, linux-acpi@vger.kernel.org, linux-mm@kvack.org, linux-cxl@vger.kernel.org, kernel-team@meta.com, Jonathan.Cameron@huawei.com, rrichter@amd.com, Terry.Bowman@amd.com, dave.jiang@intel.com, ira.weiny@intel.com, alison.schofield@intel.com, dave.hansen@linux.intel.com, luto@kernel.org, peterz@infradead.org, tglx@linutronix.de, mingo@redhat.com, bp@alien8.de, hpa@zytor.com, rafael@kernel.org, lenb@kernel.org, david@redhat.com, osalvador@suse.de, gregkh@linuxfoundation.org, akpm@linux-foundation.org, rppt@kernel.org Subject: Re: [PATCH v6 3/3] acpi,srat: give memory block size advice based on CFMWS alignment Message-ID: References: <20241106155847.7985-1-gourry@gourry.net> <20241106155847.7985-4-gourry@gourry.net> <6733cba395c30_10bc6294df@dwillia2-xfh.jf.intel.com.notmuch> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <6733cba395c30_10bc6294df@dwillia2-xfh.jf.intel.com.notmuch> On Tue, Nov 12, 2024 at 01:41:55PM -0800, Dan Williams wrote: > Gregory Price wrote: > > Capacity is stranded when CFMWS regions are not aligned to block size. > > On x86, block size increases with capacity (2G blocks @ 64G capacity). > > > > Use CFMWS base/size to report memory block size alignment advice. > > > > Suggested-by: Dan Williams > > Signed-off-by: Gregory Price > > Acked-by: Mike Rapoport (Microsoft) > > Acked-by: David Hildenbrand > > --- > > drivers/acpi/numa/srat.c | 12 +++++++++++- > > 1 file changed, 11 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/acpi/numa/srat.c b/drivers/acpi/numa/srat.c > > index 44f91f2c6c5d..34b6993e7d6c 100644 > > --- a/drivers/acpi/numa/srat.c > > +++ b/drivers/acpi/numa/srat.c > > @@ -14,6 +14,7 @@ > > #include > > #include > > #include > > +#include > > #include > > #include > > #include > > @@ -338,13 +339,22 @@ static int __init acpi_parse_cfmws(union acpi_subtable_headers *header, > > { > > struct acpi_cedt_cfmws *cfmws; > > int *fake_pxm = arg; > > - u64 start, end; > > + u64 start, end, align; > > int node; > > > > cfmws = (struct acpi_cedt_cfmws *)header; > > start = cfmws->base_hpa; > > end = cfmws->base_hpa + cfmws->window_size; > > > > + /* Align memblock size to CFMW regions if possible */ > > + align = 1UL << __ffs(start | end); > > + if (align >= SZ_256M) { > > + if (memory_block_advise_max_size(align) < 0) > > + pr_warn("CFMWS: memblock size advise failed\n"); > > Oh, this made me go back to look at what happens if CFMWS has multiple > alignment suggestions. Should not memory_block_advise_max_size() be > considering the max advice? > > if (memory_block_advised_size) { > ... > } else { > memory_block_advised_size = max(memory_block_advised_size, size); > } > > For example, if region0 is an x4 region and region1 is an x1 region then > the memory block size should be 1GB, not 256M. I.e. CFMWS alignment > follows CXL hardware decoder alignment of "256M * InterleaveWays". Max size to minimize capacity loss to due alignment truncation. If CFMW-0 is aligned at 1GB and CFMW-1 is aligned at 256MB, if you select 1GB then some portion of CFMW-1 will be unmappable. so you want min(memory_block_advised_size, size) to ensure the hotplug memblock size aligns to the *smallest* CFMW (or any other source) alignment. Unless I'm misunderstanding your feedback here. I'm not clear on why the interleave data is relevant here - that just tells us how decoders line up with the memory region described in the CFMW. The window still gets chopped up into N memblocks of memory_block_advised_size. ~Gregory