From: Dave Jiang <dave.jiang@intel.com>
To: smadhavan@nvidia.com, dave@stgolabs.net,
jonathan.cameron@huawei.com, alison.schofield@intel.com,
vishal.l.verma@intel.com, ira.weiny@intel.com,
dan.j.williams@intel.com, bhelgaas@google.com,
ming.li@zohomail.com, rrichter@amd.com,
Smita.KoralahalliChannabasappa@amd.com, huaisheng.ye@intel.com,
linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Cc: vaslot@nvidia.com, vsethi@nvidia.com, sdonthineni@nvidia.com,
vidyas@nvidia.com, mochs@nvidia.com, jsequeira@nvidia.com
Subject: Re: [PATCH v4 09/10] PCI: save/restore CXL config around reset
Date: Wed, 21 Jan 2026 15:32:27 -0700 [thread overview]
Message-ID: <a0719ccc-4f2e-4b17-9361-a0759b1fca08@intel.com> (raw)
In-Reply-To: <20260120222610.2227109-10-smadhavan@nvidia.com>
On 1/20/26 3:26 PM, smadhavan@nvidia.com wrote:
> From: Srirangan Madhavan <smadhavan@nvidia.com>
>
> Save PCI and CXL configuration state before cxl_reset and restore it
> after reset completes. This preserves DVSEC state alongside standard
> PCI state and avoids losing reset-sensitive CXL configuration.
Instead of putting dependency on the cxl core, maybe just move the code in the previous patch here since it's just a few lines of config read/writes. But an explanation of why the DVSEC needs to be preserved on the device regardless of whether a driver is present is needed in the commit log.
DJ
>
> Signed-off-by: Srirangan Madhavan <smadhavan@nvidia.com>
> ---
> drivers/pci/pci.c | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
> index 18047c893b0c..0bc85c4cc5fd 100644
> --- a/drivers/pci/pci.c
> +++ b/drivers/pci/pci.c
> @@ -4960,6 +4960,7 @@ static int cxl_reset_init(struct pci_dev *dev, u16 dvsec)
> */
> static int cxl_reset(struct pci_dev *dev, bool probe)
> {
> + struct cxl_type2_saved_state cxl_state;
> u16 dvsec, reg;
> int rc;
>
> @@ -4989,6 +4990,11 @@ static int cxl_reset(struct pci_dev *dev, bool probe)
> if (probe)
> return 0;
>
> + pci_save_state(dev);
> + rc = cxl_config_save_state(dev, &cxl_state);
> + if (rc)
> + pci_warn(dev, "Failed to save CXL config state: %d\n", rc);
> +
> /*
> * CXL-reset-specific preparation: validate memory offline,
> * tear down regions, flush device caches.
> @@ -5004,10 +5010,16 @@ static int cxl_reset(struct pci_dev *dev, bool probe)
> if (rc)
> goto out_cleanup;
>
> + pci_restore_state(dev);
> + rc = cxl_config_restore_state(dev, &cxl_state);
> + if (rc)
> + pci_warn(dev, "Failed to restore CXL config state: %d\n", rc);
> +
> cxl_reset_cleanup_device(dev);
> return 0;
>
> out_cleanup:
> + pci_restore_state(dev);
> cxl_reset_cleanup_device(dev);
> return rc;
> }
> --
> 2.34.1
>
next prev parent reply other threads:[~2026-01-21 22:32 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-20 22:26 [PATCH v4 0/10] CXL Reset support for Type 2 devices smadhavan
2026-01-20 22:26 ` [PATCH v4 01/10] cxl: move DVSEC defines to cxl pci header smadhavan
2026-01-21 10:31 ` Jonathan Cameron
2026-01-20 22:26 ` [PATCH v4 02/10] PCI: switch CXL port DVSEC defines smadhavan
2026-01-21 10:34 ` Jonathan Cameron
2026-01-20 22:26 ` [PATCH v4 03/10] cxl: add type 2 helper and reset DVSEC bits smadhavan
2026-01-20 23:27 ` Dave Jiang
2026-01-21 10:45 ` Jonathan Cameron
2026-01-20 22:26 ` [PATCH v4 04/10] PCI: add CXL reset method smadhavan
2026-01-21 0:08 ` Dave Jiang
2026-01-21 10:57 ` Jonathan Cameron
2026-01-23 13:54 ` kernel test robot
2026-01-20 22:26 ` [PATCH v4 05/10] cxl: add reset prepare and region teardown smadhavan
2026-01-21 11:09 ` Jonathan Cameron
2026-01-21 21:25 ` Dave Jiang
2026-01-20 22:26 ` [PATCH v4 06/10] PCI: wire CXL reset prepare/cleanup smadhavan
2026-01-21 22:13 ` Dave Jiang
2026-01-22 2:17 ` Srirangan Madhavan
2026-01-22 15:11 ` Dave Jiang
2026-01-24 7:54 ` kernel test robot
2026-01-20 22:26 ` [PATCH v4 07/10] cxl: add host cache flush and multi-function reset smadhavan
2026-01-21 11:20 ` Jonathan Cameron
2026-01-21 20:27 ` Davidlohr Bueso
2026-01-22 9:53 ` Jonathan Cameron
2026-01-21 22:19 ` Vikram Sethi
2026-01-22 9:40 ` Souvik Chakravarty
[not found] ` <PH7PR12MB9175CDFC163843BB497073CEBD96A@PH7PR12MB9175.namprd12.prod.outlook.com>
2026-01-22 10:31 ` Jonathan Cameron
2026-01-22 19:24 ` Vikram Sethi
2026-01-23 13:13 ` Jonathan Cameron
2026-01-21 23:59 ` Dave Jiang
2026-01-20 22:26 ` [PATCH v4 08/10] cxl: add DVSEC config save/restore smadhavan
2026-01-21 11:31 ` Jonathan Cameron
2026-01-20 22:26 ` [PATCH v4 09/10] PCI: save/restore CXL config around reset smadhavan
2026-01-21 22:32 ` Dave Jiang [this message]
2026-01-22 10:01 ` Lukas Wunner
2026-01-22 10:47 ` Jonathan Cameron
2026-01-26 22:34 ` Alex Williamson
2026-03-12 18:24 ` Jonathan Cameron
2026-01-20 22:26 ` [PATCH v4 10/10] cxl: add HDM decoder and IDE save/restore smadhavan
2026-01-21 11:42 ` Jonathan Cameron
2026-01-22 15:09 ` Dave Jiang
2026-01-21 1:19 ` [PATCH v4 0/10] CXL Reset support for Type 2 devices Alison Schofield
2026-01-22 0:00 ` Bjorn Helgaas
2026-01-27 16:33 ` Alex Williamson
2026-01-27 17:02 ` dan.j.williams
2026-01-27 18:07 ` Vikram Sethi
2026-01-28 3:42 ` dan.j.williams
2026-01-28 12:36 ` Jonathan Cameron
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