Re: [PATCH 3/3] cxl/pci: Update only the Port GPF timeout fields

[Guixin Liu <kanie@linux.alibaba.com>]

在 2026/9/26 07:44, Jonathan Cameron 写道:
> On Tue, 22 Sep 2026 18:00:13 +0800
> Guixin Liu <kanie@linux.alibaba.com> wrote:
>
>> update_gpf_port_dvsec() rebuilds the phase control register from just
>> the timeout base and scale, so the rest of the register is cleared by
>> the write. The other bits are reserved today and nothing is lost, but
>> the full-register rewrite would clobber any field the spec defines
>> there later.
>>
>> Read-modify-write the register and change only the two timeout
>> fields.
>>
>> Fixes: a52b6a2c1c99 ("cxl/pci: Support Global Persistent Flush (GPF)")
>> Assisted-by: LLM
>> Signed-off-by: Guixin Liu <kanie@linux.alibaba.com>
>> ---
>>  drivers/cxl/core/pci.c | 5 +++--
>>  1 file changed, 3 insertions(+), 2 deletions(-)
>>
>> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
>> index 1f470ab0df3b..72e54facafe8 100644
>> --- a/drivers/cxl/core/pci.c
>> +++ b/drivers/cxl/core/pci.c
>> @@ -846,8 +846,9 @@ static int update_gpf_port_dvsec(struct pci_dev *pdev, int dvsec, int phase)
>>  	    FIELD_GET(scale, ctrl) == GPF_TIMEOUT_SCALE_MAX)
>>  		return 0;
>>  
>> -	ctrl = FIELD_PREP(base, GPF_TIMEOUT_BASE_MAX);
>> -	ctrl |= FIELD_PREP(scale, GPF_TIMEOUT_SCALE_MAX);
>> +	ctrl &= ~(base | scale);
>> +	ctrl |= FIELD_PREP(base, GPF_TIMEOUT_BASE_MAX) |
>> +		FIELD_PREP(scale, GPF_TIMEOUT_SCALE_MAX);
> I think a little nicer if you use a pair of FIELD_MODIFY() and let
> the compiler figure out that it can combine things.
Sure, changed in v2 thanks.

Best Regards,
Guixin Liu
>>  
>>  	rc = pci_write_config_word(pdev, dvsec + offset, ctrl);
>>  	if (rc) {