From: Dave Jiang <dave.jiang@intel.com>
To: Li Ming <ming.li@zohomail.com>,
dave@stgolabs.net, jonathan.cameron@huawei.com,
alison.schofield@intel.com, vishal.l.verma@intel.com,
ira.weiny@intel.com, dan.j.williams@intel.com
Cc: linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 1/1] cxl/hdm: Add support for 32 switch decoders
Date: Mon, 23 Mar 2026 08:37:19 -0700 [thread overview]
Message-ID: <a77fd9a3-e1e7-447d-8d60-d5c6b7dff9a8@intel.com> (raw)
In-Reply-To: <20260321061459.1910205-1-ming.li@zohomail.com>
On 3/20/26 11:14 PM, Li Ming wrote:
> Per CXL r4.0 section 8.2.4.20.1. CXL host bridge and switch ports can
> support 32 HDM decoders. Current implementation misses some decoders on
> CXL host bridge and switch in the case that the value of Decoder Count
> field in CXL HDM decoder Capability Register is greater than or equal to
> 9.
>
> Update calculation implementation to ensure the decoder count calculation
> is correct for CXL host bridge/switch ports.
>
> Signed-off-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> Changes from v1:
> - Return -ENXIO if the value violates SPEC. (Dave & Alison)
> ---
> drivers/cxl/core/hdm.c | 2 +-
> drivers/cxl/cxl.h | 11 ++++++++++-
> drivers/cxl/cxlmem.h | 2 +-
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index c222e98ae736..3930e130d6b6 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -177,7 +177,7 @@ static struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
> }
>
> parse_hdm_decoder_caps(cxlhdm);
> - if (cxlhdm->decoder_count == 0) {
> + if (cxlhdm->decoder_count < 0) {
> dev_err(dev, "Spec violation. Caps invalid\n");
> return ERR_PTR(-ENXIO);
> }
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 9b947286eb9b..0a5301049cf3 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -77,7 +77,16 @@ static inline int cxl_hdm_decoder_count(u32 cap_hdr)
> {
> int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr);
>
> - return val ? val * 2 : 1;
> + switch (val) {
> + case 0:
> + return 1;
> + case 1 ... 8:
> + return val * 2;
> + case 9 ... 12:
> + return (val - 4) * 4;
> + default:
> + return -ENXIO;
> + }
> }
>
> /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index e21d744d639b..399b150b404c 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -923,7 +923,7 @@ int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd);
> */
> struct cxl_hdm {
> struct cxl_component_regs regs;
> - unsigned int decoder_count;
> + int decoder_count;
> unsigned int target_count;
> unsigned int interleave_mask;
> unsigned long iw_cap_mask;
next prev parent reply other threads:[~2026-03-23 15:37 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-03-21 6:14 [PATCH v2 1/1] cxl/hdm: Add support for 32 switch decoders Li Ming
2026-03-23 2:39 ` Alison Schofield
2026-03-23 15:37 ` Dave Jiang [this message]
2026-03-23 15:55 ` Gregory Price
2026-04-10 8:17 ` Li Ming
2026-04-10 18:39 ` Dave Jiang
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