* Re: [PATCH v2 1/1] cxl/hdm: Add support for 32 switch decoders
2026-03-21 6:14 [PATCH v2 1/1] cxl/hdm: Add support for 32 switch decoders Li Ming
@ 2026-03-23 2:39 ` Alison Schofield
2026-03-23 15:37 ` Dave Jiang
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Alison Schofield @ 2026-03-23 2:39 UTC (permalink / raw)
To: Li Ming
Cc: dave, jonathan.cameron, dave.jiang, vishal.l.verma, ira.weiny,
dan.j.williams, linux-cxl, linux-kernel
On Sat, Mar 21, 2026 at 02:14:59PM +0800, Li Ming wrote:
> Per CXL r4.0 section 8.2.4.20.1. CXL host bridge and switch ports can
> support 32 HDM decoders. Current implementation misses some decoders on
> CXL host bridge and switch in the case that the value of Decoder Count
> field in CXL HDM decoder Capability Register is greater than or equal to
> 9.
>
> Update calculation implementation to ensure the decoder count calculation
> is correct for CXL host bridge/switch ports.
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v2 1/1] cxl/hdm: Add support for 32 switch decoders
2026-03-21 6:14 [PATCH v2 1/1] cxl/hdm: Add support for 32 switch decoders Li Ming
2026-03-23 2:39 ` Alison Schofield
@ 2026-03-23 15:37 ` Dave Jiang
2026-03-23 15:55 ` Gregory Price
2026-04-10 8:17 ` Li Ming
3 siblings, 0 replies; 6+ messages in thread
From: Dave Jiang @ 2026-03-23 15:37 UTC (permalink / raw)
To: Li Ming, dave, jonathan.cameron, alison.schofield, vishal.l.verma,
ira.weiny, dan.j.williams
Cc: linux-cxl, linux-kernel
On 3/20/26 11:14 PM, Li Ming wrote:
> Per CXL r4.0 section 8.2.4.20.1. CXL host bridge and switch ports can
> support 32 HDM decoders. Current implementation misses some decoders on
> CXL host bridge and switch in the case that the value of Decoder Count
> field in CXL HDM decoder Capability Register is greater than or equal to
> 9.
>
> Update calculation implementation to ensure the decoder count calculation
> is correct for CXL host bridge/switch ports.
>
> Signed-off-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
> ---
> Changes from v1:
> - Return -ENXIO if the value violates SPEC. (Dave & Alison)
> ---
> drivers/cxl/core/hdm.c | 2 +-
> drivers/cxl/cxl.h | 11 ++++++++++-
> drivers/cxl/cxlmem.h | 2 +-
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index c222e98ae736..3930e130d6b6 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -177,7 +177,7 @@ static struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
> }
>
> parse_hdm_decoder_caps(cxlhdm);
> - if (cxlhdm->decoder_count == 0) {
> + if (cxlhdm->decoder_count < 0) {
> dev_err(dev, "Spec violation. Caps invalid\n");
> return ERR_PTR(-ENXIO);
> }
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 9b947286eb9b..0a5301049cf3 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -77,7 +77,16 @@ static inline int cxl_hdm_decoder_count(u32 cap_hdr)
> {
> int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr);
>
> - return val ? val * 2 : 1;
> + switch (val) {
> + case 0:
> + return 1;
> + case 1 ... 8:
> + return val * 2;
> + case 9 ... 12:
> + return (val - 4) * 4;
> + default:
> + return -ENXIO;
> + }
> }
>
> /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index e21d744d639b..399b150b404c 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -923,7 +923,7 @@ int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd);
> */
> struct cxl_hdm {
> struct cxl_component_regs regs;
> - unsigned int decoder_count;
> + int decoder_count;
> unsigned int target_count;
> unsigned int interleave_mask;
> unsigned long iw_cap_mask;
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v2 1/1] cxl/hdm: Add support for 32 switch decoders
2026-03-21 6:14 [PATCH v2 1/1] cxl/hdm: Add support for 32 switch decoders Li Ming
2026-03-23 2:39 ` Alison Schofield
2026-03-23 15:37 ` Dave Jiang
@ 2026-03-23 15:55 ` Gregory Price
2026-04-10 8:17 ` Li Ming
3 siblings, 0 replies; 6+ messages in thread
From: Gregory Price @ 2026-03-23 15:55 UTC (permalink / raw)
To: Li Ming
Cc: dave, jonathan.cameron, dave.jiang, alison.schofield,
vishal.l.verma, ira.weiny, dan.j.williams, linux-cxl,
linux-kernel
On Sat, Mar 21, 2026 at 02:14:59PM +0800, Li Ming wrote:
> Per CXL r4.0 section 8.2.4.20.1. CXL host bridge and switch ports can
> support 32 HDM decoders. Current implementation misses some decoders on
> CXL host bridge and switch in the case that the value of Decoder Count
> field in CXL HDM decoder Capability Register is greater than or equal to
> 9.
>
> Update calculation implementation to ensure the decoder count calculation
> is correct for CXL host bridge/switch ports.
>
> Signed-off-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Gregory Price <gourry@gourry.net>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 1/1] cxl/hdm: Add support for 32 switch decoders
2026-03-21 6:14 [PATCH v2 1/1] cxl/hdm: Add support for 32 switch decoders Li Ming
` (2 preceding siblings ...)
2026-03-23 15:55 ` Gregory Price
@ 2026-04-10 8:17 ` Li Ming
2026-04-10 18:39 ` Dave Jiang
3 siblings, 1 reply; 6+ messages in thread
From: Li Ming @ 2026-04-10 8:17 UTC (permalink / raw)
To: dave, jonathan.cameron, dave.jiang, alison.schofield,
vishal.l.verma, ira.weiny, dan.j.williams
Cc: linux-cxl, linux-kernel
kindly ping.
Is this patch missing in cxl/next?
Ming
在 2026/3/21 14:14, Li Ming 写道:
> Per CXL r4.0 section 8.2.4.20.1. CXL host bridge and switch ports can
> support 32 HDM decoders. Current implementation misses some decoders on
> CXL host bridge and switch in the case that the value of Decoder Count
> field in CXL HDM decoder Capability Register is greater than or equal to
> 9.
>
> Update calculation implementation to ensure the decoder count calculation
> is correct for CXL host bridge/switch ports.
>
> Signed-off-by: Li Ming <ming.li@zohomail.com>
> ---
> Changes from v1:
> - Return -ENXIO if the value violates SPEC. (Dave & Alison)
> ---
> drivers/cxl/core/hdm.c | 2 +-
> drivers/cxl/cxl.h | 11 ++++++++++-
> drivers/cxl/cxlmem.h | 2 +-
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
> index c222e98ae736..3930e130d6b6 100644
> --- a/drivers/cxl/core/hdm.c
> +++ b/drivers/cxl/core/hdm.c
> @@ -177,7 +177,7 @@ static struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
> }
>
> parse_hdm_decoder_caps(cxlhdm);
> - if (cxlhdm->decoder_count == 0) {
> + if (cxlhdm->decoder_count < 0) {
> dev_err(dev, "Spec violation. Caps invalid\n");
> return ERR_PTR(-ENXIO);
> }
> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
> index 9b947286eb9b..0a5301049cf3 100644
> --- a/drivers/cxl/cxl.h
> +++ b/drivers/cxl/cxl.h
> @@ -77,7 +77,16 @@ static inline int cxl_hdm_decoder_count(u32 cap_hdr)
> {
> int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr);
>
> - return val ? val * 2 : 1;
> + switch (val) {
> + case 0:
> + return 1;
> + case 1 ... 8:
> + return val * 2;
> + case 9 ... 12:
> + return (val - 4) * 4;
> + default:
> + return -ENXIO;
> + }
> }
>
> /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */
> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
> index e21d744d639b..399b150b404c 100644
> --- a/drivers/cxl/cxlmem.h
> +++ b/drivers/cxl/cxlmem.h
> @@ -923,7 +923,7 @@ int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd);
> */
> struct cxl_hdm {
> struct cxl_component_regs regs;
> - unsigned int decoder_count;
> + int decoder_count;
> unsigned int target_count;
> unsigned int interleave_mask;
> unsigned long iw_cap_mask;
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v2 1/1] cxl/hdm: Add support for 32 switch decoders
2026-04-10 8:17 ` Li Ming
@ 2026-04-10 18:39 ` Dave Jiang
0 siblings, 0 replies; 6+ messages in thread
From: Dave Jiang @ 2026-04-10 18:39 UTC (permalink / raw)
To: Li Ming, dave, jonathan.cameron, alison.schofield, vishal.l.verma,
ira.weiny, dan.j.williams
Cc: linux-cxl, linux-kernel
On 4/10/26 1:17 AM, Li Ming wrote:
> kindly ping.
>
> Is this patch missing in cxl/next?
Sorry I missed it. Applied to cxl/next
3624a22783b7
>
>
> Ming
>
> 在 2026/3/21 14:14, Li Ming 写道:
>> Per CXL r4.0 section 8.2.4.20.1. CXL host bridge and switch ports can
>> support 32 HDM decoders. Current implementation misses some decoders on
>> CXL host bridge and switch in the case that the value of Decoder Count
>> field in CXL HDM decoder Capability Register is greater than or equal to
>> 9.
>>
>> Update calculation implementation to ensure the decoder count calculation
>> is correct for CXL host bridge/switch ports.
>>
>> Signed-off-by: Li Ming <ming.li@zohomail.com>
>> ---
>> Changes from v1:
>> - Return -ENXIO if the value violates SPEC. (Dave & Alison)
>> ---
>> drivers/cxl/core/hdm.c | 2 +-
>> drivers/cxl/cxl.h | 11 ++++++++++-
>> drivers/cxl/cxlmem.h | 2 +-
>> 3 files changed, 12 insertions(+), 3 deletions(-)
>>
>> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
>> index c222e98ae736..3930e130d6b6 100644
>> --- a/drivers/cxl/core/hdm.c
>> +++ b/drivers/cxl/core/hdm.c
>> @@ -177,7 +177,7 @@ static struct cxl_hdm *devm_cxl_setup_hdm(struct cxl_port *port,
>> }
>> parse_hdm_decoder_caps(cxlhdm);
>> - if (cxlhdm->decoder_count == 0) {
>> + if (cxlhdm->decoder_count < 0) {
>> dev_err(dev, "Spec violation. Caps invalid\n");
>> return ERR_PTR(-ENXIO);
>> }
>> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
>> index 9b947286eb9b..0a5301049cf3 100644
>> --- a/drivers/cxl/cxl.h
>> +++ b/drivers/cxl/cxl.h
>> @@ -77,7 +77,16 @@ static inline int cxl_hdm_decoder_count(u32 cap_hdr)
>> {
>> int val = FIELD_GET(CXL_HDM_DECODER_COUNT_MASK, cap_hdr);
>> - return val ? val * 2 : 1;
>> + switch (val) {
>> + case 0:
>> + return 1;
>> + case 1 ... 8:
>> + return val * 2;
>> + case 9 ... 12:
>> + return (val - 4) * 4;
>> + default:
>> + return -ENXIO;
>> + }
>> }
>> /* Encode defined in CXL 2.0 8.2.5.12.7 HDM Decoder Control Register */
>> diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
>> index e21d744d639b..399b150b404c 100644
>> --- a/drivers/cxl/cxlmem.h
>> +++ b/drivers/cxl/cxlmem.h
>> @@ -923,7 +923,7 @@ int cxl_mem_sanitize(struct cxl_memdev *cxlmd, u16 cmd);
>> */
>> struct cxl_hdm {
>> struct cxl_component_regs regs;
>> - unsigned int decoder_count;
>> + int decoder_count;
>> unsigned int target_count;
>> unsigned int interleave_mask;
>> unsigned long iw_cap_mask;
^ permalink raw reply [flat|nested] 6+ messages in thread