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[96.255.20.42]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7cd467d7efesm8601885a.30.2025.05.15.10.03.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 May 2025 10:03:54 -0700 (PDT) Date: Thu, 15 May 2025 13:03:52 -0400 From: Gregory Price To: Dave Jiang Cc: linux-cxl@vger.kernel.org, Dan Williams , dave@stgolabs.net, jonathan.cameron@huawei.com, alison.schofield@intel.com, ira.weiny@intel.com, rrichter@amd.com, ming.li@zohomail.com Subject: Re: [PATCH v2 08/10] cxl: Add helper to detect top of CXL device topology Message-ID: References: <20250507004310.3536991-1-dave.jiang@intel.com> <20250507004310.3536991-9-dave.jiang@intel.com> <96957e88-778e-41d6-a503-1819fac51855@intel.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <96957e88-778e-41d6-a503-1819fac51855@intel.com> On Tue, May 13, 2025 at 09:12:00AM -0700, Dave Jiang wrote: > > > On 5/13/25 8:49 AM, Gregory Price wrote: > > On Tue, May 06, 2025 at 05:43:08PM -0700, Dave Jiang wrote: > >> Add a helper to replace the open code detection of CXL device hierarchy > >> root. The helper will be used for delayed hostbridge port creation later > >> on. > >> > >> Signed-off-by: Dave Jiang > > > > ignorant terminology question: what's the different between the > > "cxl hierarchy head" and "cxl root"? > > I struggle to find the correct terminology between the head of the PCI (or platform device for cxl_test) hierarchy vs the CXL one we constructed for the 'cxl_port' hierarchy. I'm open to suggestions to use better words to distinguish that. Is there an actual difference or they actually the same "device" - just abstracted differently? ~Gregory