From: Robert Richter <rrichter@amd.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: linux-cxl@vger.kernel.org, dave@stgolabs.net,
jonathan.cameron@huawei.com, alison.schofield@intel.com,
vishal.l.verma@intel.com, ira.weiny@intel.com,
dan.j.williams@intel.com, Gregory Price <gourry@gourry.net>,
Alejandro Lucero <alucerop@amd.com>
Subject: Re: [PATCH v3 3/9] cxl: Separate out CXL dport->id vs actual dport hardware id
Date: Wed, 28 May 2025 14:53:38 +0200 [thread overview]
Message-ID: <aDcHUlKYjKXIZEDZ@rric.localdomain> (raw)
In-Reply-To: <20250521183443.3828320-4-dave.jiang@intel.com>
On 21.05.25 11:34:37, Dave Jiang wrote:
> @@ -667,7 +670,8 @@ struct cxl_rcrb_info {
> struct cxl_dport {
> struct device *dport_dev;
> struct cxl_register_map reg_map;
> - int port_id;
> + int id;
> + int port_num;
I have noticed some leftovers of the port_id string in 2 comments
(based on cxl/next):
drivers/cxl/core/pci.c: * dport->port_id is valid means that dport has been probed and is
drivers/cxl/cxl.h: * @target_map: array of expected dport port_id mirror the target
-Robert
> struct cxl_rcrb_info rcrb;
> bool rch;
> struct cxl_port *port;
next prev parent reply other threads:[~2025-05-28 12:53 UTC|newest]
Thread overview: 26+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-21 18:34 [PATCH v3 0/9] cxl: Delay HB port and switch dport probing until endpoint dev probe Dave Jiang
2025-05-21 18:34 ` [PATCH v3 1/9] cxl/region: Add decoder check to check_commit_order() Dave Jiang
2025-05-21 18:34 ` [PATCH v3 2/9] cxl: Add helper to detect top of CXL device topology Dave Jiang
2025-05-21 18:39 ` Dave Jiang
2025-05-22 9:18 ` Jonathan Cameron
2025-05-22 9:43 ` Li Ming
2025-05-21 18:34 ` [PATCH v3 3/9] cxl: Separate out CXL dport->id vs actual dport hardware id Dave Jiang
2025-05-22 9:43 ` Li Ming
2025-05-28 12:53 ` Robert Richter [this message]
2025-05-21 18:34 ` [PATCH v3 4/9] cxl: Remove adding of port_num via devm_cxl_add_dport() Dave Jiang
2025-05-21 18:34 ` [PATCH v3 5/9] cxl: Defer hardware dport->port_id assignment and registers probing Dave Jiang
2025-05-22 10:55 ` Li Ming
2025-06-04 15:27 ` Robert Richter
2025-05-21 18:34 ` [PATCH v3 6/9] cxl/test: Add workaround for cxl_test for cxl_core calling mocked functions Dave Jiang
2025-05-21 18:34 ` [PATCH v3 7/9] cxl: Change sslbis handler to only handle single dport Dave Jiang
2025-05-22 11:04 ` Li Ming
2025-05-21 18:34 ` [PATCH v3 8/9] cxl: Create an xarray to tie a host bridge to the cxl_root Dave Jiang
2025-05-21 18:34 ` [PATCH v3 9/9] cxl: Move enumeration of hostbridge ports to the memdev probe path Dave Jiang
2025-05-30 13:51 ` [PATCH v3 0/9] cxl: Delay HB port and switch dport probing until endpoint dev probe Robert Richter
2025-06-03 13:55 ` Dave Jiang
2025-06-04 15:44 ` Robert Richter
2025-06-05 15:17 ` Dave Jiang
2025-06-06 9:44 ` Robert Richter
2025-06-13 15:15 ` Gregory Price
2025-06-13 15:43 ` Dave Jiang
2025-06-17 17:47 ` Robert Richter
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