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[96.255.20.42]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-6fac6e00cebsm52506366d6.73.2025.06.01.16.30.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Jun 2025 16:30:46 -0700 (PDT) Date: Sun, 1 Jun 2025 19:30:44 -0400 From: Gregory Price To: Alok Tiwari Cc: dave@stgolabs.net, jonathan.cameron@huawei.com, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, ira.weiny@intel.com, dan.j.williams@intel.com, corbet@lwn.net, linux-cxl@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, darren.kenny@oracle.com Subject: Re: [PATCH] Documentation: cxl: fix typos and improve clarity in memory-devices.rst Message-ID: References: <20250531075209.3334261-1-alok.a.tiwari@oracle.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250531075209.3334261-1-alok.a.tiwari@oracle.com> On Sat, May 31, 2025 at 12:51:58AM -0700, Alok Tiwari wrote: > This patch corrects several typographical issues and improves phrasing > in memory-devices.rst: > > - Fixes duplicate word ("1 one") and adjusts phrasing for clarity. > - Adds missing hyphen in "on-device". > - Corrects "a give memory device" to "a given memory device". > - fix singular/plural "decoder resource" -> "decoder resources". > - Clarifies "spans to Host Bridges" -> "spans two Host Bridges". > > These changes improve readability and accuracy of the documentation. > > Signed-off-by: Alok Tiwari > --- > Documentation/driver-api/cxl/memory-devices.rst | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentation/driver-api/cxl/memory-devices.rst > index d732c42526df..e9e2952a967d 100644 > --- a/Documentation/driver-api/cxl/memory-devices.rst > +++ b/Documentation/driver-api/cxl/memory-devices.rst > @@ -29,8 +29,8 @@ Platform firmware enumerates a menu of interleave options at the "CXL root port" > (Linux term for the top of the CXL decode topology). From there, PCIe topology > dictates which endpoints can participate in which Host Bridge decode regimes. > Each PCIe Switch in the path between the root and an endpoint introduces a point > -at which the interleave can be split. For example platform firmware may say at a > -given range only decodes to 1 one Host Bridge, but that Host Bridge may in turn > +at which the interleave can be split. For example, platform firmware may say at a ^^^^ If you wouldn't mind, can you also change: "at a" - > "a" Otherwise Reviewed-by: Gregory Price