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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?a2nZekxedlYaOJkbu7oqvSnkedrlJWGzON5rSCVS+QnKoXXpoSoWzSTIORKj?= =?us-ascii?Q?hjSIoGaQ7NT3jrkFkLCXfYaOy2UNeeYKCul41kCvn6OvHBZuuTG7cDYdsUMk?= =?us-ascii?Q?1h5YYSCME5bZR4k6bLsdUGaGfssZA1Q/xUBN/uko6270MokbtrBDoOM2ackq?= =?us-ascii?Q?lVTEE2lKnWZTmVYjbqfAEDOdiKmd7cmjAJpxCEgZy5d6wvfCBv92J+nqmft9?= =?us-ascii?Q?yNYq6XYysFPq//SnTd+jQFLmV7aFeqpftN7SE2OXPXXKjYbb6uz/6gmyjIDa?= =?us-ascii?Q?mFAnEPL6tkwHqd6PM3pBsGcLfeOXCiai5KdgOJh8DmnkGocPOGTNoz9CQ51F?= =?us-ascii?Q?RMzcnuCPKB/ol1m6oDclG/dJJpdEP5ArYHYWyWcwRxtCUoVKbhSSd/JZ2YRT?= =?us-ascii?Q?ejfhdMqxrS0LNo5yMqKGYYwqkJp/HZg0udjxxu4iAj85/OGlbEdPB6uYoCbe?= =?us-ascii?Q?zLhuhCF+GIaKwx5LFihGh+MiO2/mS26flvvClpfSHxHf3JLIMo52gYnvrzKI?= =?us-ascii?Q?FWymiX3ctLJSRWXBiiL7YJAOa5BmgB8SyYRrYKzyU1FhXW11XG/637NaAr2N?= =?us-ascii?Q?AbqsS26AvPaMfII1q9Mp6bWp3VzHimH64utk2QXiWFfaFOdFYhZnQuauENJ1?= =?us-ascii?Q?o9JnVxaYekmXjmSqPKlj6FrQA/qFrBBvM8d4X4V7dedzV54ya4vAF7E/8fdu?= =?us-ascii?Q?+QjhfyyjYagvpmIvkowY5+LRXw0OzpdJhCKcwLxEKbUVW6te04scTzP8Qpkq?= =?us-ascii?Q?ehDalrHjsuX6VHJE2x4UDm9jDouXNqmrW5g42aiOD33qVPHB2tHGcGpFmJ1P?= =?us-ascii?Q?vxx+u6y9pMXS2rFEylDai60V0Zca91BofRfoJiys+ZVv6yHOy2+GeazrkfC+?= =?us-ascii?Q?jG+ej152HZdh+WPczS5U4KM+7HdUu5eOLvG1LcsoGhA40dVbUz4Wxi3Ou11+?= =?us-ascii?Q?WQa+g/gekvr1YS+wSuFnZYLIhoJswpzxSynd7x7vPRRK5yugj1DAGp8xEVyQ?= =?us-ascii?Q?GYSsi9IcGW8/uFGI7TGFaGNVJt7T9b475radOMu1bUYNhcB/LM6ej5lj2Rh7?= =?us-ascii?Q?dpwDq496HA3GH/noOJeX0/yBTdcAGwKldzqANpiZX1D0xDKJWZm9HFlwmuXH?= =?us-ascii?Q?HJaOK3cQndqB5Tm/FozkTTd4OTLKHfqn95yxxrzdlUONGcPaIXzydUBYkIk/?= =?us-ascii?Q?r15+EUfADyTrIZitTEeE8zn+kDaHQIPDRLV3SEUrR5YGJSOP3RI+XOmUCcra?= =?us-ascii?Q?1ruGYzaXO8SHsOVBio9LYnQUwC3iKyDcDPBJ7BCFUbyWhlN7H2XY1w5VJOAm?= =?us-ascii?Q?l6ERLxklubIeU47dbgDc6EZ69DKkwvlK+mCr4irsDOWylwyWZITvkosaYTH6?= =?us-ascii?Q?0q9s34tkix4b2PyG1rxhxWSTQqfQqJjOhSWZjg3O8g1BywvtZtXLTTnn8ooc?= =?us-ascii?Q?qA4/nFCOlRyik5YCWlcVv6Bmww3zs0vFX3ABAIqRDl0psF86udJyfOLF24Ye?= =?us-ascii?Q?Alm/3/PW7/D3QwKe0nCCGweCTot3Cq/0jpk6QQQR8APQmWJ+WRbAlGbm3is7?= =?us-ascii?Q?lNt88gTpInWMZ3fjkTo8lYou5IRVboYgIMK/m8Ix?= X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-Network-Message-Id: 45fe1345-7b64-467e-8d1e-08dde167e779 X-MS-Exchange-CrossTenant-AuthSource: CYYPR12MB8750.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2025 10:37:33.9659 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: X2li81eC/xiyf8TVPOyDcKvAuxyNyE9clY0kwQTliw97zMv/Uj5SqCPvIhrj8nd2WsXSRSj+tp7hsMM+Im65yA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB5887 On 14.08.25 15:21:44, Dave Jiang wrote: > This patch moves the port register setup to when the first dport appears > via the memdev probe path. At this point, the CXL link should be > established and the register access is expected to succeed. This change > addresses an error message observed when PCIe hotplug is enabled on > an Intel platform. The error messages "cxl portN: Couldn't locate the > CXL.cache and CXL.mem capability array header" is observed for the > hostbridge during cxl_acpi driver probe. If the cxl_acpi module > probe is running before the CXL link between the endpoint device and the > RP is established, then the platform may not have exposed DVSEC ID 3 > and/or DVSEC ID 7 blocks which will trigger the error message. This > behavior is defined by the spec and not a hardware quirk. > > This change also needs the dport enumeration to be moved to the memdev > probe path in order to address the issue. This change is just part of > the code refactoring and is not a wholly contained fix itself. > > Suggested-by: Dan Williamsn > Signed-off-by: Dave Jiang > --- > drivers/cxl/core/port.c | 16 +++++++++++++--- > drivers/cxl/cxl.h | 2 ++ > 2 files changed, 15 insertions(+), 3 deletions(-) > > diff --git a/drivers/cxl/core/port.c b/drivers/cxl/core/port.c > index 48e76673aaf3..25209952f469 100644 > --- a/drivers/cxl/core/port.c > +++ b/drivers/cxl/core/port.c > @@ -867,9 +867,7 @@ static int cxl_port_add(struct cxl_port *port, > if (rc) > return rc; > > - rc = cxl_port_setup_regs(port, component_reg_phys); > - if (rc) > - return rc; > + port->component_reg_phys = component_reg_phys; > } else { > rc = dev_set_name(dev, "root%d", port->id); > if (rc) > @@ -1200,6 +1198,18 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, > > cxl_debugfs_create_dport_dir(dport); > > + /* > + * Setup port register if this is the first dport showed up. Having > + * a dport also means that there is at least 1 active link. > + */ > + if (port->nr_dports == 1 && > + port->component_reg_phys != CXL_RESOURCE_NONE) { > + rc = cxl_port_setup_regs(port, port->component_reg_phys); All that delays decoder enablement and visibility in sysfs. I think we need a different approach to handle late CHBRC availablity. Let's see your response to my other mail. -Robert > + if (rc) > + return ERR_PTR(rc); > + port->component_reg_phys = CXL_RESOURCE_NONE; > + } > + > return dport; > } > > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > index 4b858f3d44c6..87a905db5ffb 100644 > --- a/drivers/cxl/cxl.h > +++ b/drivers/cxl/cxl.h > @@ -599,6 +599,7 @@ struct cxl_dax_region { > * @cdat: Cached CDAT data > * @cdat_available: Should a CDAT attribute be available in sysfs > * @pci_latency: Upstream latency in picoseconds > + * @component_reg_phys: Physical address of component register > */ > struct cxl_port { > struct device dev; > @@ -622,6 +623,7 @@ struct cxl_port { > } cdat; > bool cdat_available; > long pci_latency; > + resource_size_t component_reg_phys; > }; > > /** > -- > 2.50.1 >