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Tue, 9 Sep 2025 21:43:34 +0000 Date: Tue, 9 Sep 2025 14:43:26 -0700 From: Alison Schofield To: Dave Jiang CC: Davidlohr Bueso , Jonathan Cameron , Vishal Verma , "Ira Weiny" , Dan Williams , Subject: Re: [PATCH v2] cxl/acpi: Limit XOR map application based on host bridge ways Message-ID: References: <20250813032918.2899852-1-alison.schofield@intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-ClientProxiedBy: BYAPR02CA0058.namprd02.prod.outlook.com (2603:10b6:a03:54::35) To DS4PPF0BAC23327.namprd11.prod.outlook.com (2603:10b6:f:fc02::9) Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS4PPF0BAC23327:EE_|PH0PR11MB4853:EE_ X-MS-Office365-Filtering-Correlation-Id: de7433b3-299e-4534-14c2-08ddefe9ecfb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|376014|1800799024; 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The story above is true, but I missed the piece that came before. The CXL driver actually stores a customized list of xormaps per root decoder (see cxl_parse_cxims()) so there cannot be any extra maps in it's root decoder platform data (struct cxl_cxims_data). This came up during testing when I moved out of tree code for address translation into the cxl-translate test module. In that case there was only one struct cxl_cxmis_data, not multiples per region interleave (or per root decoder) and so I was alarmed when all the xormaps were always applied by the CXL driver. Now I know that is working as designed, and it is the test module that needs to change. My apologies for crying wolf! > > > --- > > > > Changes in v2: > > - Use CXL_DECODER_MAX_INTERLEAVE in hbiw_to_nr_maps[] definition (Dan) > > - Rebase onto latest cxl/next > > > > > > drivers/cxl/acpi.c | 18 +++++++++++++++--- > > 1 file changed, 15 insertions(+), 3 deletions(-) > > > > diff --git a/drivers/cxl/acpi.c b/drivers/cxl/acpi.c > > index f1625212b08b..26c494704437 100644 > > --- a/drivers/cxl/acpi.c > > +++ b/drivers/cxl/acpi.c > > @@ -16,19 +16,31 @@ struct cxl_cxims_data { > > u64 xormaps[] __counted_by(nr_maps); > > }; > > > > +/* > > + * There is one CXIMS, therefore one set of XOR maps, that all CXL Windows with > > + * the same host bridge granularity share. The number of maps to apply at address > > + * translation is based on the Host Bridge interleave ways of the CXL Window. > > + * CXL Specification 3.2 Section 9.18.1.4 and Table 9-22. > > + */ > > +#define HBIW_TO_NR_MAPS_SIZE (CXL_DECODER_MAX_INTERLEAVE + 1) > > + > > +static const int hbiw_to_nr_maps[HBIW_TO_NR_MAPS_SIZE] = { > > + [1] = 0, [2] = 1, [3] = 0, [4] = 2, [6] = 1, [8] = 3, [12] = 2, [16] = 4 > > +}; > > + > > static const guid_t acpi_cxl_qtg_id_guid = > > GUID_INIT(0xF365F9A6, 0xA7DE, 0x4071, > > 0xA6, 0x6A, 0xB4, 0x0C, 0x0B, 0x4F, 0x8E, 0x52); > > > > static u64 cxl_apply_xor_maps(struct cxl_root_decoder *cxlrd, u64 addr) > > { > > + int nr_maps_to_apply = hbiw_to_nr_maps[cxlrd->cxlsd.nr_targets]; > > struct cxl_cxims_data *cximsd = cxlrd->platform_data; > > - int hbiw = cxlrd->cxlsd.nr_targets; > > u64 val; > > int pos; > > > > /* No xormaps for host bridge interleave ways of 1 or 3 */ > > - if (hbiw == 1 || hbiw == 3) > > + if (!nr_maps_to_apply) > > return addr; > > > > /* > > @@ -50,7 +62,7 @@ static u64 cxl_apply_xor_maps(struct cxl_root_decoder *cxlrd, u64 addr) > > * bits results in val==0, if odd the XOR result is val==1. > > */ > > > > - for (int i = 0; i < cximsd->nr_maps; i++) { > > + for (int i = 0; i < nr_maps_to_apply; i++) { > > if (!cximsd->xormaps[i]) > > continue; > > pos = __ffs(cximsd->xormaps[i]); > > > > base-commit: d9412f08e25a5b66f9021739c090cc9b8f1089b1 >