From: Alison Schofield <alison.schofield@intel.com>
To: Dave Jiang <dave.jiang@intel.com>
Cc: <linux-cxl@vger.kernel.org>, <nvdimm@lists.linux.dev>,
<dave@stgolabs.net>, <jonathan.cameron@huawei.com>,
<vishal.l.verma@intel.com>, <ira.weiny@intel.com>,
<dan.j.williams@intel.com>
Subject: Re: [NDCTL PATCH v2 1/2] cxl/test: Add test for extended linear cache support
Date: Tue, 2 Dec 2025 14:22:52 -0800 [thread overview]
Message-ID: <aS9mvJI9FW--YF4Z@aschofie-mobl2.lan> (raw)
In-Reply-To: <aS9lExT_uyhyA8nd@aschofie-mobl2.lan>
On Tue, Dec 02, 2025 at 02:15:47PM -0800, Alison Schofield wrote:
> On Thu, Nov 20, 2025 at 05:20:17PM -0700, Dave Jiang wrote:
> > Add a unit test that verifies the extended linear cache setup paths
> > in the kernel driver. cxl_test provides a mock'd version. The test
> > verifies the sysfs attribute that indicates extended linear cache support
> > is correctly reported. It also verifies the sizing and offset of the
> > regions and decoders.
> >
> > The expecation is that CFMWS covers the entire extended linear cache
> > region. The first part is DRAM and second part is CXL memory in a 1:1
> > setup. The start base for hardware decoders should be offsetted by the
> > DRAM size.
>
> Thanks!
>
> With this [ as: remove CONFIG_TRACE check ]
>
> Applied to pending: https://github.com/pmem/ndctl/commit/39085f7
Here is the corrected commit id:
https://github.com/pmem/ndctl/commit/6834cd1
>
> >
>
next prev parent reply other threads:[~2025-12-02 22:23 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-11-21 0:20 [NDCTL PATCH v2 0/2] cxl: Add tests for extended linear cache support Dave Jiang
2025-11-21 0:20 ` [NDCTL PATCH v2 1/2] cxl/test: Add test " Dave Jiang
2025-12-02 22:15 ` Alison Schofield
2025-12-02 22:22 ` Alison Schofield [this message]
2025-11-21 0:20 ` [NDCTL PATCH v2 2/2] cxl/test: Add support for poison test for ELC Dave Jiang
2025-12-02 22:21 ` Alison Schofield
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