From: Alison Schofield <alison.schofield@intel.com>
To: Srirangan Madhavan <smadhavan@nvidia.com>
Cc: "dave@stgolabs.net" <dave@stgolabs.net>,
"jonathan.cameron@huawei.com" <Jonathan.Cameron@huawei.com>,
"dave.jiang@intel.com" <dave.jiang@intel.com>,
"vishal.l.verma@intel.com" <vishal.l.verma@intel.com>,
"ira.weiny@intel.com" <ira.weiny@intel.com>,
"dan.j.williams@intel.com" <dan.j.williams@intel.com>,
"bhelgaas@google.com" <bhelgaas@google.com>,
"ming.li@zohomail.com" <ming.li@zohomail.com>,
"rrichter@amd.com" <rrichter@amd.com>,
"Smita.KoralahalliChannabasappa@amd.com"
<Smita.KoralahalliChannabasappa@amd.com>,
"huaisheng.ye@intel.com" <huaisheng.ye@intel.com>,
"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
Vishal Aslot <vaslot@nvidia.com>,
Vikram Sethi <vsethi@nvidia.com>,
Shanker Donthineni <sdonthineni@nvidia.com>,
Vidya Sagar <vidyas@nvidia.com>, Matt Ochs <mochs@nvidia.com>,
Jason Sequeira <jsequeira@nvidia.com>
Subject: Re: [PATCH v3 0/10] CXL reset support for Type 2 devices
Date: Tue, 20 Jan 2026 16:30:08 -0800 [thread overview]
Message-ID: <aXAeEHMVY1Jf7oeI@aschofie-mobl2.lan> (raw)
In-Reply-To: <CY5PR12MB6226EE35D88E6F4442572D1CC389A@CY5PR12MB6226.namprd12.prod.outlook.com>
On Tue, Jan 20, 2026 at 10:30:51PM +0000, Srirangan Madhavan wrote:
> Hi Alison,
>
> Thank you for the heads‑up. I’ve respun the series as v4 and rebased it on pci/next as mentioned by the testbot. The v4 changes are limited to build‑fixes from the bot report + Reported‑by/Closes on the reset method patch. And the reproduce steps from testbot clear locally for me now.
pci/next? Ah, that's different than what we typically do in drivers/cxl.
I was expecting a mainline base commit - like 6.19-rc6. Anyway v4 still
has conflicts w that. What is the dependency that is on pci/next? I can
see the impact, appended below, but pci/next has a slew of things since
6.19-rc1.
drivers/cxl/pci.c:1090:6: error: redefinition of ‘cxl_is_type2_device’
1090 | bool cxl_is_type2_device(struct pci_dev *pdev)
| ^~~~~~~~~~~~~~~~~~~
In file included from drivers/cxl/pci.c:11:
./include/linux/pci.h:1472:20: note: previous definition of ‘cxl_is_type2_device’ with type ‘bool(struct pci_dev *)’ {aka ‘_Bool(struct pci_dev *)’}
1472 | static inline bool cxl_is_type2_device(struct pci_dev *dev)
| ^~~~~~~~~~~~~~~~~~~
drivers/cxl/pci.c: In function ‘cxl_check_region_driver_bound’:
drivers/cxl/pci.c:1419:28: error: ‘cxl_region_rwsem’ undeclared (first use in this function); did you mean ‘cxl_region_ref’?
1419 | guard(rwsem_read)(&cxl_region_rwsem);
| ^~~~~~~~~~~~~~~~
| cxl_region_ref
drivers/cxl/pci.c:1419:28: note: each undeclared identifier is reported only once for each function it appears in
drivers/cxl/pci.c:1420:41: error: ‘struct cxl_region’ has no member named ‘driver’
1420 | if (cxld->region && cxld->region->driver)
| ^~
drivers/cxl/pci.c: In function ‘cxl_decoder_kill_region_iter’:
drivers/cxl/pci.c:1437:9: error: implicit declaration of function ‘cxl_decoder_kill_region_locked’; did you mean ‘cxl_decoder_kill_region_iter’? [-Werror=implicit-function-declaration]
1437 | cxl_decoder_kill_region_locked(cxled);
| ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
| cxl_decoder_kill_region_iter
drivers/cxl/pci.c: In function ‘cxl_region_flush_device_caches’:
drivers/cxl/pci.c:1504:53: error: ‘struct cxl_dev_state’ has no member named ‘pdev’; did you mean ‘dev’?
1504 | if (!target_cxlds || !target_cxlds->pdev)
| ^~~~
| dev
drivers/cxl/pci.c:1507:35: error: ‘struct cxl_dev_state’ has no member named ‘pdev’; did you mean ‘dev’?
1507 | if (target_cxlds->pdev != target_pdev)
| ^~~~
| dev
drivers/cxl/pci.c: In function ‘cxl_reset_prepare_memdev’:
drivers/cxl/pci.c:1548:21: error: ‘cxl_region_rwsem’ undeclared (first use in this function); did you mean ‘cxl_region_ref’?
1548 | down_write(&cxl_region_rwsem);
| ^~~~~~~~~~~~~~~~
| cxl_region_ref
In file included from ./include/linux/spinlock.h:63,
from ./include/linux/sched.h:37,
from ./include/linux/percpu.h:12,
from ./arch/x86/include/asm/msr.h:16,
from ./arch/x86/include/asm/tsc.h:11,
from ./arch/x86/include/asm/timex.h:6,
from ./include/linux/timex.h:67,
from ./include/linux/time32.h:13,
from ./include/linux/time.h:60,
from ./include/linux/stat.h:19,
from ./include/linux/module.h:13,
from drivers/cxl/pci.c:6:
drivers/cxl/pci.c: In function ‘cxl_reset_cleanup_memdev’:
drivers/cxl/pci.c:1585:35: error: ‘cxl_region_rwsem’ undeclared (first use in this function); did you mean ‘cxl_region_ref’?
1585 | if (lockdep_is_held_type(&cxl_region_rwsem, -1))
| ^~~~~~~~~~~~~~~~
./include/linux/lockdep.h:253:61: note: in definition of macro ‘lockdep_is_held_type’
253 | fine lockdep_is_held_type(lock, r) lock_is_held_type(&(lock)->dep_map, (r))
| ^~~~
drivers/cxl/pci.c: At top level:
drivers/cxl/pci.c:1665:5: error: redefinition of ‘cxl_reset_prepare_device’
1665 | int cxl_reset_prepare_device(struct pci_dev *pdev)
| ^~~~~~~~~~~~~~~~~~~~~~~~
./include/linux/pci.h:1477:19: note: previous definition of ‘cxl_reset_prepare_device’ with type ‘int(struct pci_dev *)’
1477 | static inline int cxl_reset_prepare_device(struct pci_dev *pdev)
| ^~~~~~~~~~~~~~~~~~~~~~~~
drivers/cxl/pci.c:1696:6: error: redefinition of ‘cxl_reset_cleanup_device’
1696 | void cxl_reset_cleanup_device(struct pci_dev *pdev)
| ^~~~~~~~~~~~~~~~~~~~~~~~
./include/linux/pci.h:1482:20: note: previous definition of ‘cxl_reset_cleanup_device’ with type ‘void(struct pci_dev *)’
1482 | static inline void cxl_reset_cleanup_device(struct pci_dev *pdev)
| ^~~~~~~~~~~~~~~~~~~~~~~~
cc1: some warnings being treated as errors
prev parent reply other threads:[~2026-01-21 0:30 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-01-16 1:41 [PATCH v3 0/10] CXL reset support for Type 2 devices smadhavan
2026-01-16 1:41 ` [PATCH v3 1/10] cxl: move DVSEC defines to cxl pci header smadhavan
2026-01-16 1:41 ` [PATCH v3 2/10] PCI: switch CXL port DVSEC defines smadhavan
2026-01-16 1:41 ` [PATCH v3 3/10] cxl: add type 2 helper and reset DVSEC bits smadhavan
2026-01-16 1:41 ` [PATCH v3 4/10] PCI: add CXL reset method smadhavan
2026-01-17 13:56 ` kernel test robot
2026-01-17 14:28 ` kernel test robot
2026-01-16 1:41 ` [PATCH v3 5/10] cxl: add reset prepare and region teardown smadhavan
2026-01-16 1:41 ` [PATCH v3 6/10] PCI: wire CXL reset prepare/cleanup smadhavan
2026-01-16 1:41 ` [PATCH v3 7/10] cxl: add host cache flush and multi-function reset smadhavan
2026-01-16 1:41 ` [PATCH v3 8/10] cxl: add DVSEC config save/restore smadhavan
2026-01-16 1:41 ` [PATCH v3 9/10] PCI: save/restore CXL config around reset smadhavan
2026-01-16 1:41 ` [PATCH v3 10/10] cxl: add HDM decoder and IDE save/restore smadhavan
2026-01-18 22:29 ` [PATCH v3 0/10] CXL reset support for Type 2 devices Alison Schofield
2026-01-20 22:33 ` Srirangan Madhavan
[not found] ` <CY5PR12MB6226EE35D88E6F4442572D1CC389A@CY5PR12MB6226.namprd12.prod.outlook.com>
2026-01-21 0:30 ` Alison Schofield [this message]
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