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[96.255.20.138]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-5070d6a2676sm95492671cf.18.2026.02.24.08.05.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 Feb 2026 08:05:40 -0800 (PST) Date: Tue, 24 Feb 2026 11:05:39 -0500 From: Gregory Price To: alejandro.lucero-palau@amd.com Cc: linux-cxl@vger.kernel.org, dan.j.williams@intel.com, dave.jiang@intel.com, Alejandro Lucero Subject: Re: [PATCH v1 2/3] cxl/region: Factor out interleave ways setup Message-ID: References: <20260224152645.3441489-1-alejandro.lucero-palau@amd.com> <20260224152645.3441489-3-alejandro.lucero-palau@amd.com> Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260224152645.3441489-3-alejandro.lucero-palau@amd.com> On Tue, Feb 24, 2026 at 03:26:44PM +0000, alejandro.lucero-palau@amd.com wrote: > From: Alejandro Lucero > > Region creation based on Type3 devices is triggered from user space > allowing memory combination through interleaving. > > In preparation for kernel driven region creation, that is Type2 drivers > triggering region creation backed with its advertised CXL memory, factor > out a common helper from the user-sysfs region setup for interleave ways. > > Signed-off-by: Alejandro Lucero Reviewed-by: Gregory Price