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Mon, 23 Mar 2026 02:37:31 +0000 Date: Sun, 22 Mar 2026 19:37:28 -0700 From: Alison Schofield To: Gregory Price CC: , , , , , , , , Subject: Re: [PATCH v4 1/3] cxl/core/region: move pmem region driver logic into region_pmem.c Message-ID: References: <20260322131638.3636725-1-gourry@gourry.net> <20260322131638.3636725-2-gourry@gourry.net> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260322131638.3636725-2-gourry@gourry.net> X-ClientProxiedBy: BY3PR10CA0025.namprd10.prod.outlook.com (2603:10b6:a03:255::30) To DS4PPF0BAC23327.namprd11.prod.outlook.com (2603:10b6:f:fc02::9) Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS4PPF0BAC23327:EE_|SAWPR11MB9781:EE_ X-MS-Office365-Filtering-Correlation-Id: 8cd78f64-c1aa-4c46-c72c-08de888521ea X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|366016|1800799024|18002099003|22082099003|56012099003|7053199007; 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Move the pmem region driver logic from region.c into > region_pmem.c make it clear that this code only applies to pmem regions. > > No functional changes. This always adds region_pmem.o regardless of CONFIG_CXL_PMEM. Are you heading towards conditionally compiling, where region_pmem.o is omitted if !CONFIG_CXL_PMEM? Similar question for region_dax.o --Alison > > Signed-off-by: Gregory Price > --- > drivers/cxl/core/Makefile | 1 + > drivers/cxl/core/core.h | 1 + > drivers/cxl/core/region.c | 184 -------------------------------- > drivers/cxl/core/region_pmem.c | 189 +++++++++++++++++++++++++++++++++ > 4 files changed, 191 insertions(+), 184 deletions(-) > create mode 100644 drivers/cxl/core/region_pmem.c > > diff --git a/drivers/cxl/core/Makefile b/drivers/cxl/core/Makefile > index a639a9499972..d1484a0e5eb4 100644 > --- a/drivers/cxl/core/Makefile > +++ b/drivers/cxl/core/Makefile > @@ -16,6 +16,7 @@ cxl_core-y += pmu.o > cxl_core-y += cdat.o > cxl_core-$(CONFIG_TRACING) += trace.o > cxl_core-$(CONFIG_CXL_REGION) += region.o > +cxl_core-$(CONFIG_CXL_REGION) += region_pmem.o > cxl_core-$(CONFIG_CXL_MCE) += mce.o > cxl_core-$(CONFIG_CXL_FEATURES) += features.o > cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) += edac.o > diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h > index 5539e941782f..ef03966eeabd 100644 > --- a/drivers/cxl/core/core.h > +++ b/drivers/cxl/core/core.h > @@ -50,6 +50,7 @@ int cxl_get_poison_by_endpoint(struct cxl_port *port); > struct cxl_region *cxl_dpa_to_region(const struct cxl_memdev *cxlmd, u64 dpa); > u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, const struct cxl_memdev *cxlmd, > u64 dpa); > +int devm_cxl_add_pmem_region(struct cxl_region *cxlr); > > #else > static inline u64 cxl_dpa_to_hpa(struct cxl_region *cxlr, > diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c > index f24b7e754727..72aee1408efb 100644 > --- a/drivers/cxl/core/region.c > +++ b/drivers/cxl/core/region.c > @@ -2781,46 +2781,6 @@ static ssize_t delete_region_store(struct device *dev, > } > DEVICE_ATTR_WO(delete_region); > > -static void cxl_pmem_region_release(struct device *dev) > -{ > - struct cxl_pmem_region *cxlr_pmem = to_cxl_pmem_region(dev); > - int i; > - > - for (i = 0; i < cxlr_pmem->nr_mappings; i++) { > - struct cxl_memdev *cxlmd = cxlr_pmem->mapping[i].cxlmd; > - > - put_device(&cxlmd->dev); > - } > - > - kfree(cxlr_pmem); > -} > - > -static const struct attribute_group *cxl_pmem_region_attribute_groups[] = { > - &cxl_base_attribute_group, > - NULL, > -}; > - > -const struct device_type cxl_pmem_region_type = { > - .name = "cxl_pmem_region", > - .release = cxl_pmem_region_release, > - .groups = cxl_pmem_region_attribute_groups, > -}; > - > -bool is_cxl_pmem_region(struct device *dev) > -{ > - return dev->type == &cxl_pmem_region_type; > -} > -EXPORT_SYMBOL_NS_GPL(is_cxl_pmem_region, "CXL"); > - > -struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) > -{ > - if (dev_WARN_ONCE(dev, !is_cxl_pmem_region(dev), > - "not a cxl_pmem_region device\n")) > - return NULL; > - return container_of(dev, struct cxl_pmem_region, dev); > -} > -EXPORT_SYMBOL_NS_GPL(to_cxl_pmem_region, "CXL"); > - > struct cxl_poison_context { > struct cxl_port *port; > int part; > @@ -3476,64 +3436,6 @@ static int region_offset_to_dpa_result(struct cxl_region *cxlr, u64 offset, > return -ENXIO; > } > > -static struct lock_class_key cxl_pmem_region_key; > - > -static int cxl_pmem_region_alloc(struct cxl_region *cxlr) > -{ > - struct cxl_region_params *p = &cxlr->params; > - struct cxl_nvdimm_bridge *cxl_nvb; > - struct device *dev; > - int i; > - > - guard(rwsem_read)(&cxl_rwsem.region); > - if (p->state != CXL_CONFIG_COMMIT) > - return -ENXIO; > - > - struct cxl_pmem_region *cxlr_pmem __free(kfree) = > - kzalloc_flex(*cxlr_pmem, mapping, p->nr_targets); > - if (!cxlr_pmem) > - return -ENOMEM; > - > - cxlr_pmem->hpa_range.start = p->res->start; > - cxlr_pmem->hpa_range.end = p->res->end; > - > - /* Snapshot the region configuration underneath the cxl_rwsem.region */ > - cxlr_pmem->nr_mappings = p->nr_targets; > - for (i = 0; i < p->nr_targets; i++) { > - struct cxl_endpoint_decoder *cxled = p->targets[i]; > - struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); > - struct cxl_pmem_region_mapping *m = &cxlr_pmem->mapping[i]; > - > - /* > - * Regions never span CXL root devices, so by definition the > - * bridge for one device is the same for all. > - */ > - if (i == 0) { > - cxl_nvb = cxl_find_nvdimm_bridge(cxlmd->endpoint); > - if (!cxl_nvb) > - return -ENODEV; > - cxlr->cxl_nvb = cxl_nvb; > - } > - m->cxlmd = cxlmd; > - get_device(&cxlmd->dev); > - m->start = cxled->dpa_res->start; > - m->size = resource_size(cxled->dpa_res); > - m->position = i; > - } > - > - dev = &cxlr_pmem->dev; > - device_initialize(dev); > - lockdep_set_class(&dev->mutex, &cxl_pmem_region_key); > - device_set_pm_not_required(dev); > - dev->parent = &cxlr->dev; > - dev->bus = &cxl_bus_type; > - dev->type = &cxl_pmem_region_type; > - cxlr_pmem->cxlr = cxlr; > - cxlr->cxlr_pmem = no_free_ptr(cxlr_pmem); > - > - return 0; > -} > - > static void cxl_dax_region_release(struct device *dev) > { > struct cxl_dax_region *cxlr_dax = to_cxl_dax_region(dev); > @@ -3597,92 +3499,6 @@ static struct cxl_dax_region *cxl_dax_region_alloc(struct cxl_region *cxlr) > return cxlr_dax; > } > > -static void cxlr_pmem_unregister(void *_cxlr_pmem) > -{ > - struct cxl_pmem_region *cxlr_pmem = _cxlr_pmem; > - struct cxl_region *cxlr = cxlr_pmem->cxlr; > - struct cxl_nvdimm_bridge *cxl_nvb = cxlr->cxl_nvb; > - > - /* > - * Either the bridge is in ->remove() context under the device_lock(), > - * or cxlr_release_nvdimm() is cancelling the bridge's release action > - * for @cxlr_pmem and doing it itself (while manually holding the bridge > - * lock). > - */ > - device_lock_assert(&cxl_nvb->dev); > - cxlr->cxlr_pmem = NULL; > - cxlr_pmem->cxlr = NULL; > - device_unregister(&cxlr_pmem->dev); > -} > - > -static void cxlr_release_nvdimm(void *_cxlr) > -{ > - struct cxl_region *cxlr = _cxlr; > - struct cxl_nvdimm_bridge *cxl_nvb = cxlr->cxl_nvb; > - > - scoped_guard(device, &cxl_nvb->dev) { > - if (cxlr->cxlr_pmem) > - devm_release_action(&cxl_nvb->dev, cxlr_pmem_unregister, > - cxlr->cxlr_pmem); > - } > - cxlr->cxl_nvb = NULL; > - put_device(&cxl_nvb->dev); > -} > - > -/** > - * devm_cxl_add_pmem_region() - add a cxl_region-to-nd_region bridge > - * @cxlr: parent CXL region for this pmem region bridge device > - * > - * Return: 0 on success negative error code on failure. > - */ > -static int devm_cxl_add_pmem_region(struct cxl_region *cxlr) > -{ > - struct cxl_pmem_region *cxlr_pmem; > - struct cxl_nvdimm_bridge *cxl_nvb; > - struct device *dev; > - int rc; > - > - rc = cxl_pmem_region_alloc(cxlr); > - if (rc) > - return rc; > - cxlr_pmem = cxlr->cxlr_pmem; > - cxl_nvb = cxlr->cxl_nvb; > - > - dev = &cxlr_pmem->dev; > - rc = dev_set_name(dev, "pmem_region%d", cxlr->id); > - if (rc) > - goto err; > - > - rc = device_add(dev); > - if (rc) > - goto err; > - > - dev_dbg(&cxlr->dev, "%s: register %s\n", dev_name(dev->parent), > - dev_name(dev)); > - > - scoped_guard(device, &cxl_nvb->dev) { > - if (cxl_nvb->dev.driver) > - rc = devm_add_action_or_reset(&cxl_nvb->dev, > - cxlr_pmem_unregister, > - cxlr_pmem); > - else > - rc = -ENXIO; > - } > - > - if (rc) > - goto err_bridge; > - > - /* @cxlr carries a reference on @cxl_nvb until cxlr_release_nvdimm */ > - return devm_add_action_or_reset(&cxlr->dev, cxlr_release_nvdimm, cxlr); > - > -err: > - put_device(dev); > -err_bridge: > - put_device(&cxl_nvb->dev); > - cxlr->cxl_nvb = NULL; > - return rc; > -} > - > static void cxlr_dax_unregister(void *_cxlr_dax) > { > struct cxl_dax_region *cxlr_dax = _cxlr_dax; > diff --git a/drivers/cxl/core/region_pmem.c b/drivers/cxl/core/region_pmem.c > new file mode 100644 > index 000000000000..138c373a5700 > --- /dev/null > +++ b/drivers/cxl/core/region_pmem.c > @@ -0,0 +1,189 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* Copyright(c) 2022 Intel Corporation. All rights reserved. */ > +#include > +#include > +#include > +#include > +#include "core.h" > + > +static void cxl_pmem_region_release(struct device *dev) > +{ > + struct cxl_pmem_region *cxlr_pmem = to_cxl_pmem_region(dev); > + int i; > + > + for (i = 0; i < cxlr_pmem->nr_mappings; i++) { > + struct cxl_memdev *cxlmd = cxlr_pmem->mapping[i].cxlmd; > + > + put_device(&cxlmd->dev); > + } > + > + kfree(cxlr_pmem); > +} > + > +static const struct attribute_group *cxl_pmem_region_attribute_groups[] = { > + &cxl_base_attribute_group, > + NULL > +}; > + > +const struct device_type cxl_pmem_region_type = { > + .name = "cxl_pmem_region", > + .release = cxl_pmem_region_release, > + .groups = cxl_pmem_region_attribute_groups, > +}; > +bool is_cxl_pmem_region(struct device *dev) > +{ > + return dev->type == &cxl_pmem_region_type; > +} > +EXPORT_SYMBOL_NS_GPL(is_cxl_pmem_region, "CXL"); > + > +struct cxl_pmem_region *to_cxl_pmem_region(struct device *dev) > +{ > + if (dev_WARN_ONCE(dev, !is_cxl_pmem_region(dev), > + "not a cxl_pmem_region device\n")) > + return NULL; > + return container_of(dev, struct cxl_pmem_region, dev); > +} > +EXPORT_SYMBOL_NS_GPL(to_cxl_pmem_region, "CXL"); > +static struct lock_class_key cxl_pmem_region_key; > + > +static int cxl_pmem_region_alloc(struct cxl_region *cxlr) > +{ > + struct cxl_region_params *p = &cxlr->params; > + struct cxl_nvdimm_bridge *cxl_nvb; > + struct device *dev; > + int i; > + > + guard(rwsem_read)(&cxl_rwsem.region); > + if (p->state != CXL_CONFIG_COMMIT) > + return -ENXIO; > + > + struct cxl_pmem_region *cxlr_pmem __free(kfree) = > + kzalloc_flex(*cxlr_pmem, mapping, p->nr_targets); > + if (!cxlr_pmem) > + return -ENOMEM; > + > + cxlr_pmem->hpa_range.start = p->res->start; > + cxlr_pmem->hpa_range.end = p->res->end; > + > + /* Snapshot the region configuration underneath the cxl_rwsem.region */ > + cxlr_pmem->nr_mappings = p->nr_targets; > + for (i = 0; i < p->nr_targets; i++) { > + struct cxl_endpoint_decoder *cxled = p->targets[i]; > + struct cxl_memdev *cxlmd = cxled_to_memdev(cxled); > + struct cxl_pmem_region_mapping *m = &cxlr_pmem->mapping[i]; > + > + /* > + * Regions never span CXL root devices, so by definition the > + * bridge for one device is the same for all. > + */ > + if (i == 0) { > + cxl_nvb = cxl_find_nvdimm_bridge(cxlmd->endpoint); > + if (!cxl_nvb) > + return -ENODEV; > + cxlr->cxl_nvb = cxl_nvb; > + } > + m->cxlmd = cxlmd; > + get_device(&cxlmd->dev); > + m->start = cxled->dpa_res->start; > + m->size = resource_size(cxled->dpa_res); > + m->position = i; > + } > + > + dev = &cxlr_pmem->dev; > + device_initialize(dev); > + lockdep_set_class(&dev->mutex, &cxl_pmem_region_key); > + device_set_pm_not_required(dev); > + dev->parent = &cxlr->dev; > + dev->bus = &cxl_bus_type; > + dev->type = &cxl_pmem_region_type; > + cxlr_pmem->cxlr = cxlr; > + cxlr->cxlr_pmem = no_free_ptr(cxlr_pmem); > + > + return 0; > +} > + > +static void cxlr_pmem_unregister(void *_cxlr_pmem) > +{ > + struct cxl_pmem_region *cxlr_pmem = _cxlr_pmem; > + struct cxl_region *cxlr = cxlr_pmem->cxlr; > + struct cxl_nvdimm_bridge *cxl_nvb = cxlr->cxl_nvb; > + > + /* > + * Either the bridge is in ->remove() context under the device_lock(), > + * or cxlr_release_nvdimm() is cancelling the bridge's release action > + * for @cxlr_pmem and doing it itself (while manually holding the bridge > + * lock). > + */ > + device_lock_assert(&cxl_nvb->dev); > + cxlr->cxlr_pmem = NULL; > + cxlr_pmem->cxlr = NULL; > + device_unregister(&cxlr_pmem->dev); > +} > + > +static void cxlr_release_nvdimm(void *_cxlr) > +{ > + struct cxl_region *cxlr = _cxlr; > + struct cxl_nvdimm_bridge *cxl_nvb = cxlr->cxl_nvb; > + > + scoped_guard(device, &cxl_nvb->dev) { > + if (cxlr->cxlr_pmem) > + devm_release_action(&cxl_nvb->dev, cxlr_pmem_unregister, > + cxlr->cxlr_pmem); > + } > + cxlr->cxl_nvb = NULL; > + put_device(&cxl_nvb->dev); > +} > + > +/** > + * devm_cxl_add_pmem_region() - add a cxl_region-to-nd_region bridge > + * @cxlr: parent CXL region for this pmem region bridge device > + * > + * Return: 0 on success negative error code on failure. > + */ > +int devm_cxl_add_pmem_region(struct cxl_region *cxlr) > +{ > + struct cxl_pmem_region *cxlr_pmem; > + struct cxl_nvdimm_bridge *cxl_nvb; > + struct device *dev; > + int rc; > + > + rc = cxl_pmem_region_alloc(cxlr); > + if (rc) > + return rc; > + cxlr_pmem = cxlr->cxlr_pmem; > + cxl_nvb = cxlr->cxl_nvb; > + > + dev = &cxlr_pmem->dev; > + rc = dev_set_name(dev, "pmem_region%d", cxlr->id); > + if (rc) > + goto err; > + > + rc = device_add(dev); > + if (rc) > + goto err; > + > + dev_dbg(&cxlr->dev, "%s: register %s\n", dev_name(dev->parent), > + dev_name(dev)); > + > + scoped_guard(device, &cxl_nvb->dev) { > + if (cxl_nvb->dev.driver) > + rc = devm_add_action_or_reset(&cxl_nvb->dev, > + cxlr_pmem_unregister, > + cxlr_pmem); > + else > + rc = -ENXIO; > + } > + > + if (rc) > + goto err_bridge; > + > + /* @cxlr carries a reference on @cxl_nvb until cxlr_release_nvdimm */ > + return devm_add_action_or_reset(&cxlr->dev, cxlr_release_nvdimm, cxlr); > + > +err: > + put_device(dev); > +err_bridge: > + put_device(&cxl_nvb->dev); > + cxlr->cxl_nvb = NULL; > + return rc; > +} > -- > 2.53.0 >