From: Dave Jiang <dave.jiang@intel.com>
To: <linux-cxl@vger.kernel.org>
Cc: Dan Williams <dan.j.williams@intel.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>,
<ira.weiny@intel.com>, <vishal.l.verma@intel.com>,
<alison.schofield@intel.com>, <dave@stgolabs.net>
Subject: Re: [PATCH v14 18/19] cxl: Export sysfs attributes for memory device QoS class
Date: Mon, 18 Dec 2023 09:28:06 -0700 [thread overview]
Message-ID: <b564fba0-0390-41c3-adb2-27ac92fd8cd5@intel.com> (raw)
In-Reply-To: <2a2eb846-7e94-4e95-82d2-2187017b6d85@intel.com>
On 12/15/23 13:33, Dave Jiang wrote:
>
>
> On 12/13/23 09:43, Dave Jiang wrote:
>> Export qos_class sysfs attributes for the CXL memory device. The QoS clas
>> should show up as /sys/bus/cxl/devices/memX/ram/qos_class for the volatile
>> partition and /sys/bus/cxl/devices/memX/pmem/qos_class for the persistent
>> partition. The QTG ID is retrieved via _DSM after supplying the
>> calculated bandwidth and latency for the entire CXL path from device to
>> the CPU. This ID is used to match up to the root decoder QoS class to
>> determine which CFMWS the memory range of a hotplugged CXL mem device
>> should be assigned under.
>>
>> While there may be multiple DSMAS exported by the device CDAT, the driver
>> will only expose the first QTG ID per partition in sysfs for now. In the
>> future when multiple QTG IDs are necessary, they can be exposed. [1]
>>
>> [1]: https://lore.kernel.org/linux-cxl/167571650007.587790.10040913293130712882.stgit@djiang5-mobl3.local/T/#md2a47b1ead3e1ba08f50eab29a4af1aed1d215ab
>>
>> Suggested-by: Dan Williams <dan.j.williams@intel.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>> ---
>> v14:
>> - Move attribs to dev_groups (Dan)
>> - Update perf_prop_entry to cxl_dpa_perf (Dan)
>
> <snip>
>
> It's missing 2 lines due to rebase:
>
>
> diff --git a/drivers/cxl/mem.c b/drivers/cxl/mem.c
> index 5699d2c7d2ed..9b37a842c7ea 100644
> --- a/drivers/cxl/mem.c
> +++ b/drivers/cxl/mem.c
> @@ -285,6 +285,8 @@ static umode_t cxl_mem_visible(struct kobject *kobj, struct attribute *a, int n)
>
> static struct attribute *cxl_mem_attrs[] = {
> &dev_attr_trigger_poison_list.attr,
> + &dev_attr_mem_qos_class.attr,
+ &dev_attr_ram_qos_class.attr,
Mistake when attempting to split out the diff from the tested patch.
> + &dev_attr_pmem_qos_class.attr,
> NULL
> };
>
next prev parent reply other threads:[~2023-12-18 16:28 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-13 16:41 [PATCH v14 00/19] cxl: Add support for QTG ID retrieval for CXL subsystem Dave Jiang
2023-12-13 16:41 ` [PATCH v14 01/19] lib/firmware_table: tables: Add CDAT table parsing support Dave Jiang
2023-12-13 16:41 ` [PATCH v14 02/19] base/node / acpi: Change 'node_hmem_attrs' to 'access_coordinates' Dave Jiang
2023-12-13 16:41 ` [PATCH v14 03/19] acpi: numa: Create enum for memory_target access coordinates indexing Dave Jiang
2023-12-13 16:41 ` [PATCH v14 04/19] acpi: numa: Add genport target allocation to the HMAT parsing Dave Jiang
2023-12-13 16:41 ` [PATCH v14 05/19] acpi: Break out nesting for hmat_parse_locality() Dave Jiang
2023-12-13 16:41 ` [PATCH v14 06/19] acpi: numa: Add setting of generic port system locality attributes Dave Jiang
2023-12-13 16:42 ` [PATCH v14 07/19] acpi: numa: Add helper function to retrieve the performance attributes Dave Jiang
2023-12-13 16:42 ` [PATCH v14 08/19] cxl: Add callback to parse the DSMAS subtables from CDAT Dave Jiang
2023-12-13 16:42 ` [PATCH v14 09/19] cxl: Add callback to parse the DSLBIS subtable " Dave Jiang
2023-12-13 16:42 ` [PATCH v14 10/19] cxl: Add callback to parse the SSLBIS " Dave Jiang
2023-12-13 16:42 ` [PATCH v14 11/19] cxl: Add support for _DSM Function for retrieving QTG ID Dave Jiang
2023-12-13 16:42 ` [PATCH v14 12/19] cxl: Calculate and store PCI link latency for the downstream ports Dave Jiang
2023-12-13 16:42 ` [PATCH v14 13/19] tools/testing/cxl: Add hostbridge UID string for cxl_test mock hb devices Dave Jiang
2023-12-13 16:42 ` [PATCH v14 14/19] cxl: Store the access coordinates for the generic ports Dave Jiang
2023-12-13 16:42 ` [PATCH v14 15/19] cxl: Add helper function that calculate performance data for downstream ports Dave Jiang
2023-12-13 16:42 ` [PATCH v14 16/19] cxl: Compute the entire CXL path latency and bandwidth data Dave Jiang
2023-12-13 16:43 ` [PATCH v14 17/19] cxl: Store QTG IDs and related info to the CXL memory device context Dave Jiang
2023-12-13 16:43 ` [PATCH v14 18/19] cxl: Export sysfs attributes for memory device QoS class Dave Jiang
2023-12-15 20:33 ` Dave Jiang
2023-12-18 16:28 ` Dave Jiang [this message]
2023-12-13 16:43 ` [PATCH v14 19/19] cxl: Check qos_class validity on memdev probe Dave Jiang
2023-12-19 16:42 ` Jonathan Cameron
2023-12-20 22:26 ` Dave Jiang
2024-01-08 14:01 ` Jonathan Cameron
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