Re: [PATCH] cxl/pci: the ctrl register should be read when it is being used

[Dave Jiang <dave.jiang@intel.com>]

On 5/29/24 2:33 AM, Foryun Ma wrote:
> When the cap register and wait_for_valid checks fail, the ctrl register
> read will be redundant.
> 
> Signed-off-by: Foryun Ma <foryun.ma@jaguarmicro.com>

Please consider slight change to the subject and commit log:

cxl/core/pci: Move reading of control register to immediately before usage

Relocate the reading of the DVSEC control register to immediately before usage and
avoid unnecessary PCI config access from the read if DVSEC capability check, hdm_count
check, or device validity check results in failure.


Otherwise LGTM

> ---
>  drivers/cxl/core/pci.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 8567dd11eaac..627be83881e9 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -338,10 +338,6 @@ int cxl_dvsec_rr_decode(struct device *dev, int d,
>  	if (rc)
>  		return rc;
>  
> -	rc = pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl);
> -	if (rc)
> -		return rc;
> -
>  	if (!(cap & CXL_DVSEC_MEM_CAPABLE)) {
>  		dev_dbg(dev, "Not MEM Capable\n");
>  		return -ENXIO;
> @@ -363,6 +359,10 @@ int cxl_dvsec_rr_decode(struct device *dev, int d,
>  		return rc;
>  	}
>  
> +	rc = pci_read_config_word(pdev, d + CXL_DVSEC_CTRL_OFFSET, &ctrl);
> +	if (rc)
> +		return rc;
> +
>  	/*
>  	 * The current DVSEC values are moot if the memory capability is
>  	 * disabled, and they will remain moot after the HDM Decoder