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X-CSE-ConnectionGUID: KdaXWZ0/SNmtqlcKq+UByw== X-CSE-MsgGUID: /7rBRbHKTi6S8ClB/M6Mxw== X-IronPort-AV: E=McAfee;i="6800,10657,11558"; a="71764480" X-IronPort-AV: E=Sophos;i="6.18,278,1751266800"; d="scan'208";a="71764480" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2025 11:20:57 -0700 X-CSE-ConnectionGUID: I0KqIfnETgi5yG43kWxjNQ== X-CSE-MsgGUID: 0BMjWMbfR3qy6NnKp19xmA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.18,278,1751266800"; d="scan'208";a="180135429" Received: from dnelso2-mobl.amr.corp.intel.com (HELO [10.125.108.58]) ([10.125.108.58]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Sep 2025 11:20:55 -0700 Message-ID: Date: Fri, 19 Sep 2025 11:20:54 -0700 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v18 10/20] sfc: get root decoder To: alejandro.lucero-palau@amd.com, linux-cxl@vger.kernel.org, netdev@vger.kernel.org, dan.j.williams@intel.com, edward.cree@amd.com, davem@davemloft.net, kuba@kernel.org, pabeni@redhat.com, edumazet@google.com Cc: Alejandro Lucero , Martin Habets , Edward Cree , Jonathan Cameron References: <20250918091746.2034285-1-alejandro.lucero-palau@amd.com> <20250918091746.2034285-11-alejandro.lucero-palau@amd.com> Content-Language: en-US From: Dave Jiang In-Reply-To: <20250918091746.2034285-11-alejandro.lucero-palau@amd.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 9/18/25 2:17 AM, alejandro.lucero-palau@amd.com wrote: > From: Alejandro Lucero > > Use cxl api for getting HPA (Host Physical Address) to use from a > CXL root decoder. > > Signed-off-by: Alejandro Lucero > Reviewed-by: Martin Habets > Acked-by: Edward Cree > Reviewed-by: Jonathan Cameron Reviewed-by: Dave Jiang > --- > drivers/cxl/cxl.h | 15 --------------- > drivers/net/ethernet/sfc/Kconfig | 1 + > drivers/net/ethernet/sfc/efx_cxl.c | 27 +++++++++++++++++++++++++++ > include/cxl/cxl.h | 14 ++++++++++++++ > 4 files changed, 42 insertions(+), 15 deletions(-) > > diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h > index 076640e91ee0..ab490b5a9457 100644 > --- a/drivers/cxl/cxl.h > +++ b/drivers/cxl/cxl.h > @@ -219,21 +219,6 @@ int cxl_dport_map_rcd_linkcap(struct pci_dev *pdev, struct cxl_dport *dport); > #define CXL_RESOURCE_NONE ((resource_size_t) -1) > #define CXL_TARGET_STRLEN 20 > > -/* > - * cxl_decoder flags that define the type of memory / devices this > - * decoder supports as well as configuration lock status See "CXL 2.0 > - * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. > - * Additionally indicate whether decoder settings were autodetected, > - * user customized. > - */ > -#define CXL_DECODER_F_RAM BIT(0) > -#define CXL_DECODER_F_PMEM BIT(1) > -#define CXL_DECODER_F_TYPE2 BIT(2) > -#define CXL_DECODER_F_TYPE3 BIT(3) > -#define CXL_DECODER_F_LOCK BIT(4) > -#define CXL_DECODER_F_ENABLE BIT(5) > -#define CXL_DECODER_F_MASK GENMASK(5, 0) > - > enum cxl_decoder_type { > CXL_DECODER_DEVMEM = 2, > CXL_DECODER_HOSTONLYMEM = 3, > diff --git a/drivers/net/ethernet/sfc/Kconfig b/drivers/net/ethernet/sfc/Kconfig > index 979f2801e2a8..e959d9b4f4ce 100644 > --- a/drivers/net/ethernet/sfc/Kconfig > +++ b/drivers/net/ethernet/sfc/Kconfig > @@ -69,6 +69,7 @@ config SFC_MCDI_LOGGING > config SFC_CXL > bool "Solarflare SFC9100-family CXL support" > depends on SFC && CXL_BUS >= SFC > + depends on CXL_REGION > default SFC > help > This enables SFC CXL support if the kernel is configuring CXL for > diff --git a/drivers/net/ethernet/sfc/efx_cxl.c b/drivers/net/ethernet/sfc/efx_cxl.c > index 177c60b269d6..d29594e71027 100644 > --- a/drivers/net/ethernet/sfc/efx_cxl.c > +++ b/drivers/net/ethernet/sfc/efx_cxl.c > @@ -18,6 +18,7 @@ int efx_cxl_init(struct efx_probe_data *probe_data) > { > struct efx_nic *efx = &probe_data->efx; > struct pci_dev *pci_dev = efx->pci_dev; > + resource_size_t max_size; > struct efx_cxl *cxl; > u16 dvsec; > int rc; > @@ -88,13 +89,39 @@ int efx_cxl_init(struct efx_probe_data *probe_data) > return PTR_ERR(cxl->cxlmd); > } > > + cxl->endpoint = cxl_acquire_endpoint(cxl->cxlmd); > + if (IS_ERR(cxl->endpoint)) > + return PTR_ERR(cxl->endpoint); > + > + cxl->cxlrd = cxl_get_hpa_freespace(cxl->cxlmd, 1, > + CXL_DECODER_F_RAM | CXL_DECODER_F_TYPE2, > + &max_size); > + > + if (IS_ERR(cxl->cxlrd)) { > + pci_err(pci_dev, "cxl_get_hpa_freespace failed\n"); > + cxl_release_endpoint(cxl->cxlmd, cxl->endpoint); > + return PTR_ERR(cxl->cxlrd); > + } > + > + if (max_size < EFX_CTPIO_BUFFER_SIZE) { > + pci_err(pci_dev, "%s: not enough free HPA space %pap < %u\n", > + __func__, &max_size, EFX_CTPIO_BUFFER_SIZE); > + cxl_put_root_decoder(cxl->cxlrd); > + cxl_release_endpoint(cxl->cxlmd, cxl->endpoint); > + return -ENOSPC; > + } > + > probe_data->cxl = cxl; > > + cxl_release_endpoint(cxl->cxlmd, cxl->endpoint); > + > return 0; > } > > void efx_cxl_exit(struct efx_probe_data *probe_data) > { > + if (probe_data->cxl) > + cxl_put_root_decoder(probe_data->cxl->cxlrd); > } > > MODULE_IMPORT_NS("CXL"); > diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h > index 7722d4190573..788700fb1eb2 100644 > --- a/include/cxl/cxl.h > +++ b/include/cxl/cxl.h > @@ -153,6 +153,20 @@ struct cxl_dpa_partition { > > #define CXL_NR_PARTITIONS_MAX 2 > > +/* > + * cxl_decoder flags that define the type of memory / devices this > + * decoder supports as well as configuration lock status See "CXL 2.0 > + * 8.2.5.12.7 CXL HDM Decoder 0 Control Register" for details. > + * Additionally indicate whether decoder settings were autodetected, > + * user customized. > + */ > +#define CXL_DECODER_F_RAM BIT(0) > +#define CXL_DECODER_F_PMEM BIT(1) > +#define CXL_DECODER_F_TYPE2 BIT(2) > +#define CXL_DECODER_F_TYPE3 BIT(3) > +#define CXL_DECODER_F_LOCK BIT(4) > +#define CXL_DECODER_F_ENABLE BIT(5) > + > struct cxl_memdev_ops { > int (*probe)(struct cxl_memdev *cxlmd); > };