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b=nfflrSi1XbSCfFpD1Z/mCPiLyuli5/UzFTniJ52N9Exp2HLTcz7sbMioCFPhVshmTp0WWz6HissuPTTMmL6v9Eo0tukgZFEI7LLkAXOd0FdKtxex0G9Iuittiyruliso5Hf+0iLu7I4wowXLFb6aAnV3iO+5RRJVnvOezjTRkTY= Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=amd.com; Received: from DS0PR12MB6390.namprd12.prod.outlook.com (2603:10b6:8:ce::7) by MW3PR12MB4425.namprd12.prod.outlook.com (2603:10b6:303:5e::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.7698.32; Wed, 26 Jun 2024 13:51:38 +0000 Received: from DS0PR12MB6390.namprd12.prod.outlook.com ([fe80::38ec:7496:1a35:599f]) by DS0PR12MB6390.namprd12.prod.outlook.com ([fe80::38ec:7496:1a35:599f%7]) with mapi id 15.20.7698.025; Wed, 26 Jun 2024 13:51:38 +0000 Message-ID: Date: Wed, 26 Jun 2024 08:51:35 -0500 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH 7/9] cxl/pci: Add atomic notifier callback for CXL PCIe port AER internal errors Content-Language: en-US To: "Li, Ming4" , "Williams, Dan J" , "Weiny, Ira" , "dave@stgolabs.net" , "Jiang, Dave" , "Schofield, Alison" , "Verma, Vishal L" , "jim.harris@samsung.com" , "ilpo.jarvinen@linux.intel.com" , "ardb@kernel.org" , "sathyanarayanan.kuppuswamy@linux.intel.com" , "linux-cxl@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "Yazen.Ghannam@amd.com" , "Robert.Richter@amd.com" References: <20240617200411.1426554-1-terry.bowman@amd.com> <20240617200411.1426554-8-terry.bowman@amd.com> <45270079-6aa2-4530-8649-87bd5765d74b@intel.com> From: Terry Bowman In-Reply-To: <45270079-6aa2-4530-8649-87bd5765d74b@intel.com> Content-Type: text/plain; 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Unregister the callback in the cxl_pci driver's unload. >> >> Implement the callback to check if the device parameter is a valid >> CXL PCIe port. If it is valid then make the notification callback call >> __cxl_handle_cor_ras() or __cxl_handle_ras() depending on the AER >> type. >> >> [1] CXL3.1 - 12.2.2 CXL Root Ports, Downstream Switch Ports, and >> Upstream Switch Ports >> >> Signed-off-by: Terry Bowman >> --- >> drivers/cxl/core/core.h | 4 ++ >> drivers/cxl/core/pci.c | 97 ++++++++++++++++++++++++++++++++++++++--- >> drivers/cxl/core/port.c | 6 +-- >> drivers/cxl/cxl.h | 5 +++ >> drivers/cxl/cxlpci.h | 2 + >> drivers/cxl/pci.c | 19 +++++++- >> 6 files changed, 123 insertions(+), 10 deletions(-) >> >> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h >> index bc5a95665aa0..69bef1db6ee0 100644 >> --- a/drivers/cxl/core/core.h >> +++ b/drivers/cxl/core/core.h >> @@ -94,4 +94,8 @@ int cxl_update_hmat_access_coordinates(int nid, struct cxl_region *cxlr, >> enum access_coordinate_class access); >> bool cxl_need_node_perf_attrs_update(int nid); >> >> +struct cxl_dport *find_dport(struct cxl_port *port, int id); >> +struct cxl_port *find_cxl_port(struct device *dport_dev, >> + struct cxl_dport **dport); >> + >> #endif /* __CXL_CORE_H__ */ >> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c >> index 59a317ab84bb..e630eccb733d 100644 >> --- a/drivers/cxl/core/pci.c >> +++ b/drivers/cxl/core/pci.c >> @@ -689,7 +689,6 @@ EXPORT_SYMBOL_NS_GPL(read_cdat_data, CXL); >> static void __cxl_handle_cor_ras(struct device *dev, >> void __iomem *ras_base) >> { >> - struct cxl_memdev *cxlmd = to_cxl_memdev(dev); >> void __iomem *addr; >> u32 status; >> >> @@ -698,10 +697,17 @@ static void __cxl_handle_cor_ras(struct device *dev, >> >> addr = ras_base + CXL_RAS_CORRECTABLE_STATUS_OFFSET; >> status = readl(addr); >> - if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) { >> - writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); >> + >> + if (!(status & CXL_RAS_CORRECTABLE_STATUS_MASK)) >> + return; >> + >> + writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr); >> + if (is_cxl_memdev(dev)) { >> + struct cxl_memdev *cxlmd = to_cxl_memdev(dev); >> + >> trace_cxl_aer_correctable_error(cxlmd, status); >> - } >> + } else if (dev_is_pci(dev)) >> + trace_cxl_port_aer_correctable_error(dev, status); >> } >> >> static void cxl_handle_endpoint_cor_ras(struct cxl_dev_state *cxlds) >> @@ -733,7 +739,6 @@ static void header_log_copy(void __iomem *ras_base, u32 *log) >> static bool __cxl_handle_ras(struct device *dev, >> void __iomem *ras_base) >> { >> - struct cxl_memdev *cxlmd = to_cxl_memdev(dev); >> u32 hl[CXL_HEADERLOG_SIZE_U32]; >> void __iomem *addr; >> u32 status; >> @@ -759,7 +764,13 @@ static bool __cxl_handle_ras(struct device *dev, >> } >> >> header_log_copy(ras_base, hl); >> - trace_cxl_aer_uncorrectable_error(cxlmd, status, fe, hl); >> + if (is_cxl_memdev(dev)) { >> + struct cxl_memdev *cxlmd = to_cxl_memdev(dev); >> + >> + trace_cxl_aer_uncorrectable_error(cxlmd, status, fe, hl); >> + } else if (dev_is_pci(dev)) >> + trace_cxl_port_aer_uncorrectable_error(dev, status); >> + >> writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr); >> >> return true; >> @@ -882,6 +893,80 @@ static bool cxl_handle_rdport_ras(struct cxl_dev_state *cxlds, >> return __cxl_handle_ras(&cxlds->cxlmd->dev, dport->regs.ras); >> } >> >> +static int match_uport(struct device *dev, void *data) >> +{ >> + struct device *uport_dev = (struct device *)data; >> + struct cxl_port *port; >> + >> + if (!is_cxl_port(dev)) >> + return 0; >> + >> + port = to_cxl_port(dev); >> + >> + return (port->uport_dev == uport_dev); >> +} >> + >> +static struct cxl_port *pci_to_cxl_uport(struct pci_dev *pdev) >> +{ >> + struct cxl_dport *dport; >> + struct device *port_dev; >> + struct cxl_port *port; >> + >> + port = find_cxl_port(pdev->dev.parent, &dport); >> + if (!port) >> + return NULL; >> + put_device(&port->dev); >> + >> + port_dev = device_find_child(&port->dev, &pdev->dev, match_uport); >> + if (!port_dev) >> + return NULL; > >  seems like just a bus_find_device(&cxl_bus_type, NULL, &pdev->dev, match_uport) can replace these find_cxl_port() and device_find_child(). > > That would be a good improvement/optimization. I'll look into making that change. >> + put_device(port_dev); >> + >> + port = to_cxl_port(port_dev); >> + >> + return port; >> +} >> + >> +static void __iomem *cxl_pci_port_ras(struct pci_dev *pdev) >> +{ >> + void __iomem *ras_base = NULL; >> + >> + if ((pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) || >> + (pci_pcie_type(pdev) == PCI_EXP_TYPE_DOWNSTREAM)) { >> + struct cxl_dport *dport; >> + >> + find_cxl_port(&pdev->dev, &dport); >> + ras_base = dport ? dport->regs.ras : NULL; > > Need put_device(&port->dev) after find_cxl_port(), use scope-based resource management __free() here should be better. > > Thanks. Regards, Terry