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X-CSE-ConnectionGUID: 8IgkARW1RdicED81lVP4hQ== X-CSE-MsgGUID: 9mV9/QdARqWh9kkl809Nsg== X-IronPort-AV: E=McAfee;i="6800,10657,11673"; a="69096634" X-IronPort-AV: E=Sophos;i="6.21,231,1763452800"; d="scan'208";a="69096634" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2026 07:59:38 -0800 X-CSE-ConnectionGUID: bDgbdEMTQw6b2QqinEE3mg== X-CSE-MsgGUID: 9BxtXjRtTumMUJG4NZE//w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.21,231,1763452800"; d="scan'208";a="204883081" Received: from sghuge-mobl2.amr.corp.intel.com (HELO [10.125.111.140]) ([10.125.111.140]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 16 Jan 2026 07:59:38 -0800 Message-ID: Date: Fri, 16 Jan 2026 08:59:36 -0700 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 0/2] cxl/region: Support unaligned address translations To: Alison Schofield , Davidlohr Bueso , Jonathan Cameron , Vishal Verma , Ira Weiny , Dan Williams Cc: linux-cxl@vger.kernel.org References: Content-Language: en-US From: Dave Jiang In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 1/15/26 9:58 PM, Alison Schofield wrote: > Changes in v6: > - Replace 64-bit division operators with div64_u64() helpers (lkp) > > Changes in v5: > - s/reg_ways/region_ways in decode_pos (DaveJ) > - Add comments in decode_pos > - Update the CXL spec references to 4.0 > > Changes in v4: > - Rebased Patch 1 onto 6.19-rc4 with minimal conflict. > - Added Patch 2 because 6.19 introduced poison by region offset > meaning that too needed support for unaligned regions. > > Changes in v3: > - Add bracketing to avert possibly uninitialized usage (lkp) > - Remove excessive narration in decode_pos() (Jonathan) > - Calculate devices_per_hb only once after switch in decode_pos() (Jonathan) > - Reduce scope of hpa and shifted in unaligned_dpa_to_hpa() (Jonathan) > - Unmix non- and assignment declarations in unaligned_dpa_to_hpa() (Jonathan) > - Add blank line after return ULLONG_MAX in unaligned_dpa_to_hpa() (Jonathan) > - s/index/position in for loop in unaligned_dpa_to_hpa() (Jonathan) > - Initialize bool aligned true > - Comment that restore_parent() math relies on power-of-2 granularity > - Tidy-up the restore_parent() comment block > > Changes in v2: > - Add 6 and 12 Host Bridge interleaves to decode_pos() (Jonathan) > - Limit the unalignment check to MOD3 regions > - Move the cache_size increment to a single place > - Updated some in code comments > - Rebase on v6.18-rc1 > > Changes in v1 (was RFC): > - Replace "/" with do_div() to quiet i386 build warning (lkp) > - Replace 'cxld->interleave_ways' with 'hbiw' for clarity > - Use div64_u64_rem() for alignment alignment > - Fix up a printk format specifier (lkp) > - Update code comments and commit log > - Rebase on v6.17-rc7 > > > Begin Cover Letter: > With the introduction of MOD3 interleave way support, platforms may > create regions at starting addresses that are not power-of-2 aligned. > This allows platforms to avoid gaps in the memory map, but addresses > within those regions cannot be translated using the existing bit > manipulation method. > > Introduce support for translating these unaligned addresses. > > > Alison Schofield (2): > cxl/region: Translate DPA->HPA in unaligned MOD3 regions > cxl/region: Translate HPA to DPA and memdev in unaligned regions > > drivers/cxl/core/region.c | 212 ++++++++++++++++++++++++++++++++++++-- > 1 file changed, 204 insertions(+), 8 deletions(-) > > > base-commit: 9ace4753a5202b02191d54e9fdf7f9e3d02b85eb Reapplied to cxl/next 19885bd10755b9f737742fef8a14cbf554cd84e8 78b50b5984629d362f826e9615ce4599f429716e