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This means > the comment and code regarding setting address bits is discarded. > Although that logic is not wrong, it adds a level of complexity that > is not required in the granularity selection. The eig and eiw are > indeed part of the routing instructions programmed into the decoders. > Up-level the discussion to nominal ways and granularity for clearer > analysis. > > The second simplification reduces the logic to a single granularity > calculation that works for all cases. The new calculation doesn't > care if parent_iw => 1 because parent_iw is used as a multiplier. > > The refactor cleans up a useless assignment of eiw made after the > iw is already calculated. > > Regression testing included an examination of all of the ways and > granularity selections made during a run of the cxl_test unit tests. > There were no differences in selections before and after this patch. > > Fixes: ("27b3f8d13830 cxl/region: Program target lists") > Signed-off-by: Alison Schofield Reviewed-by: Dave Jiang > --- > > Changes in v2: > - No changes to the code. Commit log fixups only. > - Correct the commit log example. Endpoints are 2 * 256 (Jonathan) > - Use 'encoded' and 'nominal' when referring to the interleave > granularity format (Dan, DaveJ) > - Commit log grammar & spelling fixups (Dan, DaveJ) > - Add Fixes Tag (Dan) > - v1: https://lore.kernel.org/linux-cxl/20230804232726.1672782-1-alison.schofield@intel.com/ > > drivers/cxl/core/region.c | 17 ++++++++--------- > 1 file changed, 8 insertions(+), 9 deletions(-) > > diff --git a/drivers/cxl/core/region.c b/drivers/cxl/core/region.c > index e115ba382e04..5a1cc59cca99 100644 > --- a/drivers/cxl/core/region.c > +++ b/drivers/cxl/core/region.c > @@ -1154,16 +1154,15 @@ static int cxl_port_setup_targets(struct cxl_port *port, > } > > /* > - * If @parent_port is masking address bits, pick the next unused address > - * bit to route @port's targets. > + * Interleave granularity is a multiple of @parent_port granularity. > + * Multiplier is the parent port interleave ways. > */ > - if (parent_iw > 1 && cxl_rr->nr_targets > 1) { > - u32 address_bit = max(peig + peiw, eiw + peig); > - > - eig = address_bit - eiw + 1; > - } else { > - eiw = peiw; > - eig = peig; > + rc = granularity_to_eig(parent_ig * parent_iw, &eig); > + if (rc) { > + dev_dbg(&cxlr->dev, > + "%s: invalid granularity calculation (%d * %d)\n", > + dev_name(&parent_port->dev), parent_ig, parent_iw); > + return rc; > } > > rc = eig_to_granularity(eig, &ig); > > base-commit: fe77cc2e5a6a7c85f5c6ef8a39d7694ffc7f41c9