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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SA2PEPF00003F64.mail.protection.outlook.com (10.167.248.39) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8511.15 via Frontend Transport; Mon, 3 Mar 2025 21:26:29 +0000 Received: from [10.236.179.218] (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Mon, 3 Mar 2025 15:26:27 -0600 Message-ID: Date: Mon, 3 Mar 2025 15:26:20 -0600 Precedence: bulk X-Mailing-List: linux-cxl@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC 0/2] type2 cxl initialization To: Dan Williams , CC: Alejandro Lucero , References: <20250220200041.3891165-1-alejandro.lucero-palau@amd.com> <289fc275-43b6-424c-8c0c-28c5d527ac35@amd.com> <67c615da5dd98_1a772947d@dwillia2-xfh.jf.intel.com.notmuch> Content-Language: en-US From: Ben Cheatham In-Reply-To: <67c615da5dd98_1a772947d@dwillia2-xfh.jf.intel.com.notmuch> Content-Type: text/plain; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Mar 2025 21:26:29.2216 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 15480e7a-53c4-43be-6dc4-08dd5a9a0fcc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00003F64.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7442 On 3/3/25 2:49 PM, Dan Williams wrote: > Ben Cheatham wrote: >> On 2/20/25 2:00 PM, alejandro.lucero-palau@amd.com wrote: >>> From: Alejandro Lucero >>> >>> Avoiding to send the full type2 support patchset until there is an >>> agreement about how to do the cxl initialization from accel drivers. >>> >>> Using the idea from fwctl for embedding cxl_dev_state in a private >>> accel driver struct and a macro helping for the allocation and >>> initialization of such struct. >>> >>> The main problem is the amount of internal cxl structs which need to be >>> public for accel drivers which we tried to avoid since v1 of the type2 >>> patchset history. >> >> I have a suggestion or two in the next patch, but in my opinion the only >> potentially problematic exports are the cxl register structs. I'm assuming >> allowing accelerator drivers access to those may cause stale values in the >> CXL driver, but I haven't looked. The only suggestion I have there is to >> use pointers to the struct instead, but I imagine achieving could be a >> non-trivial amount of effort. > > Hmm, say more about why you think those are a problem. Those are > "write-once at init" things, why would an accelerator driver have any > reason to play with those post init? > I could see a scenario where an accelerator driver tries to do some concurrent setup with the CXL driver and may cause an issue. For example if a type 2 driver tried to do something with HDM during setup, but I think a driver touching any of these registers when the CXL driver already does this stuff is pretty unlikely. So that leads me to think it's better to not expose this at all, but I think that would require more work than it's worth. >> The only other member that may be a problem is the DPA partition info, >> but I don't know enough about that to comment. > > I think it is sufficient to mark the bulk of 'struct cxl_dev_state' as > private and then move things into the public space as needed, something > like: > > struct cxl_dev_state { > /* public */ > struct device *dev; > struct cxl_memdev *cxlmd; > /* private */ > struct cxl_register_map reg_map; > struct cxl_regs regs; > int cxl_dvsec; > bool rcd; > bool media_ready; > struct resource dpa_res; > struct cxl_dpa_partition part[CXL_NR_PARTITIONS_MAX]; > unsigned int nr_partitions; > u64 serial; > enum cxl_devtype type; > struct cxl_mailbox cxl_mbox; > }; > > ...but otherwise let accelerator drivers see the full definition of that > struct for constainer_of() operations. That's fine by me.