From: Alejandro Lucero Palau <alucerop@amd.com>
To: Dave Jiang <dave.jiang@intel.com>,
alejandro.lucero-palau@amd.com, linux-cxl@vger.kernel.org,
netdev@vger.kernel.org, dan.j.williams@intel.com,
edward.cree@amd.com, davem@davemloft.net, kuba@kernel.org,
pabeni@redhat.com, edumazet@google.com
Cc: Ben Cheatham <benjamin.cheatham@amd.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: Re: [PATCH v17 13/22] cxl: Define a driver interface for DPA allocation
Date: Fri, 4 Jul 2025 16:21:46 +0100 [thread overview]
Message-ID: <e6997f81-cb9e-4e8f-a333-dbcc42c0c56c@amd.com> (raw)
In-Reply-To: <5b3f6c11-c51c-4f24-98c1-3d5ceadf4278@intel.com>
On 6/27/25 21:46, Dave Jiang wrote:
>
> On 6/24/25 7:13 AM, alejandro.lucero-palau@amd.com wrote:
>> From: Alejandro Lucero <alucerop@amd.com>
>>
>> Region creation involves finding available DPA (device-physical-address)
>> capacity to map into HPA (host-physical-address) space.
>>
>> In order to support CXL Type2 devices, define an API, cxl_request_dpa(),
>> that tries to allocate the DPA memory the driver requires to operate.The
>> memory requested should not be bigger than the max available HPA obtained
>> previously with cxl_get_hpa_freespace.
> cxl_get_hpa_freespace()
OK
>
>> Based on https://lore.kernel.org/linux-cxl/168592158743.1948938.7622563891193802610.stgit@dwillia2-xfh.jf.intel.com/
>>
>> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
>> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> ---
>> drivers/cxl/core/hdm.c | 93 ++++++++++++++++++++++++++++++++++++++++++
>> drivers/cxl/cxl.h | 2 +
>> include/cxl/cxl.h | 5 +++
>> 3 files changed, 100 insertions(+)
>>
>> diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
>> index 70cae4ebf8a4..b17381e49836 100644
>> --- a/drivers/cxl/core/hdm.c
>> +++ b/drivers/cxl/core/hdm.c
>> @@ -3,6 +3,7 @@
>> #include <linux/seq_file.h>
>> #include <linux/device.h>
>> #include <linux/delay.h>
>> +#include <cxl/cxl.h>
>>
>> #include "cxlmem.h"
>> #include "core.h"
>> @@ -546,6 +547,13 @@ resource_size_t cxl_dpa_resource_start(struct cxl_endpoint_decoder *cxled)
>> return base;
>> }
>>
>> +/**
>> + * cxl_dpa_free - release DPA (Device Physical Address)
>> + *
>> + * @cxled: endpoint decoder linked to the DPA
>> + *
>> + * Returns 0 or error.
>> + */
>> int cxl_dpa_free(struct cxl_endpoint_decoder *cxled)
>> {
>> struct cxl_port *port = cxled_to_port(cxled);
>> @@ -572,6 +580,7 @@ int cxl_dpa_free(struct cxl_endpoint_decoder *cxled)
>> devm_cxl_dpa_release(cxled);
>> return 0;
>> }
>> +EXPORT_SYMBOL_NS_GPL(cxl_dpa_free, "CXL");
>>
>> int cxl_dpa_set_part(struct cxl_endpoint_decoder *cxled,
>> enum cxl_partition_mode mode)
>> @@ -686,6 +695,90 @@ int cxl_dpa_alloc(struct cxl_endpoint_decoder *cxled, unsigned long long size)
>> return devm_add_action_or_reset(&port->dev, cxl_dpa_release, cxled);
>> }
>>
>> +static int find_free_decoder(struct device *dev, const void *data)
>> +{
>> + struct cxl_endpoint_decoder *cxled;
>> + struct cxl_port *port;
>> +
>> + if (!is_endpoint_decoder(dev))
>> + return 0;
>> +
>> + cxled = to_cxl_endpoint_decoder(dev);
>> + port = cxled_to_port(cxled);
>> +
>> + if (cxled->cxld.id != port->hdm_end + 1)
>> + return 0;
>> +
>> + return 1;
> return cxled->cxld.id == port->hdm_end + 1;
OK
>> +}
>> +
>> +static struct cxl_endpoint_decoder *
>> +cxl_find_free_decoder(struct cxl_memdev *cxlmd)
>> +{
>> + struct cxl_port *endpoint = cxlmd->endpoint;
>> + struct device *dev;
>> +
>> + scoped_guard(rwsem_read, &cxl_dpa_rwsem) {
> Probably ok to just use guard() here
OK
>> + dev = device_find_child(&endpoint->dev, NULL,
>> + find_free_decoder);
>> + }
>> + if (dev)
>> + return to_cxl_endpoint_decoder(dev);
>> +
>> + return NULL;
>> +}
>> +
>> +/**
>> + * cxl_request_dpa - search and reserve DPA given input constraints
>> + * @cxlmd: memdev with an endpoint port with available decoders
>> + * @mode: DPA operation mode (ram vs pmem)
>> + * @alloc: dpa size required
>> + *
>> + * Returns a pointer to a cxl_endpoint_decoder struct or an error
>> + *
>> + * Given that a region needs to allocate from limited HPA capacity it
>> + * may be the case that a device has more mappable DPA capacity than
>> + * available HPA. The expectation is that @alloc is a driver known
>> + * value based on the device capacity but it could not be available
>> + * due to HPA constraints.
>> + *
>> + * Returns a pinned cxl_decoder with at least @alloc bytes of capacity
>> + * reserved, or an error pointer. The caller is also expected to own the
>> + * lifetime of the memdev registration associated with the endpoint to
>> + * pin the decoder registered as well.
>> + */
>> +struct cxl_endpoint_decoder *cxl_request_dpa(struct cxl_memdev *cxlmd,
>> + enum cxl_partition_mode mode,
>> + resource_size_t alloc)
>> +{
>> + struct cxl_endpoint_decoder *cxled __free(put_cxled) =
>> + cxl_find_free_decoder(cxlmd);
>> + struct device *cxled_dev;
>> + int rc;
>> +
>> + if (!IS_ALIGNED(alloc, SZ_256M))
>> + return ERR_PTR(-EINVAL);
>> +
>> + if (!cxled) {
>> + rc = -ENODEV;
>> + goto err;
> return ERR_PTR(-ENODEV);
>
> cxled_dev is not set here. In fact it's never set anywhere. the put_device() later will fail. Although the __free() should take care of it right? The err path isn't necessary?
As I commented with Jonathan's review, I'll fix it.
>> + }
>> +
>> + rc = cxl_dpa_set_part(cxled, mode);
>> + if (rc)
>> + goto err;
>> +
>> + rc = cxl_dpa_alloc(cxled, alloc);
>> + if (rc)
>> + goto err;
>> +
>> + return cxled;
> return no_free_ptr(cxled);
Yes. Thanks!
>
> DJ
>
>> +err:
>> + put_device(cxled_dev);
>> + return ERR_PTR(rc);
>> +}
>> +EXPORT_SYMBOL_NS_GPL(cxl_request_dpa, "CXL");
>> +
>> static void cxld_set_interleave(struct cxl_decoder *cxld, u32 *ctrl)
>> {
>> u16 eig;
>> diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
>> index 3af8821f7c15..6e724a8440f5 100644
>> --- a/drivers/cxl/cxl.h
>> +++ b/drivers/cxl/cxl.h
>> @@ -636,6 +636,8 @@ void put_cxl_root(struct cxl_root *cxl_root);
>> DEFINE_FREE(put_cxl_root, struct cxl_root *, if (_T) put_cxl_root(_T))
>>
>> DEFINE_FREE(put_cxl_port, struct cxl_port *, if (!IS_ERR_OR_NULL(_T)) put_device(&_T->dev))
>> +DEFINE_FREE(put_cxled, struct cxl_endpoint_decoder *, if (_T) put_device(&_T->cxld.dev))
>> +
>> int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd);
>> void cxl_bus_rescan(void);
>> void cxl_bus_drain(void);
>> diff --git a/include/cxl/cxl.h b/include/cxl/cxl.h
>> index dd37b1d88454..a2f3e683724a 100644
>> --- a/include/cxl/cxl.h
>> +++ b/include/cxl/cxl.h
>> @@ -7,6 +7,7 @@
>>
>> #include <linux/node.h>
>> #include <linux/ioport.h>
>> +#include <linux/range.h>
>> #include <cxl/mailbox.h>
>>
>> /**
>> @@ -247,4 +248,8 @@ struct cxl_root_decoder *cxl_get_hpa_freespace(struct cxl_memdev *cxlmd,
>> unsigned long flags,
>> resource_size_t *max);
>> void cxl_put_root_decoder(struct cxl_root_decoder *cxlrd);
>> +struct cxl_endpoint_decoder *cxl_request_dpa(struct cxl_memdev *cxlmd,
>> + enum cxl_partition_mode mode,
>> + resource_size_t alloc);
>> +int cxl_dpa_free(struct cxl_endpoint_decoder *cxled);
>> #endif /* __CXL_CXL_H__ */
next prev parent reply other threads:[~2025-07-04 15:21 UTC|newest]
Thread overview: 113+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-24 14:13 [PATCH v17 00/22] Type2 device basic support alejandro.lucero-palau
2025-06-24 14:13 ` [PATCH v17 01/22] cxl: Add type2 " alejandro.lucero-palau
2025-06-25 14:06 ` Jonathan Cameron
2025-06-30 14:38 ` Alejandro Lucero Palau
2025-07-25 21:46 ` dan.j.williams
2025-08-05 10:45 ` Alejandro Lucero Palau
2025-08-05 15:14 ` Dave Jiang
2025-06-24 14:13 ` [PATCH v17 02/22] sfc: add cxl support alejandro.lucero-palau
2025-06-25 16:37 ` Jonathan Cameron
2025-06-30 14:52 ` Alejandro Lucero Palau
2025-06-30 14:55 ` Alejandro Lucero Palau
2025-06-30 16:07 ` Jonathan Cameron
2025-07-25 22:16 ` dan.j.williams
2025-08-06 8:37 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 03/22] cxl: Move pci generic code alejandro.lucero-palau
2025-07-25 22:41 ` dan.j.williams
2025-08-06 8:46 ` Alejandro Lucero Palau
2025-08-06 9:31 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 04/22] cxl: allow Type2 drivers to map cxl component regs alejandro.lucero-palau
2025-06-27 8:27 ` Jonathan Cameron
2025-07-25 22:55 ` dan.j.williams
2025-07-28 16:23 ` Dave Jiang
2025-08-06 9:43 ` Alejandro Lucero Palau
2025-08-06 9:41 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 05/22] sfc: setup cxl component regs and set media ready alejandro.lucero-palau
2025-06-27 8:39 ` Jonathan Cameron
2025-06-30 15:57 ` Alejandro Lucero Palau
2025-08-08 13:11 ` Alejandro Lucero Palau
2025-06-27 8:45 ` Jonathan Cameron
2025-08-08 13:14 ` Alejandro Lucero Palau
2025-07-25 23:04 ` dan.j.williams
2025-06-24 14:13 ` [PATCH v17 06/22] cxl: Support dpa initialization without a mailbox alejandro.lucero-palau
2025-06-27 8:42 ` Jonathan Cameron
2025-06-27 16:43 ` Dave Jiang
2025-07-01 15:23 ` Alejandro Lucero Palau
2025-06-27 8:43 ` Jonathan Cameron
2025-07-01 15:25 ` Alejandro Lucero Palau
2025-07-26 0:54 ` dan.j.williams
2025-06-24 14:13 ` [PATCH v17 07/22] sfc: initialize dpa alejandro.lucero-palau
2025-07-26 0:55 ` dan.j.williams
2025-08-08 16:59 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 08/22] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-07-26 1:05 ` dan.j.williams
2025-08-08 17:01 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 09/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-06-27 8:51 ` Jonathan Cameron
2025-07-01 15:30 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 10/22] cx/memdev: Indicate probe deferral alejandro.lucero-palau
2025-06-27 8:59 ` Jonathan Cameron
2025-06-27 9:42 ` Jonathan Cameron
2025-07-01 15:30 ` Alejandro Lucero Palau
2025-06-27 18:17 ` Dave Jiang
2025-06-30 16:20 ` Jonathan Cameron
2025-07-01 16:07 ` Alejandro Lucero Palau
2025-07-01 16:25 ` Dave Jiang
2025-07-01 16:44 ` Jonathan Cameron
2025-07-01 16:02 ` Alejandro Lucero Palau
2025-07-28 17:45 ` dan.j.williams
2025-07-30 3:46 ` dan.j.williams
2025-08-09 11:24 ` Alejandro Lucero Palau
2025-07-16 22:52 ` Dave Jiang
2025-06-24 14:13 ` [PATCH v17 11/22] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-06-27 22:42 ` Dave Jiang
2025-07-04 14:45 ` Alejandro Lucero Palau
2025-08-05 16:14 ` dan.j.williams
2025-08-11 12:04 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 12/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-06-27 9:10 ` Jonathan Cameron
2025-07-04 14:51 ` Alejandro Lucero Palau
2025-07-28 16:30 ` dan.j.williams
2025-08-11 14:24 ` Alejandro Lucero Palau
2025-09-02 7:11 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 13/22] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-06-27 9:06 ` Jonathan Cameron
2025-07-04 15:18 ` Alejandro Lucero Palau
2025-06-27 20:46 ` Dave Jiang
2025-07-04 15:21 ` Alejandro Lucero Palau [this message]
2025-06-24 14:13 ` [PATCH v17 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-06-27 9:11 ` Jonathan Cameron
2025-07-07 11:24 ` Alejandro Lucero Palau
2025-07-16 23:48 ` Dave Jiang
2025-06-24 14:13 ` [PATCH v17 15/22] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-09-03 17:20 ` Davidlohr Bueso
2025-06-24 14:13 ` [PATCH v17 16/22] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-06-27 9:13 ` Jonathan Cameron
2025-06-27 23:05 ` Dave Jiang
2025-06-30 16:20 ` Jonathan Cameron
2025-06-30 16:34 ` Dave Jiang
2025-06-24 14:13 ` [PATCH v17 17/22] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-06-24 14:13 ` [PATCH v17 18/22] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-06-27 9:32 ` Jonathan Cameron
2025-07-07 11:31 ` Alejandro Lucero Palau
2025-08-05 16:33 ` dan.j.williams
2025-08-11 14:45 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 19/22] cxl: Avoid dax creation for accelerators alejandro.lucero-palau
2025-06-27 9:33 ` Jonathan Cameron
2025-09-03 17:24 ` Davidlohr Bueso
2025-06-24 14:13 ` [PATCH v17 20/22] sfc: create cxl region alejandro.lucero-palau
2025-06-27 9:38 ` Jonathan Cameron
2025-07-07 11:37 ` Alejandro Lucero Palau
2025-07-28 16:20 ` dan.j.williams
2025-08-11 14:38 ` Alejandro Lucero Palau
2025-06-24 14:13 ` [PATCH v17 21/22] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-06-24 14:13 ` [PATCH v17 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-06-27 9:46 ` Jonathan Cameron
2025-07-07 12:06 ` Alejandro Lucero Palau
2025-08-27 17:26 ` ALOK TIWARI
2025-07-25 20:51 ` [PATCH v17 00/22] Type2 device basic support dan.j.williams
2025-07-25 21:11 ` dan.j.williams
2025-08-27 16:48 ` PJ Waskiewicz
2025-08-28 8:02 ` Alejandro Lucero Palau
2025-09-04 17:48 ` PJ Waskiewicz
2025-09-05 23:23 ` PJ Waskiewicz
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