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From: Dave Jiang <dave.jiang@intel.com>
To: Steven Rostedt <rostedt@goodmis.org>
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org,
	dan.j.williams@intel.com, ira.weiny@intel.com,
	vishal.l.verma@intel.com, alison.schofield@intel.com,
	Jonathan.Cameron@huawei.com, terry.bowman@amd.com,
	bhelgaas@google.com
Subject: Re: [PATCH v3 08/11] cxl/pci: add tracepoint events for CXL RAS
Date: Fri, 18 Nov 2022 10:31:44 -0700	[thread overview]
Message-ID: <e9db375a-34bd-cc21-7650-a9d074a060b7@intel.com> (raw)
In-Reply-To: <20221118121731.128df10c@gandalf.local.home>



On 11/18/2022 10:17 AM, Steven Rostedt wrote:
> On Fri, 18 Nov 2022 10:08:49 -0700
> Dave Jiang <dave.jiang@intel.com> wrote:
> 
>> +TRACE_EVENT(cxl_aer_uncorrectable_error,
>> +	TP_PROTO(const char *dev_name, u32 status, u32 fe, u32 *hl),
>> +	TP_ARGS(dev_name, status, fe, hl),
>> +	TP_STRUCT__entry(
>> +		__string(dev_name, dev_name)
>> +		__field(u32, status)
>> +		__field(u32, first_error)
>> +		__dynamic_array(u32, header_log, CXL_HEADERLOG_SIZE_U32)
> 
> If this is a fixed size, you do not need to use __dynamic_array, but
> instead just use __array()
> 
> 		__array(u32, header_log, CXL_HEADERLOG_SIZE_U32);

Thanks! I will update.

> 
>> +	),
>> +	TP_fast_assign(
>> +		__assign_str(dev_name, dev_name);
>> +		__entry->status = status;
>> +		__entry->first_error = fe;
>> +		/*
>> +		 * Embed the 512B headerlog data for user app retrieval and
>> +		 * parsing, but no need to print this in the trace buffer.
>> +		 */
>> +		memcpy(__get_dynamic_array(header_log), hl, CXL_HEADERLOG_SIZE);
> 
> 		memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);
> 
> This will be smaller and faster.
> 
> -- Steve
> 
> 
>> +	),
>> +	TP_printk("%s: status: '%s' first_error: '%s'",
>> +		  __get_str(dev_name),
>> +		  show_uc_errs(__entry->status),
>> +		  show_uc_errs(__entry->first_error)
>> +	)
>> +);
>> +

  reply	other threads:[~2022-11-18 17:32 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-18 17:08 [PATCH v3 00/11] cxl/pci: Add fundamental error handling Dave Jiang
2022-11-18 17:08 ` [PATCH v3 01/11] cxl/pci: Cleanup repeated code in cxl_probe_regs() helpers Dave Jiang
2022-11-18 17:08 ` [PATCH v3 02/11] cxl/pci: Cleanup cxl_map_device_regs() Dave Jiang
2022-11-18 17:08 ` [PATCH v3 03/11] cxl/pci: Kill cxl_map_regs() Dave Jiang
2022-11-18 17:08 ` [PATCH v3 04/11] cxl/core/regs: Make cxl_map_{component, device}_regs() device generic Dave Jiang
2022-11-18 17:08 ` [PATCH v3 05/11] cxl/port: Limit the port driver to just the HDM Decoder Capability Dave Jiang
2022-11-18 17:08 ` [PATCH v3 06/11] cxl/pci: Prepare for mapping RAS Capability Structure Dave Jiang
2022-11-18 17:08 ` [PATCH v3 07/11] cxl/pci: Find and map the " Dave Jiang
2022-11-18 17:08 ` [PATCH v3 08/11] cxl/pci: add tracepoint events for CXL RAS Dave Jiang
2022-11-18 17:17   ` Steven Rostedt
2022-11-18 17:31     ` Dave Jiang [this message]
2022-11-21 11:37   ` Jonathan Cameron
2022-11-21 13:08   ` Shiju Jose
2022-11-28 17:54     ` Dave Jiang
2022-11-18 17:08 ` [PATCH v3 09/11] cxl/pci: Add (hopeful) error handling support Dave Jiang
2022-11-21 11:56   ` Jonathan Cameron
2022-11-18 17:09 ` [PATCH v3 10/11] PCI/AER: Add optional logging callback for correctable error Dave Jiang
2022-11-19  1:08   ` Sathyanarayanan Kuppuswamy
2022-11-28 18:19     ` Dave Jiang
2022-11-21 12:05   ` Jonathan Cameron
2022-11-21 12:17     ` Jonathan Cameron
2022-11-28 21:01     ` Dave Jiang
2022-11-18 17:09 ` [PATCH v3 11/11] cxl/pci: Add callback to log AER " Dave Jiang
2022-11-21 12:21   ` Jonathan Cameron

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