From: Alejandro Lucero Palau <alucerop@amd.com>
To: Dan Williams <dan.j.williams@intel.com>,
alejandro.lucero-palau@amd.com, linux-cxl@vger.kernel.org,
netdev@vger.kernel.org, edward.cree@amd.com, davem@davemloft.net,
kuba@kernel.org, pabeni@redhat.com, edumazet@google.com,
dave.jiang@intel.com
Cc: Ben Cheatham <benjamin.cheatham@amd.com>,
Jonathan Cameron <Jonathan.Cameron@huawei.com>
Subject: Re: [PATCH v16 07/22] cxl: Support dpa initialization without a mailbox
Date: Thu, 22 May 2025 11:24:19 +0100 [thread overview]
Message-ID: <edb78c4e-f9ad-410d-907c-0564222f455f@amd.com> (raw)
In-Reply-To: <682e1fc963402_1626e1001c@dwillia2-xfh.jf.intel.com.notmuch>
On 5/21/25 19:47, Dan Williams wrote:
> alejandro.lucero-palau@ wrote:
>> From: Alejandro Lucero <alucerop@amd.com>
>>
>> Type3 relies on mailbox CXL_MBOX_OP_IDENTIFY command for initializing
>> memdev state params which end up being used for DMA initialization.
>>
>> Allow a Type2 driver to initialize DPA simply by giving the size of its
>> volatile and/or non-volatile hardware partitions.
>>
>> Export cxl_dpa_setup as well for initializing those added DPA partitions
>> with the proper resources.
>>
>> Signed-off-by: Alejandro Lucero <alucerop@amd.com>
>> Reviewed-by: Ben Cheatham <benjamin.cheatham@amd.com>
>> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
>> ---
>> drivers/cxl/core/mbox.c | 26 ++++++++++++++++++++------
>> drivers/cxl/cxlmem.h | 13 -------------
>> include/cxl/cxl.h | 14 ++++++++++++++
>> 3 files changed, 34 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
>> index ab994d459f46..b14cfc6e3dba 100644
>> --- a/drivers/cxl/core/mbox.c
>> +++ b/drivers/cxl/core/mbox.c
>> @@ -1284,6 +1284,22 @@ static void add_part(struct cxl_dpa_info *info, u64 start, u64 size, enum cxl_pa
>> info->nr_partitions++;
>> }
>>
>> +/**
>> + * cxl_mem_dpa_init: initialize dpa by a driver without a mailbox.
>> + *
>> + * @info: pointer to cxl_dpa_info
>> + * @volatile_bytes: device volatile memory size
>> + * @persistent_bytes: device persistent memory size
>> + */
>> +void cxl_mem_dpa_init(struct cxl_dpa_info *info, u64 volatile_bytes,
>> + u64 persistent_bytes)
> I struggle to imagine a Type-2 device with PMEM, or needing anything
> more complicated than a single volatile range. No need to pre-enable
> something that may never exist.
>
> Lets just have a cxl_set_capacity() for the simple / common case:
>
> int cxl_set_capacity(struct cxl_dev_state *cxlds, u64 capacity)
> {
> struct cxl_dpa_info range_info = { 0 };
>
> add_part(info, 0, capacity, CXL_PARTMODE_RAM);
> return cxl_dpa_setup(cxlds, &range_info);
> }
>
> ...then there is no need to move 'struct cxl_dpa_info' to a public
> header, or require type-2 drivers to pass in a pointless PMEM capacity.
>
> If more complicated devices show up later the code can always be made
> more sophisticated at that point.
That seems fine to me. The only problem I see is a driver with a mailbox
will initialize this differently, getting the cxl_dpa_info first, then
calling cxl_setup_dpa, or all that also hidden in another function. In
any case, I guess the first driver needing that will have to work it out.
next prev parent reply other threads:[~2025-05-22 10:24 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-05-14 13:27 [PATCH v16 00/22] Type2 device basic support alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 01/22] cxl: Add type2 " alejandro.lucero-palau
2025-05-20 2:43 ` Alison Schofield
2025-05-20 7:18 ` Alejandro Lucero Palau
2025-05-20 20:06 ` Dave Jiang
2025-05-21 9:30 ` Alejandro Lucero Palau
2025-05-20 7:17 ` dan.j.williams
2025-05-21 10:44 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 02/22] sfc: add cxl support alejandro.lucero-palau
2025-05-20 7:37 ` dan.j.williams
2025-05-21 10:50 ` Alejandro Lucero Palau
2025-05-21 17:12 ` Dan Williams
2025-05-22 8:49 ` Alejandro Lucero Palau
2025-05-22 19:41 ` Dan Williams
2025-06-04 8:09 ` Jonathan Cameron
2025-05-14 13:27 ` [PATCH v16 03/22] cxl: Move pci generic code alejandro.lucero-palau
2025-05-20 2:42 ` Alison Schofield
2025-05-21 17:44 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 04/22] cxl: Move register/capability check to driver alejandro.lucero-palau
2025-05-20 2:41 ` Alison Schofield
2025-05-21 18:23 ` Dan Williams
2025-05-22 9:45 ` Alejandro Lucero Palau
2025-05-22 19:51 ` Dan Williams
2025-05-23 9:12 ` Alejandro Lucero Palau
2025-05-23 16:55 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 05/22] cxl: Add function for type2 cxl regs setup alejandro.lucero-palau
2025-05-20 2:41 ` Alison Schofield
2025-05-21 18:28 ` Dan Williams
2025-05-22 9:52 ` Alejandro Lucero Palau
2025-05-22 20:04 ` Dan Williams
2025-06-06 11:59 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 06/22] sfc: make regs setup with checking and set media ready alejandro.lucero-palau
2025-05-21 18:34 ` Dan Williams
2025-05-22 10:07 ` Alejandro Lucero Palau
2025-05-22 20:22 ` Dan Williams
2025-05-22 20:53 ` Dan Williams
2025-05-22 21:09 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 07/22] cxl: Support dpa initialization without a mailbox alejandro.lucero-palau
2025-05-20 2:40 ` Alison Schofield
2025-05-21 18:47 ` Dan Williams
2025-05-22 10:24 ` Alejandro Lucero Palau [this message]
2025-05-14 13:27 ` [PATCH v16 08/22] sfc: initialize dpa alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 09/22] cxl: Prepare memdev creation for type2 alejandro.lucero-palau
2025-05-20 2:40 ` Alison Schofield
2025-05-21 18:49 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 10/22] sfc: create type2 cxl memdev alejandro.lucero-palau
2025-05-14 13:27 ` [PATCH v16 11/22] cxl: Define a driver interface for HPA free space enumeration alejandro.lucero-palau
2025-05-20 2:36 ` Alison Schofield
2025-05-21 19:31 ` Dan Williams
2025-05-22 10:56 ` Alejandro Lucero Palau
2025-05-22 20:31 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 12/22] sfc: obtain root decoder with enough HPA free space alejandro.lucero-palau
2025-05-21 19:56 ` Dan Williams
2025-06-06 12:59 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 13/22] cxl: Define a driver interface for DPA allocation alejandro.lucero-palau
2025-05-20 2:39 ` Alison Schofield
2025-05-21 20:23 ` Dan Williams
2025-06-06 13:09 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 14/22] sfc: get endpoint decoder alejandro.lucero-palau
2025-05-21 20:28 ` Dan Williams
2025-05-14 13:27 ` [PATCH v16 15/22] cxl: Make region type based on endpoint type alejandro.lucero-palau
2025-05-20 2:39 ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 16/22] cxl/region: Factor out interleave ways setup alejandro.lucero-palau
2025-05-20 2:37 ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 17/22] cxl/region: Factor out interleave granularity setup alejandro.lucero-palau
2025-05-20 2:38 ` Alison Schofield
2025-05-14 13:27 ` [PATCH v16 18/22] cxl: Allow region creation by type2 drivers alejandro.lucero-palau
2025-05-20 2:37 ` Alison Schofield
2025-05-21 20:45 ` Dan Williams
2025-06-06 13:27 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 19/22] cxl: Add region flag for precluding a device memory to be used for dax alejandro.lucero-palau
2025-05-20 2:36 ` Alison Schofield
2025-05-21 20:49 ` Dan Williams
2025-06-06 13:39 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 20/22] sfc: create cxl region alejandro.lucero-palau
2025-05-21 21:01 ` Dan Williams
2025-06-06 13:44 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 21/22] cxl: Add function for obtaining region range alejandro.lucero-palau
2025-05-20 2:35 ` Alison Schofield
2025-05-21 21:31 ` Dan Williams
2025-06-06 14:03 ` Alejandro Lucero Palau
2025-05-14 13:27 ` [PATCH v16 22/22] sfc: support pio mapping based on cxl alejandro.lucero-palau
2025-05-21 21:48 ` Dan Williams
2025-05-23 1:13 ` Edward Cree
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