Re: [PATCH v2 3/3] cxl/pci: Update only the Port GPF timeout fields

[Dave Jiang <dave.jiang@intel.com>]

On 10/7/26 8:46 PM, Guixin Liu wrote:
> update_gpf_port_dvsec() rebuilds the phase control register from just
> the timeout base and scale, so the rest of the register is cleared by
> the write. The other bits are reserved today and nothing is lost, but
> the full-register rewrite would clobber any field the spec defines
> there later.
> 
> Read-modify-write the register and change only the two timeout
> fields.
> 
> Fixes: a52b6a2c1c99 ("cxl/pci: Support Global Persistent Flush (GPF)")
> Assisted-by: LLM
> Signed-off-by: Guixin Liu <kanie@linux.alibaba.com>

Reviewed-by: Dave Jiang <dave.jiang@intel.com>

> ---
>  drivers/cxl/core/pci.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/cxl/core/pci.c b/drivers/cxl/core/pci.c
> index 1f470ab0df3b..edf0b47f39db 100644
> --- a/drivers/cxl/core/pci.c
> +++ b/drivers/cxl/core/pci.c
> @@ -846,8 +846,8 @@ static int update_gpf_port_dvsec(struct pci_dev *pdev, int dvsec, int phase)
>  	    FIELD_GET(scale, ctrl) == GPF_TIMEOUT_SCALE_MAX)
>  		return 0;
>  
> -	ctrl = FIELD_PREP(base, GPF_TIMEOUT_BASE_MAX);
> -	ctrl |= FIELD_PREP(scale, GPF_TIMEOUT_SCALE_MAX);
> +	FIELD_MODIFY(base, &ctrl, GPF_TIMEOUT_BASE_MAX);
> +	FIELD_MODIFY(scale, &ctrl, GPF_TIMEOUT_SCALE_MAX);
>  
>  	rc = pci_write_config_word(pdev, dvsec + offset, ctrl);
>  	if (rc) {