Re: [PATCH v4 0/3] perf/cxlpmu: Misc updates

[Dave Jiang <dave.jiang@intel.com>]

On 7/16/26 9:47 AM, Will Deacon wrote:
> On Thu, Jul 16, 2026 at 09:46:05AM -0700, Dave Jiang wrote:
>>
>>
>> On 7/15/26 12:14 PM, Davidlohr Bueso wrote:
>>> Hello,
>>>
>>> Changes from v3 (https://lore.kernel.org/all/20260713061112.105419-1-dave@stgolabs.net/):
>>>  - Validate the event vendor ID for CRB filtering, the Table 13-5
>>>    event groups are scoped by the CXL VID in patch 3 (Richard).
>>>  - Add Richard's Reviewed-by tag to patch 1.
>>>
>>> Three patches for the CXL PMU driver.
>>>
>>> Patch 1 is a standalone fix.
>>>
>>> Patch 2 adds the CXL 4.0 events that hardware exposes but the
>>> driver did not. It now precedes the filter work as the latter
>>> refers to the new event group IDs.
>>>
>>> Patch 3 implements Channel/Rank/Bank (CRB) filtering, now permitted
>>> for all event groups that CXL 4.0 Table 13-5 allows Filter ID 1 on.
>>>
>>> v2 was tested on real hardware. The v4 changes have been exercised
>>> under qemu CPMU emulation (jic23 tree) + changes for the new events/Filter=1:
>>>
>>>     https://lore.kernel.org/all/20260715190050.458288-1-dave@stgolabs.net/
>>>
>>> Thanks!
>>>
>>> Davidlohr Bueso (1):
>>>   perf/cxlpmu: Fix 64-bit write to 32-bit HDM filter register
>>>
>>> Harshal Thakkar (2):
>>>   perf/cxlpmu: Add missing CXL 4.0 events
>>>   perf/cxlpmu: Support Channel/Rank/Bank filter
>>>
>>>  drivers/perf/cxl_pmu.c | 119 +++++++++++++++++++++++++++++++++++++++--
>>>  1 file changed, 116 insertions(+), 3 deletions(-)
>>>
>>>
>>> base-commit: d60ec36cab338dfe2ae40d73e9c8d6c4af70d2b8
>>
>> For the series
>> Reviewed-by: Dave Jiang <dave.jiang@intel.com>
>>
>>
>> This is being picked up by the perf maintainer right?
> 
> Yeah, I'll grab it eventually. Just a bit swamped atm.

Thanks Will! Wasn't trying to rush you. Just checking to see which acceptance path the series is going through.

> 
> Will