From: Dave Jiang <dave.jiang@intel.com>
To: linux-cxl@vger.kernel.org, nvdimm@lists.linux.dev
Cc: dan.j.williams@intel.com, jmoyer@redhat.com, vishal.l.verma@intel.com
Subject: Re: [ndctl PATCH v3 1/4] ndctl: add CXL bus detection
Date: Fri, 16 Dec 2022 10:23:19 -0700 [thread overview]
Message-ID: <f804d081-abb9-cb46-e14f-a37f3ac63f21@intel.com> (raw)
In-Reply-To: <167121128334.3620577.18417349282991011007.stgit@djiang5-desk3.ch.intel.com>
On 12/16/2022 10:21 AM, Dave Jiang wrote:
> Add a CXL bus type, and detect whether a 'dimm' is backed by the CXL
> subsystem.
>
> Reviewed-by: Alison Schofield <alison.schofield@intel.com>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
>
> ---
> v3:
> - Simplify detecting cxl subsystem. (Dan)
> v2:
> - Improve commit log. (Vishal)
> ---
> ndctl/lib/libndctl.c | 30 ++++++++++++++++++++++++++++++
> ndctl/lib/libndctl.sym | 1 +
> ndctl/lib/private.h | 1 +
> ndctl/libndctl.h | 1 +
> 4 files changed, 33 insertions(+)
>
> diff --git a/ndctl/lib/libndctl.c b/ndctl/lib/libndctl.c
> index ad54f0626510..9cd5340b5702 100644
> --- a/ndctl/lib/libndctl.c
> +++ b/ndctl/lib/libndctl.c
> @@ -12,6 +12,7 @@
> #include <ctype.h>
> #include <fcntl.h>
> #include <dirent.h>
> +#include <libgen.h>
Of course I missed removing this change.
> #include <sys/stat.h>
> #include <sys/types.h>
> #include <sys/ioctl.h>
> @@ -876,6 +877,24 @@ static enum ndctl_fwa_method fwa_method_to_method(const char *fwa_method)
> return NDCTL_FWA_METHOD_RESET;
> }
>
> +static int is_subsys_cxl(const char *subsys)
> +{
> + char *path;
> + int rc;
> +
> + path = realpath(subsys, NULL);
> + if (!path)
> + return -errno;
> +
> + if (!strcmp(subsys, "/sys/bus/cxl"))
> + rc = 1;
> + else
> + rc = 0;
> +
> + free(path);
> + return rc;
> +}
> +
> static void *add_bus(void *parent, int id, const char *ctl_base)
> {
> char buf[SYSFS_ATTR_SIZE];
> @@ -919,6 +938,12 @@ static void *add_bus(void *parent, int id, const char *ctl_base)
> else
> bus->has_of_node = 1;
>
> + sprintf(path, "%s/device/../subsys", ctl_base);
> + if (is_subsys_cxl(path))
> + bus->has_cxl = 1;
> + else
> + bus->has_cxl = 0;
> +
> sprintf(path, "%s/device/nfit/dsm_mask", ctl_base);
> if (sysfs_read_attr(ctx, path, buf) < 0)
> bus->nfit_dsm_mask = 0;
> @@ -1050,6 +1075,11 @@ NDCTL_EXPORT int ndctl_bus_has_of_node(struct ndctl_bus *bus)
> return bus->has_of_node;
> }
>
> +NDCTL_EXPORT int ndctl_bus_has_cxl(struct ndctl_bus *bus)
> +{
> + return bus->has_cxl;
> +}
> +
> NDCTL_EXPORT int ndctl_bus_is_papr_scm(struct ndctl_bus *bus)
> {
> char buf[SYSFS_ATTR_SIZE];
> diff --git a/ndctl/lib/libndctl.sym b/ndctl/lib/libndctl.sym
> index 75c32b9d4967..2892544d1985 100644
> --- a/ndctl/lib/libndctl.sym
> +++ b/ndctl/lib/libndctl.sym
> @@ -464,4 +464,5 @@ LIBNDCTL_27 {
> } LIBNDCTL_26;
> LIBNDCTL_28 {
> ndctl_dimm_disable_master_passphrase;
> + ndctl_bus_has_cxl;
> } LIBNDCTL_27;
> diff --git a/ndctl/lib/private.h b/ndctl/lib/private.h
> index e5c56295556d..46bc8908bd90 100644
> --- a/ndctl/lib/private.h
> +++ b/ndctl/lib/private.h
> @@ -163,6 +163,7 @@ struct ndctl_bus {
> int regions_init;
> int has_nfit;
> int has_of_node;
> + int has_cxl;
> char *bus_path;
> char *bus_buf;
> size_t buf_len;
> diff --git a/ndctl/libndctl.h b/ndctl/libndctl.h
> index c52e82a6f826..91ef0f42f654 100644
> --- a/ndctl/libndctl.h
> +++ b/ndctl/libndctl.h
> @@ -133,6 +133,7 @@ struct ndctl_bus *ndctl_bus_get_next(struct ndctl_bus *bus);
> struct ndctl_ctx *ndctl_bus_get_ctx(struct ndctl_bus *bus);
> int ndctl_bus_has_nfit(struct ndctl_bus *bus);
> int ndctl_bus_has_of_node(struct ndctl_bus *bus);
> +int ndctl_bus_has_cxl(struct ndctl_bus *bus);
> int ndctl_bus_is_papr_scm(struct ndctl_bus *bus);
> unsigned int ndctl_bus_get_major(struct ndctl_bus *bus);
> unsigned int ndctl_bus_get_minor(struct ndctl_bus *bus);
>
>
next prev parent reply other threads:[~2022-12-16 17:23 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-14 22:00 [ndctl PATCH v2 0/4] ndctl: Add security test for cxl devices through nvdimm Dave Jiang
2022-12-14 22:00 ` [ndctl PATCH v2 1/4] ndctl: add CXL bus detection Dave Jiang
2022-12-15 20:38 ` Dan Williams
2022-12-15 21:18 ` Jeff Moyer
2022-12-15 22:27 ` Dan Williams
2022-12-16 17:21 ` [ndctl PATCH v3 " Dave Jiang
2022-12-16 17:23 ` Dave Jiang [this message]
2022-12-16 18:44 ` Dan Williams
2023-01-04 20:30 ` [ndctl PATCH v4 " Dave Jiang
2022-12-14 22:00 ` [ndctl PATCH v2 2/4] ndctl/libndctl: Add bus_prefix for CXL Dave Jiang
2022-12-14 22:00 ` [ndctl PATCH v2 3/4] ndctl/libndctl: Allow retrievng of unique_id for CXL mem dev Dave Jiang
2022-12-14 22:00 ` [ndctl PATCH v2 4/4] ndctl/test: Add CXL test for security Dave Jiang
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