From: "Verma, Vishal L" <vishal.l.verma@intel.com>
To: "Jiang, Dave" <dave.jiang@intel.com>,
"linux-cxl@vger.kernel.org" <linux-cxl@vger.kernel.org>,
"nvdimm@lists.linux.dev" <nvdimm@lists.linux.dev>
Subject: Re: [NDCTL PATCH v7 4/4] ndctl: add test for qos_class in CXL test suite
Date: Fri, 23 Feb 2024 22:07:41 +0000 [thread overview]
Message-ID: <fab7eaa31a7211bc62f17afb5aea47c2cc8dfe87.camel@intel.com> (raw)
In-Reply-To: <20240208201435.2081583-5-dave.jiang@intel.com>
On Thu, 2024-02-08 at 13:11 -0700, Dave Jiang wrote:
> Add tests in cxl-qos-class.sh to verify qos_class are set with the fake
> qos_class create by the kernel. Root decoders should have qos_class
> attribute set. Memory devices should have ram_qos_class or pmem_qos_class
> set depending on which partitions are valid.
>
> Signed-off-by: Dave Jiang <dave.jiang@intel.com>
> ---
> v7:
> - Add create_region -Q testing (Vishal)
> ---
> test/common | 4 ++
> test/cxl-qos-class.sh | 102 ++++++++++++++++++++++++++++++++++++++++++
> test/meson.build | 2 +
> 3 files changed, 108 insertions(+)
> create mode 100755 test/cxl-qos-class.sh
>
> diff --git a/test/common b/test/common
> index f1023ef20f7e..5694820c7adc 100644
> --- a/test/common
> +++ b/test/common
> @@ -150,3 +150,7 @@ check_dmesg()
> grep -q "Call Trace" <<< $log && err $1
> true`
> }
> +
> +
> +# CXL COMMON
> +TEST_QOS_CLASS=42
> diff --git a/test/cxl-qos-class.sh b/test/cxl-qos-class.sh
> new file mode 100755
> index 000000000000..145df6134685
> --- /dev/null
> +++ b/test/cxl-qos-class.sh
> @@ -0,0 +1,102 @@
> +#!/bin/bash
> +# SPDX-License-Identifier: GPL-2.0
> +# Copyright (C) 2024 Intel Corporation. All rights reserved.
> +
> +. $(dirname $0)/common
> +
> +rc=77
> +
> +set -ex
> +
> +trap 'err $LINENO' ERR
> +
> +check_prereq "jq"
> +
> +modprobe -r cxl_test
> +modprobe cxl_test
> +rc=1
> +
> +check_qos_decoders () {
> + # check root decoders have expected fake qos_class
> + # also make sure the number of root decoders equal to the number
> + # with qos_class found
> + json=$($CXL list -b cxl_test -D -d root)
> + decoders=$(echo "$json" | jq length)
> + count=0
> + while read -r qos_class
> + do
For consistency, the script based tests all have the while..do,
for..do, if..then bits on the same line. Would be nice not to break
that precedent.
> + ((qos_class == TEST_QOS_CLASS)) || err "$LINENO"
> + count=$((count+1))
> + done <<< "$(echo "$json" | jq -r '.[] | .qos_class')"
> +
> + ((count == decoders)) || err "$LINENO";
> +}
> +
> +check_qos_memdevs () {
> + # Check that memdevs that expose ram_qos_class or pmem_qos_class have
> + # expected fake value programmed.
> + json=$(cxl list -b cxl_test -M)
> + readarray -t lines < <(jq ".[] | .ram_size, .pmem_size, .ram_qos_class, .pmem_qos_class" <<<"$json")
> + for (( i = 0; i < ${#lines[@]}; i += 4 ))
> + do
> + ram_size=${lines[i]}
> + pmem_size=${lines[i+1]}
> + ram_qos_class=${lines[i+2]}
> + pmem_qos_class=${lines[i+3]}
Hm instead of splitting into lines, and then looping through them, why
not just invoke jq for each?
ram_size=$(jq ".[] | .ram_size" <<< $json)
pmem_size=$(jq ".[] | .pmem_size" <<< $json)
...etc
> +
> + if [[ "$ram_size" != null ]]
> + then
> + ((ram_qos_class == TEST_QOS_CLASS)) || err "$LINENO"
> + fi
This might be a bit more readable as:
if [[ "$ram_size" != null ]] && ((ram_qos_class != TEST_QOS_CLASS)); then
err "$LINENO"
fi
> + if [[ "$pmem_size" != null ]]
> + then
> + ((pmem_qos_class == TEST_QOS_CLASS)) || err "$LINENO"
> + fi
> + done
> +}
> +
> +# Based on cxl-create-region.sh create_single()
> +destroy_regions()
> +{
> + if [[ "$*" ]]; then
> + $CXL destroy-region -f -b cxl_test "$@"
> + else
> + $CXL destroy-region -f -b cxl_test all
> + fi
> +}
> +
> +create_region_check_qos()
> +{
> + # the 5th cxl_test decoder is expected to target a single-port
> + # host-bridge. Older cxl_test implementations may not define it,
> + # so skip the test in that case.
> + decoder=$($CXL list -b cxl_test -D -d root |
> + jq -r ".[4] |
> + select(.pmem_capable == true) |
> + select(.nr_targets == 1) |
> + .decoder")
> +
> + if [[ ! $decoder ]]; then
> + echo "no single-port host-bridge decoder found, skipping"
> + return
> + fi
> +
> + # Send create-region with -Q to enforce qos_class matching
> + region=$($CXL create-region -Q -d "$decoder" | jq -r ".region")
> + if [[ ! $region ]]; then
> + echo "failed to create single-port host-bridge region"
> + err "$LINENO"
> + fi
> +
> + destroy_regions "$region"
> +}
> +
> +check_qos_decoders
> +
> +check_qos_memdevs
> +
> +create_region_check_qos
> +
> +check_dmesg "$LINEO"
> +
> +modprobe -r cxl_test
> diff --git a/test/meson.build b/test/meson.build
> index 5eb35749a95b..4892df11119f 100644
> --- a/test/meson.build
> +++ b/test/meson.build
> @@ -160,6 +160,7 @@ cxl_events = find_program('cxl-events.sh')
> cxl_poison = find_program('cxl-poison.sh')
> cxl_sanitize = find_program('cxl-sanitize.sh')
> cxl_destroy_region = find_program('cxl-destroy-region.sh')
> +cxl_qos_class = find_program('cxl-qos-class.sh')
>
> tests = [
> [ 'libndctl', libndctl, 'ndctl' ],
> @@ -192,6 +193,7 @@ tests = [
> [ 'cxl-poison.sh', cxl_poison, 'cxl' ],
> [ 'cxl-sanitize.sh', cxl_sanitize, 'cxl' ],
> [ 'cxl-destroy-region.sh', cxl_destroy_region, 'cxl' ],
> + [ 'cxl-qos-class.sh', cxl_qos_class, 'cxl' ],
> ]
>
> if get_option('destructive').enabled()
next prev parent reply other threads:[~2024-02-23 22:07 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-08 20:11 [NDCTL PATCH v7 4/4] ndctl: Add support of qos_class for CXL CLI Dave Jiang
2024-02-08 20:11 ` [NDCTL PATCH v7 1/4] ndctl: cxl: Add QoS class retrieval for the root decoder Dave Jiang
2024-02-08 20:11 ` [NDCTL PATCH v7 2/4] ndctl: cxl: Add QoS class support for the memory device Dave Jiang
2024-02-08 20:11 ` [NDCTL PATCH v7 3/4] ndctl: cxl: add QoS class check for CXL region creation Dave Jiang
2024-02-23 22:48 ` Verma, Vishal L
2024-02-26 21:58 ` Dave Jiang
2024-02-08 20:11 ` [NDCTL PATCH v7 4/4] ndctl: add test for qos_class in CXL test suite Dave Jiang
2024-02-22 7:59 ` Verma, Vishal L
2024-02-26 22:39 ` Dave Jiang
2024-02-23 22:07 ` Verma, Vishal L [this message]
2024-02-26 23:09 ` Dave Jiang
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