From: sashiko-bot@kernel.org
To: "Srirangan Madhavan" <smadhavan@nvidia.com>
Cc: linux-cxl@vger.kernel.org, linux-pci@vger.kernel.org
Subject: Re: [PATCH v15 09/16] PCI/CXL: Cache endpoint HDM state during PCI enumeration
Date: Sun, 11 Oct 2026 02:25:06 +0000 [thread overview]
Message-ID: <sashiko-outbox-166976@kernel.org> (raw)
In-Reply-To: <20261011021422.3428136-10-smadhavan@nvidia.com>
Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:
- [Low] Missing MODULE_IMPORT_NS("CXL") in drivers/pci/cxl.c causes modpost namespace warnings.
--
commit 316d4b1d9e38508bd7197a5097af59c2f4cb6fd4
Author: Srirangan Madhavan <smadhavan@nvidia.com>
PCI/CXL: Cache endpoint HDM state during PCI enumeration
This commit caches the HDM state in pci_dev->hdm after BAR resource
setup and before driver binding, allowing resets to restore it without
a bound CXL driver. It saves the HDM register location, decoder settings,
and Device DVSEC state, keeping PCI discovery separate from shared HDM helpers.
Link: https://git.kernel.org/pub/scm/linux/kernel/git/djiang/linux.git/commit/?id=b12baa1105f33cc1a10f9c9c0c6376194397d9f3
> diff --git a/drivers/pci/cxl.c b/drivers/pci/cxl.c
> new file mode 100644
> index 0000000000000..471b57391593e
> --- /dev/null
> +++ b/drivers/pci/cxl.c
[ ... ]
> +static void __iomem *cxl_pci_hdm_map_regs(struct pci_dev *pdev,
> + struct cxl_register_map *map,
> + resource_size_t *hdm_offset,
> + int *decoder_count)
> +{
> + struct cxl_reg_map *hdm_map = &map->component_map.hdm_decoder;
> + void __iomem *hdm;
> + int rc;
> +
> + /* cxl_setup_regs() populates hdm_map, including its valid bit. */
> + rc = cxl_setup_regs(map);
[Severity: Low]
Does this file need a MODULE_IMPORT_NS("CXL") declaration?
cxl_setup_regs() is exported via EXPORT_SYMBOL_NS_GPL(cxl_setup_regs, "CXL"),
and drivers/pci/cxl.c invokes this exported function during device enumeration.
Because the file lacks MODULE_IMPORT_NS("CXL");, it causes modpost to emit a
namespace violation warning when verifying vmlinux.o imports.
While this does not cause functional runtime failure, it pollutes the build
logs and can cause build failures under strict configurations.
> + if (rc)
> + return ERR_PTR(rc);
> + if (!hdm_map->valid)
> + return ERR_PTR(-ENODEV);
[ ... ]
--
Sashiko AI review · https://sashiko.dev/#/patchset/20261011021422.3428136-1-smadhavan@nvidia.com?part=9
next prev parent reply other threads:[~2026-10-11 2:25 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-11 2:14 [PATCH v15 00/16] PCI/CXL: Add CXL reset support for Type 2 devices Srirangan Madhavan
2026-10-11 2:14 ` [PATCH v15 01/16] cxl: Drop stale decoder interleave limit comment Srirangan Madhavan
2026-10-11 2:16 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 02/16] cxl: Share CXL port upstream PCI device lookup Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 03/16] cxl: Move decoder declarations to shared header Srirangan Madhavan
2026-10-11 2:19 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 04/16] cxl: Embed decoder configuration in a standalone structure Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 05/16] cxl: Introduce endpoint HDM decoder settings Srirangan Madhavan
2026-10-11 2:22 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 06/16] cxl: Move HDM decoder helpers to built-in code Srirangan Madhavan
2026-10-11 2:21 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 07/16] cxl: Share HDM decoder register unpacking Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 08/16] cxl: Refresh cached PCI HDM decoder settings Srirangan Madhavan
2026-10-11 2:23 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 09/16] PCI/CXL: Cache endpoint HDM state during PCI enumeration Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot [this message]
2026-10-11 2:14 ` [PATCH v15 10/16] PCI/CXL: Add CXL Device Reset sequencing Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 11/16] cxl: Validate and synchronize HDM ranges around reset Srirangan Madhavan
2026-10-11 2:21 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 12/16] PCI/CXL: Reject reset with unsafe function scope Srirangan Madhavan
2026-10-11 2:28 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 13/16] PCI/CXL: Restore CXL state after PCI reset Srirangan Madhavan
2026-10-11 2:25 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 14/16] PCI/CXL: Expose CXL Reset as a PCI reset method Srirangan Madhavan
2026-10-11 2:34 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 15/16] PCI/CXL: Restore CXL state after CXL bus reset Srirangan Madhavan
2026-10-11 2:24 ` sashiko-bot
2026-10-11 2:14 ` [PATCH v15 16/16] tools/testing/cxl: Add HDM decoder range checks Srirangan Madhavan
2026-10-11 2:22 ` sashiko-bot
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