[PATCH 00/11] clk: samsung: remove number of clocks from bindings

[PATCH 00/11] clk: samsung: remove number of clocks from bindings

[Krzysztof Kozlowski]

Hi,

No dependencies, patches can be taken in one set via my clk tree.

Best regards,
Krzysztof

Krzysztof Kozlowski (11):
  clk: samsung: exynos3250: do not define number of clocks in bindings
  clk: samsung: exynos4: do not define number of clocks in bindings
  clk: samsung: exynos5250: do not define number of clocks in bindings
  clk: samsung: exynos5260: do not define number of clocks in bindings
  clk: samsung: exynos5410: do not define number of clocks in bindings
  clk: samsung: exynos5420: do not define number of clocks in bindings
  clk: samsung: exynos5433: do not define number of clocks in bindings
  clk: samsung: exynos7885: do not define number of clocks in bindings
  clk: samsung: exynos850: do not define number of clocks in bindings
  clk: samsung: exynoautov9: do not define number of clocks in bindings
  dt-bindings: clock: samsung: remove define with number of clocks

 drivers/clk/samsung/clk-exynos3250.c          | 11 +++-
 drivers/clk/samsung/clk-exynos4.c             |  5 +-
 drivers/clk/samsung/clk-exynos4412-isp.c      |  5 +-
 drivers/clk/samsung/clk-exynos5250.c          |  5 +-
 drivers/clk/samsung/clk-exynos5260.c          | 41 ++++++++----
 drivers/clk/samsung/clk-exynos5410.c          |  5 +-
 drivers/clk/samsung/clk-exynos5420.c          |  5 +-
 drivers/clk/samsung/clk-exynos5433.c          | 65 +++++++++++++------
 drivers/clk/samsung/clk-exynos7885.c          | 14 ++--
 drivers/clk/samsung/clk-exynos850.c           | 35 ++++++----
 drivers/clk/samsung/clk-exynosautov9.c        | 29 ++++++---
 include/dt-bindings/clock/exynos3250.h        | 18 -----
 include/dt-bindings/clock/exynos4.h           |  5 --
 include/dt-bindings/clock/exynos5250.h        |  3 -
 include/dt-bindings/clock/exynos5260-clk.h    | 25 -------
 include/dt-bindings/clock/exynos5410.h        |  2 -
 include/dt-bindings/clock/exynos5420.h        |  3 -
 include/dt-bindings/clock/exynos5433.h        | 42 ------------
 include/dt-bindings/clock/exynos7885.h        |  4 --
 include/dt-bindings/clock/exynos850.h         | 10 ---
 .../dt-bindings/clock/samsung,exynosautov9.h  | 18 -----
 21 files changed, 154 insertions(+), 196 deletions(-)

-- 
2.34.1

[PATCH 01/11] clk: samsung: exynos3250: do not define number of clocks in bindings

[Krzysztof Kozlowski]

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore this number of clocks
should not be in the bindings, because otherwise we should not change
it.

Define number of clocks per each clock controller inside the driver
directly.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 drivers/clk/samsung/clk-exynos3250.c | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos3250.c b/drivers/clk/samsung/clk-exynos3250.c
index 6cc65ccf867c..a02461667664 100644
--- a/drivers/clk/samsung/clk-exynos3250.c
+++ b/drivers/clk/samsung/clk-exynos3250.c
@@ -100,6 +100,11 @@
 #define PWR_CTRL1_USE_CORE1_WFI			(1 << 1)
 #define PWR_CTRL1_USE_CORE0_WFI			(1 << 0)
 
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR_MAIN				(CLK_SCLK_MMC2 + 1)
+#define CLKS_NR_DMC				(CLK_DIV_DMCD + 1)
+#define CLKS_NR_ISP				(CLK_SCLK_MPWM_ISP + 1)
+
 static const unsigned long exynos3250_cmu_clk_regs[] __initconst = {
 	SRC_LEFTBUS,
 	DIV_LEFTBUS,
@@ -807,7 +812,7 @@ static const struct samsung_cmu_info cmu_info __initconst = {
 	.nr_fixed_factor_clks	= ARRAY_SIZE(fixed_factor_clks),
 	.cpu_clks		= exynos3250_cpu_clks,
 	.nr_cpu_clks		= ARRAY_SIZE(exynos3250_cpu_clks),
-	.nr_clk_ids		= CLK_NR_CLKS,
+	.nr_clk_ids		= CLKS_NR_MAIN,
 	.clk_regs		= exynos3250_cmu_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(exynos3250_cmu_clk_regs),
 };
@@ -923,7 +928,7 @@ static const struct samsung_cmu_info dmc_cmu_info __initconst = {
 	.nr_mux_clks		= ARRAY_SIZE(dmc_mux_clks),
 	.div_clks		= dmc_div_clks,
 	.nr_div_clks		= ARRAY_SIZE(dmc_div_clks),
-	.nr_clk_ids		= NR_CLKS_DMC,
+	.nr_clk_ids		= CLKS_NR_DMC,
 	.clk_regs		= exynos3250_cmu_dmc_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs),
 };
@@ -1067,7 +1072,7 @@ static const struct samsung_cmu_info isp_cmu_info __initconst = {
 	.nr_div_clks	= ARRAY_SIZE(isp_div_clks),
 	.gate_clks	= isp_gate_clks,
 	.nr_gate_clks	= ARRAY_SIZE(isp_gate_clks),
-	.nr_clk_ids	= NR_CLKS_ISP,
+	.nr_clk_ids	= CLKS_NR_ISP,
 };
 
 static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)
-- 
2.34.1

RE: [PATCH 01/11] clk: samsung: exynos3250: do not define number of clocks in bindings

[Alim Akhtar]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Tuesday, August 8, 2023 1:57 PM
> To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Sylwester
> Nawrocki <s.nawrocki@samsung.com>; Tomasz Figa
> <tomasz.figa@gmail.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim
> Akhtar <alim.akhtar@samsung.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob
> Herring <robh+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org
> Subject: [PATCH 01/11] clk: samsung: exynos3250: do not define number of
> clocks in bindings
> 
> Number of clocks supported by Linux drivers might vary - sometimes we add
> new clocks, not exposed previously.  Therefore this number of clocks
should
> not be in the bindings, because otherwise we should not change it.
> 
> Define number of clocks per each clock controller inside the driver
directly.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

>  drivers/clk/samsung/clk-exynos3250.c | 11 ++++++++---
>  1 file changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos3250.c
b/drivers/clk/samsung/clk-
> exynos3250.c
> index 6cc65ccf867c..a02461667664 100644
> --- a/drivers/clk/samsung/clk-exynos3250.c
> +++ b/drivers/clk/samsung/clk-exynos3250.c
> @@ -100,6 +100,11 @@
>  #define PWR_CTRL1_USE_CORE1_WFI			(1 << 1)
>  #define PWR_CTRL1_USE_CORE0_WFI			(1 << 0)
> 
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define CLKS_NR_MAIN				(CLK_SCLK_MMC2 +
> 1)
> +#define CLKS_NR_DMC				(CLK_DIV_DMCD + 1)
> +#define CLKS_NR_ISP				(CLK_SCLK_MPWM_ISP + 1)
> +
>  static const unsigned long exynos3250_cmu_clk_regs[] __initconst = {
>  	SRC_LEFTBUS,
>  	DIV_LEFTBUS,
> @@ -807,7 +812,7 @@ static const struct samsung_cmu_info cmu_info
> __initconst = {
>  	.nr_fixed_factor_clks	= ARRAY_SIZE(fixed_factor_clks),
>  	.cpu_clks		= exynos3250_cpu_clks,
>  	.nr_cpu_clks		= ARRAY_SIZE(exynos3250_cpu_clks),
> -	.nr_clk_ids		= CLK_NR_CLKS,
> +	.nr_clk_ids		= CLKS_NR_MAIN,
>  	.clk_regs		= exynos3250_cmu_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(exynos3250_cmu_clk_regs),
>  };
> @@ -923,7 +928,7 @@ static const struct samsung_cmu_info dmc_cmu_info
> __initconst = {
>  	.nr_mux_clks		= ARRAY_SIZE(dmc_mux_clks),
>  	.div_clks		= dmc_div_clks,
>  	.nr_div_clks		= ARRAY_SIZE(dmc_div_clks),
> -	.nr_clk_ids		= NR_CLKS_DMC,
> +	.nr_clk_ids		= CLKS_NR_DMC,
>  	.clk_regs		= exynos3250_cmu_dmc_clk_regs,
>  	.nr_clk_regs		=
> ARRAY_SIZE(exynos3250_cmu_dmc_clk_regs),
>  };
> @@ -1067,7 +1072,7 @@ static const struct samsung_cmu_info isp_cmu_info
> __initconst = {
>  	.nr_div_clks	= ARRAY_SIZE(isp_div_clks),
>  	.gate_clks	= isp_gate_clks,
>  	.nr_gate_clks	= ARRAY_SIZE(isp_gate_clks),
> -	.nr_clk_ids	= NR_CLKS_ISP,
> +	.nr_clk_ids	= CLKS_NR_ISP,
>  };
> 
>  static int __init exynos3250_cmu_isp_probe(struct platform_device *pdev)
> --
> 2.34.1

[PATCH 02/11] clk: samsung: exynos4: do not define number of clocks in bindings

[Krzysztof Kozlowski]

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore this number of clocks
should not be in the bindings, because otherwise we should not change
it.

Define number of clocks per each clock controller inside the driver
directly.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 drivers/clk/samsung/clk-exynos4.c        | 5 ++++-
 drivers/clk/samsung/clk-exynos4412-isp.c | 5 ++++-
 2 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 43207257a9cc..4ec41221e68f 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -135,6 +135,9 @@
 #define PWR_CTRL1_USE_CORE1_WFI			(1 << 1)
 #define PWR_CTRL1_USE_CORE0_WFI			(1 << 0)
 
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR					(CLK_DIV_CORE2 + 1)
+
 /* the exynos4 soc type */
 enum exynos4_soc {
 	EXYNOS4210,
@@ -1275,7 +1278,7 @@ static void __init exynos4_clk_init(struct device_node *np,
 	if (!reg_base)
 		panic("%s: failed to map registers\n", __func__);
 
-	ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
+	ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
 	hws = ctx->clk_data.hws;
 
 	samsung_clk_of_register_fixed_ext(ctx, exynos4_fixed_rate_ext_clks,
diff --git a/drivers/clk/samsung/clk-exynos4412-isp.c b/drivers/clk/samsung/clk-exynos4412-isp.c
index 1470c15e95da..a70c2b06a61a 100644
--- a/drivers/clk/samsung/clk-exynos4412-isp.c
+++ b/drivers/clk/samsung/clk-exynos4412-isp.c
@@ -22,6 +22,9 @@
 #define E4X12_GATE_ISP0		0x0800
 #define E4X12_GATE_ISP1		0x0804
 
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR_ISP		(CLK_ISP_DIV_MCUISP1 + 1)
+
 /*
  * Support for CMU save/restore across system suspends
  */
@@ -121,7 +124,7 @@ static int __init exynos4x12_isp_clk_probe(struct platform_device *pdev)
 	if (!exynos4x12_save_isp)
 		return -ENOMEM;
 
-	ctx = samsung_clk_init(dev, reg_base, CLK_NR_ISP_CLKS);
+	ctx = samsung_clk_init(dev, reg_base, CLKS_NR_ISP);
 
 	platform_set_drvdata(pdev, ctx);
 
-- 
2.34.1

RE: [PATCH 02/11] clk: samsung: exynos4: do not define number of clocks in bindings

[Alim Akhtar]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Tuesday, August 8, 2023 1:57 PM
> To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Sylwester
> Nawrocki <s.nawrocki@samsung.com>; Tomasz Figa
> <tomasz.figa@gmail.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim
> Akhtar <alim.akhtar@samsung.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob
> Herring <robh+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org
> Subject: [PATCH 02/11] clk: samsung: exynos4: do not define number of
> clocks in bindings
> 
> Number of clocks supported by Linux drivers might vary - sometimes we add
> new clocks, not exposed previously.  Therefore this number of clocks
should
> not be in the bindings, because otherwise we should not change it.
> 
> Define number of clocks per each clock controller inside the driver
directly.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

>  drivers/clk/samsung/clk-exynos4.c        | 5 ++++-
>  drivers/clk/samsung/clk-exynos4412-isp.c | 5 ++++-
>  2 files changed, 8 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-
> exynos4.c
> index 43207257a9cc..4ec41221e68f 100644
> --- a/drivers/clk/samsung/clk-exynos4.c
> +++ b/drivers/clk/samsung/clk-exynos4.c
> @@ -135,6 +135,9 @@
>  #define PWR_CTRL1_USE_CORE1_WFI			(1 << 1)
>  #define PWR_CTRL1_USE_CORE0_WFI			(1 << 0)
> 
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define CLKS_NR					(CLK_DIV_CORE2 + 1)
> +
>  /* the exynos4 soc type */
>  enum exynos4_soc {
>  	EXYNOS4210,
> @@ -1275,7 +1278,7 @@ static void __init exynos4_clk_init(struct
> device_node *np,
>  	if (!reg_base)
>  		panic("%s: failed to map registers\n", __func__);
> 
> -	ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
> +	ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
>  	hws = ctx->clk_data.hws;
> 
>  	samsung_clk_of_register_fixed_ext(ctx,
> exynos4_fixed_rate_ext_clks, diff --git a/drivers/clk/samsung/clk-
> exynos4412-isp.c b/drivers/clk/samsung/clk-exynos4412-isp.c
> index 1470c15e95da..a70c2b06a61a 100644
> --- a/drivers/clk/samsung/clk-exynos4412-isp.c
> +++ b/drivers/clk/samsung/clk-exynos4412-isp.c
> @@ -22,6 +22,9 @@
>  #define E4X12_GATE_ISP0		0x0800
>  #define E4X12_GATE_ISP1		0x0804
> 
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define CLKS_NR_ISP		(CLK_ISP_DIV_MCUISP1 + 1)
> +
>  /*
>   * Support for CMU save/restore across system suspends
>   */
> @@ -121,7 +124,7 @@ static int __init exynos4x12_isp_clk_probe(struct
> platform_device *pdev)
>  	if (!exynos4x12_save_isp)
>  		return -ENOMEM;
> 
> -	ctx = samsung_clk_init(dev, reg_base, CLK_NR_ISP_CLKS);
> +	ctx = samsung_clk_init(dev, reg_base, CLKS_NR_ISP);
> 
>  	platform_set_drvdata(pdev, ctx);
> 
> --
> 2.34.1

[PATCH 03/11] clk: samsung: exynos5250: do not define number of clocks in bindings

[Krzysztof Kozlowski]

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore this number of clocks
should not be in the bindings, because otherwise we should not change
it.

Define number of clocks per each clock controller inside the driver
directly.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 drivers/clk/samsung/clk-exynos5250.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5250.c b/drivers/clk/samsung/clk-exynos5250.c
index 92fb09922f28..8ebe6155d8b7 100644
--- a/drivers/clk/samsung/clk-exynos5250.c
+++ b/drivers/clk/samsung/clk-exynos5250.c
@@ -100,6 +100,9 @@
 #define PWR_CTRL2_CORE2_UP_RATIO		(1 << 4)
 #define PWR_CTRL2_CORE1_UP_RATIO		(1 << 0)
 
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR					(CLK_MOUT_VPLLSRC + 1)
+
 /* list of PLLs to be registered */
 enum exynos5250_plls {
 	apll, mpll, cpll, epll, vpll, gpll, bpll,
@@ -797,7 +800,7 @@ static void __init exynos5250_clk_init(struct device_node *np)
 		panic("%s: unable to determine soc\n", __func__);
 	}
 
-	ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
+	ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
 	hws = ctx->clk_data.hws;
 
 	samsung_clk_of_register_fixed_ext(ctx, exynos5250_fixed_rate_ext_clks,
-- 
2.34.1

RE: [PATCH 03/11] clk: samsung: exynos5250: do not define number of clocks in bindings

[Alim Akhtar]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Tuesday, August 8, 2023 1:58 PM
> To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Sylwester
> Nawrocki <s.nawrocki@samsung.com>; Tomasz Figa
> <tomasz.figa@gmail.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim
> Akhtar <alim.akhtar@samsung.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob
> Herring <robh+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org
> Subject: [PATCH 03/11] clk: samsung: exynos5250: do not define number of
> clocks in bindings
> 
> Number of clocks supported by Linux drivers might vary - sometimes we add
> new clocks, not exposed previously.  Therefore this number of clocks
should
> not be in the bindings, because otherwise we should not change it.
> 
> Define number of clocks per each clock controller inside the driver
directly.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

>  drivers/clk/samsung/clk-exynos5250.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5250.c
b/drivers/clk/samsung/clk-
> exynos5250.c
> index 92fb09922f28..8ebe6155d8b7 100644
> --- a/drivers/clk/samsung/clk-exynos5250.c
> +++ b/drivers/clk/samsung/clk-exynos5250.c
> @@ -100,6 +100,9 @@
>  #define PWR_CTRL2_CORE2_UP_RATIO		(1 << 4)
>  #define PWR_CTRL2_CORE1_UP_RATIO		(1 << 0)
> 
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define CLKS_NR
> 	(CLK_MOUT_VPLLSRC + 1)
> +
>  /* list of PLLs to be registered */
>  enum exynos5250_plls {
>  	apll, mpll, cpll, epll, vpll, gpll, bpll, @@ -797,7 +800,7 @@ static
void
> __init exynos5250_clk_init(struct device_node *np)
>  		panic("%s: unable to determine soc\n", __func__);
>  	}
> 
> -	ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
> +	ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
>  	hws = ctx->clk_data.hws;
> 
>  	samsung_clk_of_register_fixed_ext(ctx,
> exynos5250_fixed_rate_ext_clks,
> --
> 2.34.1

[PATCH 04/11] clk: samsung: exynos5260: do not define number of clocks in bindings

[Krzysztof Kozlowski]

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore this number of clocks
should not be in the bindings, because otherwise we should not change
it.

Define number of clocks per each clock controller inside the driver
directly.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 drivers/clk/samsung/clk-exynos5260.c | 41 +++++++++++++++++++---------
 1 file changed, 28 insertions(+), 13 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5260.c b/drivers/clk/samsung/clk-exynos5260.c
index e05d7323669a..16da6ef5ca0c 100644
--- a/drivers/clk/samsung/clk-exynos5260.c
+++ b/drivers/clk/samsung/clk-exynos5260.c
@@ -15,6 +15,21 @@
 
 #include <dt-bindings/clock/exynos5260-clk.h>
 
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR_TOP			(PHYCLK_USBDRD30_UDRD30_PHYCLOCK + 1)
+#define CLKS_NR_EGL			(EGL_DOUT_EGL1 + 1)
+#define CLKS_NR_KFC			(KFC_DOUT_KFC1 + 1)
+#define CLKS_NR_MIF			(MIF_SCLK_LPDDR3PHY_WRAP_U0 + 1)
+#define CLKS_NR_G3D			(G3D_CLK_G3D + 1)
+#define CLKS_NR_AUD			(AUD_SCLK_I2S + 1)
+#define CLKS_NR_MFC			(MFC_CLK_SMMU2_MFCM0 + 1)
+#define CLKS_NR_GSCL			(GSCL_SCLK_CSIS0_WRAP + 1)
+#define CLKS_NR_FSYS			(FSYS_PHYCLK_USBHOST20 + 1)
+#define CLKS_NR_PERI			(PERI_SCLK_PCM1 + 1)
+#define CLKS_NR_DISP			(DISP_MOUT_HDMI_PHY_PIXEL_USER + 1)
+#define CLKS_NR_G2D			(G2D_CLK_SMMU3_G2D + 1)
+#define CLKS_NR_ISP			(ISP_SCLK_UART_EXT + 1)
+
 /*
  * Applicable for all 2550 Type PLLS for Exynos5260, listed below
  * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
@@ -135,7 +150,7 @@ static const struct samsung_cmu_info aud_cmu __initconst = {
 	.nr_div_clks	= ARRAY_SIZE(aud_div_clks),
 	.gate_clks	= aud_gate_clks,
 	.nr_gate_clks	= ARRAY_SIZE(aud_gate_clks),
-	.nr_clk_ids	= AUD_NR_CLK,
+	.nr_clk_ids	= CLKS_NR_AUD,
 	.clk_regs	= aud_clk_regs,
 	.nr_clk_regs	= ARRAY_SIZE(aud_clk_regs),
 };
@@ -325,7 +340,7 @@ static const struct samsung_cmu_info disp_cmu __initconst = {
 	.nr_div_clks	= ARRAY_SIZE(disp_div_clks),
 	.gate_clks	= disp_gate_clks,
 	.nr_gate_clks	= ARRAY_SIZE(disp_gate_clks),
-	.nr_clk_ids	= DISP_NR_CLK,
+	.nr_clk_ids	= CLKS_NR_DISP,
 	.clk_regs	= disp_clk_regs,
 	.nr_clk_regs	= ARRAY_SIZE(disp_clk_regs),
 };
@@ -389,7 +404,7 @@ static const struct samsung_cmu_info egl_cmu __initconst = {
 	.nr_mux_clks	= ARRAY_SIZE(egl_mux_clks),
 	.div_clks	= egl_div_clks,
 	.nr_div_clks	= ARRAY_SIZE(egl_div_clks),
-	.nr_clk_ids	= EGL_NR_CLK,
+	.nr_clk_ids	= CLKS_NR_EGL,
 	.clk_regs	= egl_clk_regs,
 	.nr_clk_regs	= ARRAY_SIZE(egl_clk_regs),
 };
@@ -489,7 +504,7 @@ static const struct samsung_cmu_info fsys_cmu __initconst = {
 	.nr_mux_clks	= ARRAY_SIZE(fsys_mux_clks),
 	.gate_clks	= fsys_gate_clks,
 	.nr_gate_clks	= ARRAY_SIZE(fsys_gate_clks),
-	.nr_clk_ids	= FSYS_NR_CLK,
+	.nr_clk_ids	= CLKS_NR_FSYS,
 	.clk_regs	= fsys_clk_regs,
 	.nr_clk_regs	= ARRAY_SIZE(fsys_clk_regs),
 };
@@ -580,7 +595,7 @@ static const struct samsung_cmu_info g2d_cmu __initconst = {
 	.nr_div_clks	= ARRAY_SIZE(g2d_div_clks),
 	.gate_clks	= g2d_gate_clks,
 	.nr_gate_clks	= ARRAY_SIZE(g2d_gate_clks),
-	.nr_clk_ids	= G2D_NR_CLK,
+	.nr_clk_ids	= CLKS_NR_G2D,
 	.clk_regs	= g2d_clk_regs,
 	.nr_clk_regs	= ARRAY_SIZE(g2d_clk_regs),
 };
@@ -643,7 +658,7 @@ static const struct samsung_cmu_info g3d_cmu __initconst = {
 	.nr_div_clks	= ARRAY_SIZE(g3d_div_clks),
 	.gate_clks	= g3d_gate_clks,
 	.nr_gate_clks	= ARRAY_SIZE(g3d_gate_clks),
-	.nr_clk_ids	= G3D_NR_CLK,
+	.nr_clk_ids	= CLKS_NR_G3D,
 	.clk_regs	= g3d_clk_regs,
 	.nr_clk_regs	= ARRAY_SIZE(g3d_clk_regs),
 };
@@ -776,7 +791,7 @@ static const struct samsung_cmu_info gscl_cmu __initconst = {
 	.nr_div_clks	= ARRAY_SIZE(gscl_div_clks),
 	.gate_clks	= gscl_gate_clks,
 	.nr_gate_clks	= ARRAY_SIZE(gscl_gate_clks),
-	.nr_clk_ids	= GSCL_NR_CLK,
+	.nr_clk_ids	= CLKS_NR_GSCL,
 	.clk_regs	= gscl_clk_regs,
 	.nr_clk_regs	= ARRAY_SIZE(gscl_clk_regs),
 };
@@ -895,7 +910,7 @@ static const struct samsung_cmu_info isp_cmu __initconst = {
 	.nr_div_clks	= ARRAY_SIZE(isp_div_clks),
 	.gate_clks	= isp_gate_clks,
 	.nr_gate_clks	= ARRAY_SIZE(isp_gate_clks),
-	.nr_clk_ids	= ISP_NR_CLK,
+	.nr_clk_ids	= CLKS_NR_ISP,
 	.clk_regs	= isp_clk_regs,
 	.nr_clk_regs	= ARRAY_SIZE(isp_clk_regs),
 };
@@ -959,7 +974,7 @@ static const struct samsung_cmu_info kfc_cmu __initconst = {
 	.nr_mux_clks	= ARRAY_SIZE(kfc_mux_clks),
 	.div_clks	= kfc_div_clks,
 	.nr_div_clks	= ARRAY_SIZE(kfc_div_clks),
-	.nr_clk_ids	= KFC_NR_CLK,
+	.nr_clk_ids	= CLKS_NR_KFC,
 	.clk_regs	= kfc_clk_regs,
 	.nr_clk_regs	= ARRAY_SIZE(kfc_clk_regs),
 };
@@ -1015,7 +1030,7 @@ static const struct samsung_cmu_info mfc_cmu __initconst = {
 	.nr_div_clks	= ARRAY_SIZE(mfc_div_clks),
 	.gate_clks	= mfc_gate_clks,
 	.nr_gate_clks	= ARRAY_SIZE(mfc_gate_clks),
-	.nr_clk_ids	= MFC_NR_CLK,
+	.nr_clk_ids	= CLKS_NR_MFC,
 	.clk_regs	= mfc_clk_regs,
 	.nr_clk_regs	= ARRAY_SIZE(mfc_clk_regs),
 };
@@ -1164,7 +1179,7 @@ static const struct samsung_cmu_info mif_cmu __initconst = {
 	.nr_div_clks	= ARRAY_SIZE(mif_div_clks),
 	.gate_clks	= mif_gate_clks,
 	.nr_gate_clks	= ARRAY_SIZE(mif_gate_clks),
-	.nr_clk_ids	= MIF_NR_CLK,
+	.nr_clk_ids	= CLKS_NR_MIF,
 	.clk_regs	= mif_clk_regs,
 	.nr_clk_regs	= ARRAY_SIZE(mif_clk_regs),
 };
@@ -1370,7 +1385,7 @@ static const struct samsung_cmu_info peri_cmu __initconst = {
 	.nr_div_clks	= ARRAY_SIZE(peri_div_clks),
 	.gate_clks	= peri_gate_clks,
 	.nr_gate_clks	= ARRAY_SIZE(peri_gate_clks),
-	.nr_clk_ids	= PERI_NR_CLK,
+	.nr_clk_ids	= CLKS_NR_PERI,
 	.clk_regs	= peri_clk_regs,
 	.nr_clk_regs	= ARRAY_SIZE(peri_clk_regs),
 };
@@ -1826,7 +1841,7 @@ static const struct samsung_cmu_info top_cmu __initconst = {
 	.nr_gate_clks	= ARRAY_SIZE(top_gate_clks),
 	.fixed_clks	= fixed_rate_clks,
 	.nr_fixed_clks	= ARRAY_SIZE(fixed_rate_clks),
-	.nr_clk_ids	= TOP_NR_CLK,
+	.nr_clk_ids	= CLKS_NR_TOP,
 	.clk_regs	= top_clk_regs,
 	.nr_clk_regs	= ARRAY_SIZE(top_clk_regs),
 };
-- 
2.34.1

RE: [PATCH 04/11] clk: samsung: exynos5260: do not define number of clocks in bindings

[Alim Akhtar]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Tuesday, August 8, 2023 1:58 PM
> To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Sylwester
> Nawrocki <s.nawrocki@samsung.com>; Tomasz Figa
> <tomasz.figa@gmail.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim
> Akhtar <alim.akhtar@samsung.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob
> Herring <robh+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org
> Subject: [PATCH 04/11] clk: samsung: exynos5260: do not define number of
> clocks in bindings
> 
> Number of clocks supported by Linux drivers might vary - sometimes we add
> new clocks, not exposed previously.  Therefore this number of clocks
should
> not be in the bindings, because otherwise we should not change it.
> 
> Define number of clocks per each clock controller inside the driver
directly.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

>  drivers/clk/samsung/clk-exynos5260.c | 41 +++++++++++++++++++---------
>  1 file changed, 28 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5260.c
b/drivers/clk/samsung/clk-
> exynos5260.c
> index e05d7323669a..16da6ef5ca0c 100644
> --- a/drivers/clk/samsung/clk-exynos5260.c
> +++ b/drivers/clk/samsung/clk-exynos5260.c
> @@ -15,6 +15,21 @@
> 
>  #include <dt-bindings/clock/exynos5260-clk.h>
> 
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define CLKS_NR_TOP
> 	(PHYCLK_USBDRD30_UDRD30_PHYCLOCK + 1)
> +#define CLKS_NR_EGL			(EGL_DOUT_EGL1 + 1)
> +#define CLKS_NR_KFC			(KFC_DOUT_KFC1 + 1)
> +#define CLKS_NR_MIF
> 	(MIF_SCLK_LPDDR3PHY_WRAP_U0 + 1)
> +#define CLKS_NR_G3D			(G3D_CLK_G3D + 1)
> +#define CLKS_NR_AUD			(AUD_SCLK_I2S + 1)
> +#define CLKS_NR_MFC			(MFC_CLK_SMMU2_MFCM0
> + 1)
> +#define CLKS_NR_GSCL			(GSCL_SCLK_CSIS0_WRAP +
> 1)
> +#define CLKS_NR_FSYS			(FSYS_PHYCLK_USBHOST20 +
> 1)
> +#define CLKS_NR_PERI			(PERI_SCLK_PCM1 + 1)
> +#define CLKS_NR_DISP
> 	(DISP_MOUT_HDMI_PHY_PIXEL_USER + 1)
> +#define CLKS_NR_G2D			(G2D_CLK_SMMU3_G2D + 1)
> +#define CLKS_NR_ISP			(ISP_SCLK_UART_EXT + 1)
> +
>  /*
>   * Applicable for all 2550 Type PLLS for Exynos5260, listed below
>   * DISP_PLL, EGL_PLL, KFC_PLL, MEM_PLL, BUS_PLL, MEDIA_PLL, G3D_PLL.
> @@ -135,7 +150,7 @@ static const struct samsung_cmu_info aud_cmu
> __initconst = {
>  	.nr_div_clks	= ARRAY_SIZE(aud_div_clks),
>  	.gate_clks	= aud_gate_clks,
>  	.nr_gate_clks	= ARRAY_SIZE(aud_gate_clks),
> -	.nr_clk_ids	= AUD_NR_CLK,
> +	.nr_clk_ids	= CLKS_NR_AUD,
>  	.clk_regs	= aud_clk_regs,
>  	.nr_clk_regs	= ARRAY_SIZE(aud_clk_regs),
>  };
> @@ -325,7 +340,7 @@ static const struct samsung_cmu_info disp_cmu
> __initconst = {
>  	.nr_div_clks	= ARRAY_SIZE(disp_div_clks),
>  	.gate_clks	= disp_gate_clks,
>  	.nr_gate_clks	= ARRAY_SIZE(disp_gate_clks),
> -	.nr_clk_ids	= DISP_NR_CLK,
> +	.nr_clk_ids	= CLKS_NR_DISP,
>  	.clk_regs	= disp_clk_regs,
>  	.nr_clk_regs	= ARRAY_SIZE(disp_clk_regs),
>  };
> @@ -389,7 +404,7 @@ static const struct samsung_cmu_info egl_cmu
> __initconst = {
>  	.nr_mux_clks	= ARRAY_SIZE(egl_mux_clks),
>  	.div_clks	= egl_div_clks,
>  	.nr_div_clks	= ARRAY_SIZE(egl_div_clks),
> -	.nr_clk_ids	= EGL_NR_CLK,
> +	.nr_clk_ids	= CLKS_NR_EGL,
>  	.clk_regs	= egl_clk_regs,
>  	.nr_clk_regs	= ARRAY_SIZE(egl_clk_regs),
>  };
> @@ -489,7 +504,7 @@ static const struct samsung_cmu_info fsys_cmu
> __initconst = {
>  	.nr_mux_clks	= ARRAY_SIZE(fsys_mux_clks),
>  	.gate_clks	= fsys_gate_clks,
>  	.nr_gate_clks	= ARRAY_SIZE(fsys_gate_clks),
> -	.nr_clk_ids	= FSYS_NR_CLK,
> +	.nr_clk_ids	= CLKS_NR_FSYS,
>  	.clk_regs	= fsys_clk_regs,
>  	.nr_clk_regs	= ARRAY_SIZE(fsys_clk_regs),
>  };
> @@ -580,7 +595,7 @@ static const struct samsung_cmu_info g2d_cmu
> __initconst = {
>  	.nr_div_clks	= ARRAY_SIZE(g2d_div_clks),
>  	.gate_clks	= g2d_gate_clks,
>  	.nr_gate_clks	= ARRAY_SIZE(g2d_gate_clks),
> -	.nr_clk_ids	= G2D_NR_CLK,
> +	.nr_clk_ids	= CLKS_NR_G2D,
>  	.clk_regs	= g2d_clk_regs,
>  	.nr_clk_regs	= ARRAY_SIZE(g2d_clk_regs),
>  };
> @@ -643,7 +658,7 @@ static const struct samsung_cmu_info g3d_cmu
> __initconst = {
>  	.nr_div_clks	= ARRAY_SIZE(g3d_div_clks),
>  	.gate_clks	= g3d_gate_clks,
>  	.nr_gate_clks	= ARRAY_SIZE(g3d_gate_clks),
> -	.nr_clk_ids	= G3D_NR_CLK,
> +	.nr_clk_ids	= CLKS_NR_G3D,
>  	.clk_regs	= g3d_clk_regs,
>  	.nr_clk_regs	= ARRAY_SIZE(g3d_clk_regs),
>  };
> @@ -776,7 +791,7 @@ static const struct samsung_cmu_info gscl_cmu
> __initconst = {
>  	.nr_div_clks	= ARRAY_SIZE(gscl_div_clks),
>  	.gate_clks	= gscl_gate_clks,
>  	.nr_gate_clks	= ARRAY_SIZE(gscl_gate_clks),
> -	.nr_clk_ids	= GSCL_NR_CLK,
> +	.nr_clk_ids	= CLKS_NR_GSCL,
>  	.clk_regs	= gscl_clk_regs,
>  	.nr_clk_regs	= ARRAY_SIZE(gscl_clk_regs),
>  };
> @@ -895,7 +910,7 @@ static const struct samsung_cmu_info isp_cmu
> __initconst = {
>  	.nr_div_clks	= ARRAY_SIZE(isp_div_clks),
>  	.gate_clks	= isp_gate_clks,
>  	.nr_gate_clks	= ARRAY_SIZE(isp_gate_clks),
> -	.nr_clk_ids	= ISP_NR_CLK,
> +	.nr_clk_ids	= CLKS_NR_ISP,
>  	.clk_regs	= isp_clk_regs,
>  	.nr_clk_regs	= ARRAY_SIZE(isp_clk_regs),
>  };
> @@ -959,7 +974,7 @@ static const struct samsung_cmu_info kfc_cmu
> __initconst = {
>  	.nr_mux_clks	= ARRAY_SIZE(kfc_mux_clks),
>  	.div_clks	= kfc_div_clks,
>  	.nr_div_clks	= ARRAY_SIZE(kfc_div_clks),
> -	.nr_clk_ids	= KFC_NR_CLK,
> +	.nr_clk_ids	= CLKS_NR_KFC,
>  	.clk_regs	= kfc_clk_regs,
>  	.nr_clk_regs	= ARRAY_SIZE(kfc_clk_regs),
>  };
> @@ -1015,7 +1030,7 @@ static const struct samsung_cmu_info mfc_cmu
> __initconst = {
>  	.nr_div_clks	= ARRAY_SIZE(mfc_div_clks),
>  	.gate_clks	= mfc_gate_clks,
>  	.nr_gate_clks	= ARRAY_SIZE(mfc_gate_clks),
> -	.nr_clk_ids	= MFC_NR_CLK,
> +	.nr_clk_ids	= CLKS_NR_MFC,
>  	.clk_regs	= mfc_clk_regs,
>  	.nr_clk_regs	= ARRAY_SIZE(mfc_clk_regs),
>  };
> @@ -1164,7 +1179,7 @@ static const struct samsung_cmu_info mif_cmu
> __initconst = {
>  	.nr_div_clks	= ARRAY_SIZE(mif_div_clks),
>  	.gate_clks	= mif_gate_clks,
>  	.nr_gate_clks	= ARRAY_SIZE(mif_gate_clks),
> -	.nr_clk_ids	= MIF_NR_CLK,
> +	.nr_clk_ids	= CLKS_NR_MIF,
>  	.clk_regs	= mif_clk_regs,
>  	.nr_clk_regs	= ARRAY_SIZE(mif_clk_regs),
>  };
> @@ -1370,7 +1385,7 @@ static const struct samsung_cmu_info peri_cmu
> __initconst = {
>  	.nr_div_clks	= ARRAY_SIZE(peri_div_clks),
>  	.gate_clks	= peri_gate_clks,
>  	.nr_gate_clks	= ARRAY_SIZE(peri_gate_clks),
> -	.nr_clk_ids	= PERI_NR_CLK,
> +	.nr_clk_ids	= CLKS_NR_PERI,
>  	.clk_regs	= peri_clk_regs,
>  	.nr_clk_regs	= ARRAY_SIZE(peri_clk_regs),
>  };
> @@ -1826,7 +1841,7 @@ static const struct samsung_cmu_info top_cmu
> __initconst = {
>  	.nr_gate_clks	= ARRAY_SIZE(top_gate_clks),
>  	.fixed_clks	= fixed_rate_clks,
>  	.nr_fixed_clks	= ARRAY_SIZE(fixed_rate_clks),
> -	.nr_clk_ids	= TOP_NR_CLK,
> +	.nr_clk_ids	= CLKS_NR_TOP,
>  	.clk_regs	= top_clk_regs,
>  	.nr_clk_regs	= ARRAY_SIZE(top_clk_regs),
>  };
> --
> 2.34.1

[PATCH 05/11] clk: samsung: exynos5410: do not define number of clocks in bindings

[Krzysztof Kozlowski]

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore this number of clocks
should not be in the bindings, because otherwise we should not change
it.

Define number of clocks per each clock controller inside the driver
directly.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 drivers/clk/samsung/clk-exynos5410.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5410.c b/drivers/clk/samsung/clk-exynos5410.c
index d67d67a519a4..2654077211e7 100644
--- a/drivers/clk/samsung/clk-exynos5410.c
+++ b/drivers/clk/samsung/clk-exynos5410.c
@@ -56,6 +56,9 @@
 #define SRC_KFC			0x28200
 #define DIV_KFC0		0x28500
 
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR			512
+
 /* list of PLLs */
 enum exynos5410_plls {
 	apll, cpll, epll, mpll,
@@ -260,7 +263,7 @@ static const struct samsung_cmu_info cmu __initconst = {
 	.nr_div_clks	= ARRAY_SIZE(exynos5410_div_clks),
 	.gate_clks	= exynos5410_gate_clks,
 	.nr_gate_clks	= ARRAY_SIZE(exynos5410_gate_clks),
-	.nr_clk_ids	= CLK_NR_CLKS,
+	.nr_clk_ids	= CLKS_NR,
 };
 
 /* register exynos5410 clocks */
-- 
2.34.1

RE: [PATCH 05/11] clk: samsung: exynos5410: do not define number of clocks in bindings

[Alim Akhtar]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Tuesday, August 8, 2023 1:58 PM
> To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Sylwester
> Nawrocki <s.nawrocki@samsung.com>; Tomasz Figa
> <tomasz.figa@gmail.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim
> Akhtar <alim.akhtar@samsung.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob
> Herring <robh+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org
> Subject: [PATCH 05/11] clk: samsung: exynos5410: do not define number of
> clocks in bindings
> 
> Number of clocks supported by Linux drivers might vary - sometimes we add
> new clocks, not exposed previously.  Therefore this number of clocks
should
> not be in the bindings, because otherwise we should not change it.
> 
> Define number of clocks per each clock controller inside the driver
directly.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

>  drivers/clk/samsung/clk-exynos5410.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5410.c
b/drivers/clk/samsung/clk-
> exynos5410.c
> index d67d67a519a4..2654077211e7 100644
> --- a/drivers/clk/samsung/clk-exynos5410.c
> +++ b/drivers/clk/samsung/clk-exynos5410.c
> @@ -56,6 +56,9 @@
>  #define SRC_KFC			0x28200
>  #define DIV_KFC0		0x28500
> 
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define CLKS_NR			512
> +
>  /* list of PLLs */
>  enum exynos5410_plls {
>  	apll, cpll, epll, mpll,
> @@ -260,7 +263,7 @@ static const struct samsung_cmu_info cmu __initconst
> = {
>  	.nr_div_clks	= ARRAY_SIZE(exynos5410_div_clks),
>  	.gate_clks	= exynos5410_gate_clks,
>  	.nr_gate_clks	= ARRAY_SIZE(exynos5410_gate_clks),
> -	.nr_clk_ids	= CLK_NR_CLKS,
> +	.nr_clk_ids	= CLKS_NR,
>  };
> 
>  /* register exynos5410 clocks */
> --
> 2.34.1

[PATCH 06/11] clk: samsung: exynos5420: do not define number of clocks in bindings

[Krzysztof Kozlowski]

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore this number of clocks
should not be in the bindings, because otherwise we should not change
it.

Define number of clocks per each clock controller inside the driver
directly.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 drivers/clk/samsung/clk-exynos5420.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 1e0cbf762408..199843f12ae5 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -139,6 +139,9 @@
 #define SRC_KFC			0x28200
 #define DIV_KFC0		0x28500
 
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR			(CLK_DOUT_PCLK_DREX1 + 1)
+
 /* Exynos5x SoC type */
 enum exynos5x_soc {
 	EXYNOS5420,
@@ -1587,7 +1590,7 @@ static void __init exynos5x_clk_init(struct device_node *np,
 
 	exynos5x_soc = soc;
 
-	ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
+	ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
 	hws = ctx->clk_data.hws;
 
 	samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
-- 
2.34.1

RE: [PATCH 06/11] clk: samsung: exynos5420: do not define number of clocks in bindings

[Alim Akhtar]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Tuesday, August 8, 2023 1:58 PM
> To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Sylwester
> Nawrocki <s.nawrocki@samsung.com>; Tomasz Figa
> <tomasz.figa@gmail.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim
> Akhtar <alim.akhtar@samsung.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob
> Herring <robh+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org
> Subject: [PATCH 06/11] clk: samsung: exynos5420: do not define number of
> clocks in bindings
> 
> Number of clocks supported by Linux drivers might vary - sometimes we add
> new clocks, not exposed previously.  Therefore this number of clocks
should
> not be in the bindings, because otherwise we should not change it.
> 
> Define number of clocks per each clock controller inside the driver
directly.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>


>  drivers/clk/samsung/clk-exynos5420.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5420.c
b/drivers/clk/samsung/clk-
> exynos5420.c
> index 1e0cbf762408..199843f12ae5 100644
> --- a/drivers/clk/samsung/clk-exynos5420.c
> +++ b/drivers/clk/samsung/clk-exynos5420.c
> @@ -139,6 +139,9 @@
>  #define SRC_KFC			0x28200
>  #define DIV_KFC0		0x28500
> 
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define CLKS_NR			(CLK_DOUT_PCLK_DREX1 + 1)
> +
>  /* Exynos5x SoC type */
>  enum exynos5x_soc {
>  	EXYNOS5420,
> @@ -1587,7 +1590,7 @@ static void __init exynos5x_clk_init(struct
> device_node *np,
> 
>  	exynos5x_soc = soc;
> 
> -	ctx = samsung_clk_init(NULL, reg_base, CLK_NR_CLKS);
> +	ctx = samsung_clk_init(NULL, reg_base, CLKS_NR);
>  	hws = ctx->clk_data.hws;
> 
>  	samsung_clk_of_register_fixed_ext(ctx,
> exynos5x_fixed_rate_ext_clks,
> --
> 2.34.1

[PATCH 07/11] clk: samsung: exynos5433: do not define number of clocks in bindings

[Krzysztof Kozlowski]

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore this number of clocks
should not be in the bindings, because otherwise we should not change
it.

Define number of clocks per each clock controller inside the driver
directly.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 drivers/clk/samsung/clk-exynos5433.c | 65 +++++++++++++++++++---------
 1 file changed, 44 insertions(+), 21 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos5433.c b/drivers/clk/samsung/clk-exynos5433.c
index ed43233649ae..6bfc5d0cd924 100644
--- a/drivers/clk/samsung/clk-exynos5433.c
+++ b/drivers/clk/samsung/clk-exynos5433.c
@@ -21,6 +21,29 @@
 #include "clk-exynos-arm64.h"
 #include "clk-pll.h"
 
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR_TOP			(CLK_SCLK_HDMI_SPDIF_DISP + 1)
+#define CLKS_NR_CPIF			(CLK_SCLK_UFS_MPHY + 1)
+#define CLKS_NR_MIF			(CLK_SCLK_BUS_PLL_ATLAS + 1)
+#define CLKS_NR_PERIC			(CLK_DIV_SCLK_SC_IN + 1)
+#define CLKS_NR_PERIS			(CLK_SCLK_OTP_CON + 1)
+#define CLKS_NR_FSYS			(CLK_PCIE + 1)
+#define CLKS_NR_G2D			(CLK_PCLK_SMMU_G2D + 1)
+#define CLKS_NR_DISP			(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY + 1)
+#define CLKS_NR_AUD			(CLK_SCLK_AUD_I2S + 1)
+#define CLKS_NR_BUSX			(CLK_ACLK_BUS2RTND_400 + 1)
+#define CLKS_NR_G3D			(CLK_SCLK_HPM_G3D + 1)
+#define CLKS_NR_GSCL			(CLK_PCLK_SMMU_GSCL2 + 1)
+#define CLKS_NR_APOLLO			(CLK_SCLK_APOLLO + 1)
+#define CLKS_NR_ATLAS			(CLK_SCLK_ATLAS + 1)
+#define CLKS_NR_MSCL			(CLK_SCLK_JPEG + 1)
+#define CLKS_NR_MFC			(CLK_PCLK_SMMU_MFC_0 + 1)
+#define CLKS_NR_HEVC			(CLK_PCLK_SMMU_HEVC_0 + 1)
+#define CLKS_NR_ISP			(CLK_SCLK_PIXELASYNCM_ISPC + 1)
+#define CLKS_NR_CAM0			(CLK_SCLK_PIXELASYNCS_LITE_C_INIT + 1)
+#define CLKS_NR_CAM1			(CLK_SCLK_ISP_CA5 + 1)
+#define CLKS_NR_IMEM			(CLK_PCLK_SLIMSSS + 1)
+
 /*
  * Register offset definitions for CMU_TOP
  */
@@ -798,7 +821,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
 	.nr_fixed_clks		= ARRAY_SIZE(top_fixed_clks),
 	.fixed_factor_clks	= top_fixed_factor_clks,
 	.nr_fixed_factor_clks	= ARRAY_SIZE(top_fixed_factor_clks),
-	.nr_clk_ids		= TOP_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_TOP,
 	.clk_regs		= top_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(top_clk_regs),
 	.suspend_regs		= top_suspend_regs,
@@ -877,7 +900,7 @@ static const struct samsung_cmu_info cpif_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(cpif_div_clks),
 	.gate_clks		= cpif_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(cpif_gate_clks),
-	.nr_clk_ids		= CPIF_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_CPIF,
 	.clk_regs		= cpif_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(cpif_clk_regs),
 	.suspend_regs		= cpif_suspend_regs,
@@ -1531,7 +1554,7 @@ static const struct samsung_cmu_info mif_cmu_info __initconst = {
 	.nr_gate_clks		= ARRAY_SIZE(mif_gate_clks),
 	.fixed_factor_clks	= mif_fixed_factor_clks,
 	.nr_fixed_factor_clks	= ARRAY_SIZE(mif_fixed_factor_clks),
-	.nr_clk_ids		= MIF_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_MIF,
 	.clk_regs		= mif_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(mif_clk_regs),
 };
@@ -1730,7 +1753,7 @@ static const struct samsung_cmu_info peric_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(peric_div_clks),
 	.gate_clks		= peric_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(peric_gate_clks),
-	.nr_clk_ids		= PERIC_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_PERIC,
 	.clk_regs		= peric_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(peric_clk_regs),
 	.suspend_regs		= peric_suspend_regs,
@@ -1924,7 +1947,7 @@ static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
 static const struct samsung_cmu_info peris_cmu_info __initconst = {
 	.gate_clks		= peris_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(peris_gate_clks),
-	.nr_clk_ids		= PERIS_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_PERIS,
 	.clk_regs		= peris_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(peris_clk_regs),
 };
@@ -2336,7 +2359,7 @@ static const struct samsung_cmu_info fsys_cmu_info __initconst = {
 	.nr_gate_clks		= ARRAY_SIZE(fsys_gate_clks),
 	.fixed_clks		= fsys_fixed_clks,
 	.nr_fixed_clks		= ARRAY_SIZE(fsys_fixed_clks),
-	.nr_clk_ids		= FSYS_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_FSYS,
 	.clk_regs		= fsys_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(fsys_clk_regs),
 	.suspend_regs		= fsys_suspend_regs,
@@ -2459,7 +2482,7 @@ static const struct samsung_cmu_info g2d_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(g2d_div_clks),
 	.gate_clks		= g2d_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(g2d_gate_clks),
-	.nr_clk_ids		= G2D_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_G2D,
 	.clk_regs		= g2d_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(g2d_clk_regs),
 	.suspend_regs		= g2d_suspend_regs,
@@ -2887,7 +2910,7 @@ static const struct samsung_cmu_info disp_cmu_info __initconst = {
 	.nr_fixed_clks		= ARRAY_SIZE(disp_fixed_clks),
 	.fixed_factor_clks	= disp_fixed_factor_clks,
 	.nr_fixed_factor_clks	= ARRAY_SIZE(disp_fixed_factor_clks),
-	.nr_clk_ids		= DISP_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_DISP,
 	.clk_regs		= disp_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(disp_clk_regs),
 	.suspend_regs		= disp_suspend_regs,
@@ -3057,7 +3080,7 @@ static const struct samsung_cmu_info aud_cmu_info __initconst = {
 	.nr_gate_clks		= ARRAY_SIZE(aud_gate_clks),
 	.fixed_clks		= aud_fixed_clks,
 	.nr_fixed_clks		= ARRAY_SIZE(aud_fixed_clks),
-	.nr_clk_ids		= AUD_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_AUD,
 	.clk_regs		= aud_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(aud_clk_regs),
 	.suspend_regs		= aud_suspend_regs,
@@ -3189,7 +3212,7 @@ static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(bus##id##_div_clks),	\
 	.gate_clks		= bus##id##_gate_clks,			\
 	.nr_gate_clks		= ARRAY_SIZE(bus##id##_gate_clks),	\
-	.nr_clk_ids		= BUSx_NR_CLK
+	.nr_clk_ids		= CLKS_NR_BUSX
 
 static const struct samsung_cmu_info bus0_cmu_info __initconst = {
 	CMU_BUS_INFO_CLKS(0),
@@ -3340,7 +3363,7 @@ static const struct samsung_cmu_info g3d_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(g3d_div_clks),
 	.gate_clks		= g3d_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(g3d_gate_clks),
-	.nr_clk_ids		= G3D_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_G3D,
 	.clk_regs		= g3d_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(g3d_clk_regs),
 	.suspend_regs		= g3d_suspend_regs,
@@ -3483,7 +3506,7 @@ static const struct samsung_cmu_info gscl_cmu_info __initconst = {
 	.nr_mux_clks		= ARRAY_SIZE(gscl_mux_clks),
 	.gate_clks		= gscl_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(gscl_gate_clks),
-	.nr_clk_ids		= GSCL_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_GSCL,
 	.clk_regs		= gscl_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(gscl_clk_regs),
 	.suspend_regs		= gscl_suspend_regs,
@@ -3693,7 +3716,7 @@ static const struct samsung_cmu_info apollo_cmu_info __initconst = {
 	.nr_gate_clks	= ARRAY_SIZE(apollo_gate_clks),
 	.cpu_clks	= apollo_cpu_clks,
 	.nr_cpu_clks	= ARRAY_SIZE(apollo_cpu_clks),
-	.nr_clk_ids	= APOLLO_NR_CLK,
+	.nr_clk_ids	= CLKS_NR_APOLLO,
 	.clk_regs	= apollo_clk_regs,
 	.nr_clk_regs	= ARRAY_SIZE(apollo_clk_regs),
 };
@@ -3938,7 +3961,7 @@ static const struct samsung_cmu_info atlas_cmu_info __initconst = {
 	.nr_gate_clks	= ARRAY_SIZE(atlas_gate_clks),
 	.cpu_clks	= atlas_cpu_clks,
 	.nr_cpu_clks	= ARRAY_SIZE(atlas_cpu_clks),
-	.nr_clk_ids	= ATLAS_NR_CLK,
+	.nr_clk_ids	= CLKS_NR_ATLAS,
 	.clk_regs	= atlas_clk_regs,
 	.nr_clk_regs	= ARRAY_SIZE(atlas_clk_regs),
 };
@@ -4112,7 +4135,7 @@ static const struct samsung_cmu_info mscl_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(mscl_div_clks),
 	.gate_clks		= mscl_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(mscl_gate_clks),
-	.nr_clk_ids		= MSCL_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_MSCL,
 	.clk_regs		= mscl_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(mscl_clk_regs),
 	.suspend_regs		= mscl_suspend_regs,
@@ -4220,7 +4243,7 @@ static const struct samsung_cmu_info mfc_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(mfc_div_clks),
 	.gate_clks		= mfc_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(mfc_gate_clks),
-	.nr_clk_ids		= MFC_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_MFC,
 	.clk_regs		= mfc_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(mfc_clk_regs),
 	.suspend_regs		= mfc_suspend_regs,
@@ -4330,7 +4353,7 @@ static const struct samsung_cmu_info hevc_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(hevc_div_clks),
 	.gate_clks		= hevc_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(hevc_gate_clks),
-	.nr_clk_ids		= HEVC_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_HEVC,
 	.clk_regs		= hevc_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(hevc_clk_regs),
 	.suspend_regs		= hevc_suspend_regs,
@@ -4583,7 +4606,7 @@ static const struct samsung_cmu_info isp_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(isp_div_clks),
 	.gate_clks		= isp_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(isp_gate_clks),
-	.nr_clk_ids		= ISP_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_ISP,
 	.clk_regs		= isp_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(isp_clk_regs),
 	.suspend_regs		= isp_suspend_regs,
@@ -5065,7 +5088,7 @@ static const struct samsung_cmu_info cam0_cmu_info __initconst = {
 	.nr_gate_clks		= ARRAY_SIZE(cam0_gate_clks),
 	.fixed_clks		= cam0_fixed_clks,
 	.nr_fixed_clks		= ARRAY_SIZE(cam0_fixed_clks),
-	.nr_clk_ids		= CAM0_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_CAM0,
 	.clk_regs		= cam0_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(cam0_clk_regs),
 	.suspend_regs		= cam0_suspend_regs,
@@ -5440,7 +5463,7 @@ static const struct samsung_cmu_info cam1_cmu_info __initconst = {
 	.nr_gate_clks		= ARRAY_SIZE(cam1_gate_clks),
 	.fixed_clks		= cam1_fixed_clks,
 	.nr_fixed_clks		= ARRAY_SIZE(cam1_fixed_clks),
-	.nr_clk_ids		= CAM1_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_CAM1,
 	.clk_regs		= cam1_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(cam1_clk_regs),
 	.suspend_regs		= cam1_suspend_regs,
@@ -5472,7 +5495,7 @@ static const struct samsung_gate_clock imem_gate_clks[] __initconst = {
 static const struct samsung_cmu_info imem_cmu_info __initconst = {
 	.gate_clks		= imem_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(imem_gate_clks),
-	.nr_clk_ids		= IMEM_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_IMEM,
 	.clk_regs		= imem_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(imem_clk_regs),
 	.clk_name		= "aclk_imem_200",
-- 
2.34.1

RE: [PATCH 07/11] clk: samsung: exynos5433: do not define number of clocks in bindings

[Alim Akhtar]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Tuesday, August 8, 2023 1:58 PM
> To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Sylwester
> Nawrocki <s.nawrocki@samsung.com>; Tomasz Figa
> <tomasz.figa@gmail.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim
> Akhtar <alim.akhtar@samsung.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob
> Herring <robh+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org
> Subject: [PATCH 07/11] clk: samsung: exynos5433: do not define number of
> clocks in bindings
> 
> Number of clocks supported by Linux drivers might vary - sometimes we add
> new clocks, not exposed previously.  Therefore this number of clocks
should
> not be in the bindings, because otherwise we should not change it.
> 
> Define number of clocks per each clock controller inside the driver
directly.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

>  drivers/clk/samsung/clk-exynos5433.c | 65 +++++++++++++++++++---------
>  1 file changed, 44 insertions(+), 21 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos5433.c
b/drivers/clk/samsung/clk-
> exynos5433.c
> index ed43233649ae..6bfc5d0cd924 100644
> --- a/drivers/clk/samsung/clk-exynos5433.c
> +++ b/drivers/clk/samsung/clk-exynos5433.c
> @@ -21,6 +21,29 @@
>  #include "clk-exynos-arm64.h"
>  #include "clk-pll.h"
> 
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define CLKS_NR_TOP
> 	(CLK_SCLK_HDMI_SPDIF_DISP + 1)
> +#define CLKS_NR_CPIF			(CLK_SCLK_UFS_MPHY + 1)
> +#define CLKS_NR_MIF			(CLK_SCLK_BUS_PLL_ATLAS +
> 1)
> +#define CLKS_NR_PERIC			(CLK_DIV_SCLK_SC_IN + 1)
> +#define CLKS_NR_PERIS			(CLK_SCLK_OTP_CON + 1)
> +#define CLKS_NR_FSYS			(CLK_PCIE + 1)
> +#define CLKS_NR_G2D			(CLK_PCLK_SMMU_G2D + 1)
> +#define CLKS_NR_DISP
> 	(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY + 1)
> +#define CLKS_NR_AUD			(CLK_SCLK_AUD_I2S + 1)
> +#define CLKS_NR_BUSX			(CLK_ACLK_BUS2RTND_400 +
> 1)
> +#define CLKS_NR_G3D			(CLK_SCLK_HPM_G3D + 1)
> +#define CLKS_NR_GSCL			(CLK_PCLK_SMMU_GSCL2 +
> 1)
> +#define CLKS_NR_APOLLO			(CLK_SCLK_APOLLO + 1)
> +#define CLKS_NR_ATLAS			(CLK_SCLK_ATLAS + 1)
> +#define CLKS_NR_MSCL			(CLK_SCLK_JPEG + 1)
> +#define CLKS_NR_MFC			(CLK_PCLK_SMMU_MFC_0 +
> 1)
> +#define CLKS_NR_HEVC			(CLK_PCLK_SMMU_HEVC_0
> + 1)
> +#define CLKS_NR_ISP			(CLK_SCLK_PIXELASYNCM_ISPC + 1)
> +#define CLKS_NR_CAM0
> 	(CLK_SCLK_PIXELASYNCS_LITE_C_INIT + 1)
> +#define CLKS_NR_CAM1			(CLK_SCLK_ISP_CA5 + 1)
> +#define CLKS_NR_IMEM			(CLK_PCLK_SLIMSSS + 1)
> +
>  /*
>   * Register offset definitions for CMU_TOP
>   */
> @@ -798,7 +821,7 @@ static const struct samsung_cmu_info top_cmu_info
> __initconst = {
>  	.nr_fixed_clks		= ARRAY_SIZE(top_fixed_clks),
>  	.fixed_factor_clks	= top_fixed_factor_clks,
>  	.nr_fixed_factor_clks	= ARRAY_SIZE(top_fixed_factor_clks),
> -	.nr_clk_ids		= TOP_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_TOP,
>  	.clk_regs		= top_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(top_clk_regs),
>  	.suspend_regs		= top_suspend_regs,
> @@ -877,7 +900,7 @@ static const struct samsung_cmu_info cpif_cmu_info
> __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(cpif_div_clks),
>  	.gate_clks		= cpif_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(cpif_gate_clks),
> -	.nr_clk_ids		= CPIF_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_CPIF,
>  	.clk_regs		= cpif_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(cpif_clk_regs),
>  	.suspend_regs		= cpif_suspend_regs,
> @@ -1531,7 +1554,7 @@ static const struct samsung_cmu_info
> mif_cmu_info __initconst = {
>  	.nr_gate_clks		= ARRAY_SIZE(mif_gate_clks),
>  	.fixed_factor_clks	= mif_fixed_factor_clks,
>  	.nr_fixed_factor_clks	= ARRAY_SIZE(mif_fixed_factor_clks),
> -	.nr_clk_ids		= MIF_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_MIF,
>  	.clk_regs		= mif_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(mif_clk_regs),
>  };
> @@ -1730,7 +1753,7 @@ static const struct samsung_cmu_info
> peric_cmu_info __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(peric_div_clks),
>  	.gate_clks		= peric_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(peric_gate_clks),
> -	.nr_clk_ids		= PERIC_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_PERIC,
>  	.clk_regs		= peric_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(peric_clk_regs),
>  	.suspend_regs		= peric_suspend_regs,
> @@ -1924,7 +1947,7 @@ static const struct samsung_gate_clock
> peris_gate_clks[] __initconst = {  static const struct samsung_cmu_info
> peris_cmu_info __initconst = {
>  	.gate_clks		= peris_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(peris_gate_clks),
> -	.nr_clk_ids		= PERIS_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_PERIS,
>  	.clk_regs		= peris_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(peris_clk_regs),
>  };
> @@ -2336,7 +2359,7 @@ static const struct samsung_cmu_info
> fsys_cmu_info __initconst = {
>  	.nr_gate_clks		= ARRAY_SIZE(fsys_gate_clks),
>  	.fixed_clks		= fsys_fixed_clks,
>  	.nr_fixed_clks		= ARRAY_SIZE(fsys_fixed_clks),
> -	.nr_clk_ids		= FSYS_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_FSYS,
>  	.clk_regs		= fsys_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(fsys_clk_regs),
>  	.suspend_regs		= fsys_suspend_regs,
> @@ -2459,7 +2482,7 @@ static const struct samsung_cmu_info
> g2d_cmu_info __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(g2d_div_clks),
>  	.gate_clks		= g2d_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(g2d_gate_clks),
> -	.nr_clk_ids		= G2D_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_G2D,
>  	.clk_regs		= g2d_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(g2d_clk_regs),
>  	.suspend_regs		= g2d_suspend_regs,
> @@ -2887,7 +2910,7 @@ static const struct samsung_cmu_info
> disp_cmu_info __initconst = {
>  	.nr_fixed_clks		= ARRAY_SIZE(disp_fixed_clks),
>  	.fixed_factor_clks	= disp_fixed_factor_clks,
>  	.nr_fixed_factor_clks	= ARRAY_SIZE(disp_fixed_factor_clks),
> -	.nr_clk_ids		= DISP_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_DISP,
>  	.clk_regs		= disp_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(disp_clk_regs),
>  	.suspend_regs		= disp_suspend_regs,
> @@ -3057,7 +3080,7 @@ static const struct samsung_cmu_info
> aud_cmu_info __initconst = {
>  	.nr_gate_clks		= ARRAY_SIZE(aud_gate_clks),
>  	.fixed_clks		= aud_fixed_clks,
>  	.nr_fixed_clks		= ARRAY_SIZE(aud_fixed_clks),
> -	.nr_clk_ids		= AUD_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_AUD,
>  	.clk_regs		= aud_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(aud_clk_regs),
>  	.suspend_regs		= aud_suspend_regs,
> @@ -3189,7 +3212,7 @@ static const struct samsung_gate_clock
> bus2_gate_clks[] __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(bus##id##_div_clks),	\
>  	.gate_clks		= bus##id##_gate_clks,
> 	\
>  	.nr_gate_clks		= ARRAY_SIZE(bus##id##_gate_clks),	\
> -	.nr_clk_ids		= BUSx_NR_CLK
> +	.nr_clk_ids		= CLKS_NR_BUSX
> 
>  static const struct samsung_cmu_info bus0_cmu_info __initconst = {
>  	CMU_BUS_INFO_CLKS(0),
> @@ -3340,7 +3363,7 @@ static const struct samsung_cmu_info
> g3d_cmu_info __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(g3d_div_clks),
>  	.gate_clks		= g3d_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(g3d_gate_clks),
> -	.nr_clk_ids		= G3D_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_G3D,
>  	.clk_regs		= g3d_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(g3d_clk_regs),
>  	.suspend_regs		= g3d_suspend_regs,
> @@ -3483,7 +3506,7 @@ static const struct samsung_cmu_info
> gscl_cmu_info __initconst = {
>  	.nr_mux_clks		= ARRAY_SIZE(gscl_mux_clks),
>  	.gate_clks		= gscl_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(gscl_gate_clks),
> -	.nr_clk_ids		= GSCL_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_GSCL,
>  	.clk_regs		= gscl_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(gscl_clk_regs),
>  	.suspend_regs		= gscl_suspend_regs,
> @@ -3693,7 +3716,7 @@ static const struct samsung_cmu_info
> apollo_cmu_info __initconst = {
>  	.nr_gate_clks	= ARRAY_SIZE(apollo_gate_clks),
>  	.cpu_clks	= apollo_cpu_clks,
>  	.nr_cpu_clks	= ARRAY_SIZE(apollo_cpu_clks),
> -	.nr_clk_ids	= APOLLO_NR_CLK,
> +	.nr_clk_ids	= CLKS_NR_APOLLO,
>  	.clk_regs	= apollo_clk_regs,
>  	.nr_clk_regs	= ARRAY_SIZE(apollo_clk_regs),
>  };
> @@ -3938,7 +3961,7 @@ static const struct samsung_cmu_info
> atlas_cmu_info __initconst = {
>  	.nr_gate_clks	= ARRAY_SIZE(atlas_gate_clks),
>  	.cpu_clks	= atlas_cpu_clks,
>  	.nr_cpu_clks	= ARRAY_SIZE(atlas_cpu_clks),
> -	.nr_clk_ids	= ATLAS_NR_CLK,
> +	.nr_clk_ids	= CLKS_NR_ATLAS,
>  	.clk_regs	= atlas_clk_regs,
>  	.nr_clk_regs	= ARRAY_SIZE(atlas_clk_regs),
>  };
> @@ -4112,7 +4135,7 @@ static const struct samsung_cmu_info
> mscl_cmu_info __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(mscl_div_clks),
>  	.gate_clks		= mscl_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(mscl_gate_clks),
> -	.nr_clk_ids		= MSCL_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_MSCL,
>  	.clk_regs		= mscl_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(mscl_clk_regs),
>  	.suspend_regs		= mscl_suspend_regs,
> @@ -4220,7 +4243,7 @@ static const struct samsung_cmu_info
> mfc_cmu_info __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(mfc_div_clks),
>  	.gate_clks		= mfc_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(mfc_gate_clks),
> -	.nr_clk_ids		= MFC_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_MFC,
>  	.clk_regs		= mfc_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(mfc_clk_regs),
>  	.suspend_regs		= mfc_suspend_regs,
> @@ -4330,7 +4353,7 @@ static const struct samsung_cmu_info
> hevc_cmu_info __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(hevc_div_clks),
>  	.gate_clks		= hevc_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(hevc_gate_clks),
> -	.nr_clk_ids		= HEVC_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_HEVC,
>  	.clk_regs		= hevc_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(hevc_clk_regs),
>  	.suspend_regs		= hevc_suspend_regs,
> @@ -4583,7 +4606,7 @@ static const struct samsung_cmu_info isp_cmu_info
> __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(isp_div_clks),
>  	.gate_clks		= isp_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(isp_gate_clks),
> -	.nr_clk_ids		= ISP_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_ISP,
>  	.clk_regs		= isp_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(isp_clk_regs),
>  	.suspend_regs		= isp_suspend_regs,
> @@ -5065,7 +5088,7 @@ static const struct samsung_cmu_info
> cam0_cmu_info __initconst = {
>  	.nr_gate_clks		= ARRAY_SIZE(cam0_gate_clks),
>  	.fixed_clks		= cam0_fixed_clks,
>  	.nr_fixed_clks		= ARRAY_SIZE(cam0_fixed_clks),
> -	.nr_clk_ids		= CAM0_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_CAM0,
>  	.clk_regs		= cam0_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(cam0_clk_regs),
>  	.suspend_regs		= cam0_suspend_regs,
> @@ -5440,7 +5463,7 @@ static const struct samsung_cmu_info
> cam1_cmu_info __initconst = {
>  	.nr_gate_clks		= ARRAY_SIZE(cam1_gate_clks),
>  	.fixed_clks		= cam1_fixed_clks,
>  	.nr_fixed_clks		= ARRAY_SIZE(cam1_fixed_clks),
> -	.nr_clk_ids		= CAM1_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_CAM1,
>  	.clk_regs		= cam1_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(cam1_clk_regs),
>  	.suspend_regs		= cam1_suspend_regs,
> @@ -5472,7 +5495,7 @@ static const struct samsung_gate_clock
> imem_gate_clks[] __initconst = {  static const struct samsung_cmu_info
> imem_cmu_info __initconst = {
>  	.gate_clks		= imem_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(imem_gate_clks),
> -	.nr_clk_ids		= IMEM_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_IMEM,
>  	.clk_regs		= imem_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(imem_clk_regs),
>  	.clk_name		= "aclk_imem_200",
> --
> 2.34.1

[PATCH 08/11] clk: samsung: exynos7885: do not define number of clocks in bindings

[Krzysztof Kozlowski]

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore this number of clocks
should not be in the bindings, because otherwise we should not change
it.

Define number of clocks per each clock controller inside the driver
directly.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 drivers/clk/samsung/clk-exynos7885.c | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos7885.c b/drivers/clk/samsung/clk-exynos7885.c
index 0c6a84764f7a..f7d7427a558b 100644
--- a/drivers/clk/samsung/clk-exynos7885.c
+++ b/drivers/clk/samsung/clk-exynos7885.c
@@ -16,6 +16,12 @@
 #include "clk.h"
 #include "clk-exynos-arm64.h"
 
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR_TOP			(CLK_GOUT_FSYS_USB30DRD + 1)
+#define CLKS_NR_CORE			(CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1)
+#define CLKS_NR_PERI			(CLK_GOUT_WDT1_PCLK + 1)
+#define CLKS_NR_FSYS			(CLK_GOUT_MMC_SDIO_SDCLKIN + 1)
+
 /* ---- CMU_TOP ------------------------------------------------------------- */
 
 /* Register Offset definitions for CMU_TOP (0x12060000) */
@@ -333,7 +339,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(top_div_clks),
 	.gate_clks		= top_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(top_gate_clks),
-	.nr_clk_ids		= TOP_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_TOP,
 	.clk_regs		= top_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(top_clk_regs),
 };
@@ -552,7 +558,7 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = {
 	.nr_mux_clks		= ARRAY_SIZE(peri_mux_clks),
 	.gate_clks		= peri_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(peri_gate_clks),
-	.nr_clk_ids		= PERI_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_PERI,
 	.clk_regs		= peri_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(peri_clk_regs),
 	.clk_name		= "dout_peri_bus",
@@ -661,7 +667,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(core_div_clks),
 	.gate_clks		= core_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(core_gate_clks),
-	.nr_clk_ids		= CORE_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_CORE,
 	.clk_regs		= core_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(core_clk_regs),
 	.clk_name		= "dout_core_bus",
@@ -743,7 +749,7 @@ static const struct samsung_cmu_info fsys_cmu_info __initconst = {
 	.nr_mux_clks		= ARRAY_SIZE(fsys_mux_clks),
 	.gate_clks		= fsys_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(fsys_gate_clks),
-	.nr_clk_ids		= FSYS_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_FSYS,
 	.clk_regs		= fsys_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(fsys_clk_regs),
 	.clk_name		= "dout_fsys_bus",
-- 
2.34.1

RE: [PATCH 08/11] clk: samsung: exynos7885: do not define number of clocks in bindings

[Alim Akhtar]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Tuesday, August 8, 2023 1:58 PM
> To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Sylwester
> Nawrocki <s.nawrocki@samsung.com>; Tomasz Figa
> <tomasz.figa@gmail.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim
> Akhtar <alim.akhtar@samsung.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob
> Herring <robh+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org
> Subject: [PATCH 08/11] clk: samsung: exynos7885: do not define number of
> clocks in bindings
> 
> Number of clocks supported by Linux drivers might vary - sometimes we add
> new clocks, not exposed previously.  Therefore this number of clocks
should
> not be in the bindings, because otherwise we should not change it.
> 
> Define number of clocks per each clock controller inside the driver
directly.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---

Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

>  drivers/clk/samsung/clk-exynos7885.c | 14 ++++++++++----
>  1 file changed, 10 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos7885.c
b/drivers/clk/samsung/clk-
> exynos7885.c
> index 0c6a84764f7a..f7d7427a558b 100644
> --- a/drivers/clk/samsung/clk-exynos7885.c
> +++ b/drivers/clk/samsung/clk-exynos7885.c
> @@ -16,6 +16,12 @@
>  #include "clk.h"
>  #include "clk-exynos-arm64.h"
> 
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define CLKS_NR_TOP			(CLK_GOUT_FSYS_USB30DRD
> + 1)
> +#define CLKS_NR_CORE
> 	(CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1)
> +#define CLKS_NR_PERI			(CLK_GOUT_WDT1_PCLK + 1)
> +#define CLKS_NR_FSYS
> 	(CLK_GOUT_MMC_SDIO_SDCLKIN + 1)
> +
>  /* ---- CMU_TOP
------------------------------------------------------------- */
> 
>  /* Register Offset definitions for CMU_TOP (0x12060000) */ @@ -333,7
> +339,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst
> = {
>  	.nr_div_clks		= ARRAY_SIZE(top_div_clks),
>  	.gate_clks		= top_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(top_gate_clks),
> -	.nr_clk_ids		= TOP_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_TOP,
>  	.clk_regs		= top_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(top_clk_regs),
>  };
> @@ -552,7 +558,7 @@ static const struct samsung_cmu_info peri_cmu_info
> __initconst = {
>  	.nr_mux_clks		= ARRAY_SIZE(peri_mux_clks),
>  	.gate_clks		= peri_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(peri_gate_clks),
> -	.nr_clk_ids		= PERI_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_PERI,
>  	.clk_regs		= peri_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(peri_clk_regs),
>  	.clk_name		= "dout_peri_bus",
> @@ -661,7 +667,7 @@ static const struct samsung_cmu_info core_cmu_info
> __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(core_div_clks),
>  	.gate_clks		= core_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(core_gate_clks),
> -	.nr_clk_ids		= CORE_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_CORE,
>  	.clk_regs		= core_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(core_clk_regs),
>  	.clk_name		= "dout_core_bus",
> @@ -743,7 +749,7 @@ static const struct samsung_cmu_info fsys_cmu_info
> __initconst = {
>  	.nr_mux_clks		= ARRAY_SIZE(fsys_mux_clks),
>  	.gate_clks		= fsys_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(fsys_gate_clks),
> -	.nr_clk_ids		= FSYS_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_FSYS,
>  	.clk_regs		= fsys_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(fsys_clk_regs),
>  	.clk_name		= "dout_fsys_bus",
> --
> 2.34.1

[PATCH 09/11] clk: samsung: exynos850: do not define number of clocks in bindings

[Krzysztof Kozlowski]

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore this number of clocks
should not be in the bindings, because otherwise we should not change
it.

Define number of clocks per each clock controller inside the driver
directly.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 drivers/clk/samsung/clk-exynos850.c | 35 ++++++++++++++++++++---------
 1 file changed, 24 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
index c32b2e6451a0..bdc1eef7d6e5 100644
--- a/drivers/clk/samsung/clk-exynos850.c
+++ b/drivers/clk/samsung/clk-exynos850.c
@@ -16,6 +16,19 @@
 #include "clk.h"
 #include "clk-exynos-arm64.h"
 
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR_TOP			(CLK_DOUT_G3D_SWITCH + 1)
+#define CLKS_NR_APM			(CLK_GOUT_SYSREG_APM_PCLK + 1)
+#define CLKS_NR_AUD			(CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
+#define CLKS_NR_CMGP			(CLK_GOUT_SYSREG_CMGP_PCLK + 1)
+#define CLKS_NR_G3D			(CLK_GOUT_G3D_SYSREG_PCLK + 1)
+#define CLKS_NR_HSI			(CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
+#define CLKS_NR_IS			(CLK_GOUT_IS_SYSREG_PCLK + 1)
+#define CLKS_NR_MFCMSCL			(CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)
+#define CLKS_NR_PERI			(CLK_GOUT_WDT1_PCLK + 1)
+#define CLKS_NR_CORE			(CLK_GOUT_SYSREG_CORE_PCLK + 1)
+#define CLKS_NR_DPU			(CLK_GOUT_DPU_SYSREG_PCLK + 1)
+
 /* ---- CMU_TOP ------------------------------------------------------------- */
 
 /* Register Offset definitions for CMU_TOP (0x120e0000) */
@@ -485,7 +498,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(top_div_clks),
 	.gate_clks		= top_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(top_gate_clks),
-	.nr_clk_ids		= TOP_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_TOP,
 	.clk_regs		= top_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(top_clk_regs),
 };
@@ -625,7 +638,7 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
 	.nr_gate_clks		= ARRAY_SIZE(apm_gate_clks),
 	.fixed_clks		= apm_fixed_clks,
 	.nr_fixed_clks		= ARRAY_SIZE(apm_fixed_clks),
-	.nr_clk_ids		= APM_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_APM,
 	.clk_regs		= apm_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(apm_clk_regs),
 	.clk_name		= "dout_clkcmu_apm_bus",
@@ -908,7 +921,7 @@ static const struct samsung_cmu_info aud_cmu_info __initconst = {
 	.nr_gate_clks		= ARRAY_SIZE(aud_gate_clks),
 	.fixed_clks		= aud_fixed_clks,
 	.nr_fixed_clks		= ARRAY_SIZE(aud_fixed_clks),
-	.nr_clk_ids		= AUD_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_AUD,
 	.clk_regs		= aud_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(aud_clk_regs),
 	.clk_name		= "dout_aud",
@@ -1011,7 +1024,7 @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
 	.nr_gate_clks		= ARRAY_SIZE(cmgp_gate_clks),
 	.fixed_clks		= cmgp_fixed_clks,
 	.nr_fixed_clks		= ARRAY_SIZE(cmgp_fixed_clks),
-	.nr_clk_ids		= CMGP_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_CMGP,
 	.clk_regs		= cmgp_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(cmgp_clk_regs),
 	.clk_name		= "gout_clkcmu_cmgp_bus",
@@ -1107,7 +1120,7 @@ static const struct samsung_cmu_info g3d_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(g3d_div_clks),
 	.gate_clks		= g3d_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(g3d_gate_clks),
-	.nr_clk_ids		= G3D_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_G3D,
 	.clk_regs		= g3d_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(g3d_clk_regs),
 	.clk_name		= "dout_g3d_switch",
@@ -1209,7 +1222,7 @@ static const struct samsung_cmu_info hsi_cmu_info __initconst = {
 	.nr_mux_clks		= ARRAY_SIZE(hsi_mux_clks),
 	.gate_clks		= hsi_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(hsi_gate_clks),
-	.nr_clk_ids		= HSI_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_HSI,
 	.clk_regs		= hsi_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(hsi_clk_regs),
 	.clk_name		= "dout_hsi_bus",
@@ -1341,7 +1354,7 @@ static const struct samsung_cmu_info is_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(is_div_clks),
 	.gate_clks		= is_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(is_gate_clks),
-	.nr_clk_ids		= IS_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_IS,
 	.clk_regs		= is_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(is_clk_regs),
 	.clk_name		= "dout_is_bus",
@@ -1450,7 +1463,7 @@ static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(mfcmscl_div_clks),
 	.gate_clks		= mfcmscl_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(mfcmscl_gate_clks),
-	.nr_clk_ids		= MFCMSCL_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_MFCMSCL,
 	.clk_regs		= mfcmscl_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(mfcmscl_clk_regs),
 	.clk_name		= "dout_mfcmscl_mfc",
@@ -1625,7 +1638,7 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(peri_div_clks),
 	.gate_clks		= peri_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(peri_gate_clks),
-	.nr_clk_ids		= PERI_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_PERI,
 	.clk_regs		= peri_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(peri_clk_regs),
 	.clk_name		= "dout_peri_bus",
@@ -1732,7 +1745,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(core_div_clks),
 	.gate_clks		= core_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(core_gate_clks),
-	.nr_clk_ids		= CORE_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_CORE,
 	.clk_regs		= core_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(core_clk_regs),
 	.clk_name		= "dout_core_bus",
@@ -1806,7 +1819,7 @@ static const struct samsung_cmu_info dpu_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(dpu_div_clks),
 	.gate_clks		= dpu_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(dpu_gate_clks),
-	.nr_clk_ids		= DPU_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_DPU,
 	.clk_regs		= dpu_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(dpu_clk_regs),
 	.clk_name		= "dout_dpu",
-- 
2.34.1

Re: [PATCH 09/11] clk: samsung: exynos850: do not define number of clocks in bindings

[Sam Protsenko]

On Tue, 8 Aug 2023 at 11:15, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> Number of clocks supported by Linux drivers might vary - sometimes we
> add new clocks, not exposed previously.  Therefore this number of clocks
> should not be in the bindings, because otherwise we should not change
> it.
>
> Define number of clocks per each clock controller inside the driver
> directly.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>

>  drivers/clk/samsung/clk-exynos850.c | 35 ++++++++++++++++++++---------
>  1 file changed, 24 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c
> index c32b2e6451a0..bdc1eef7d6e5 100644
> --- a/drivers/clk/samsung/clk-exynos850.c
> +++ b/drivers/clk/samsung/clk-exynos850.c
> @@ -16,6 +16,19 @@
>  #include "clk.h"
>  #include "clk-exynos-arm64.h"
>
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define CLKS_NR_TOP                    (CLK_DOUT_G3D_SWITCH + 1)
> +#define CLKS_NR_APM                    (CLK_GOUT_SYSREG_APM_PCLK + 1)
> +#define CLKS_NR_AUD                    (CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
> +#define CLKS_NR_CMGP                   (CLK_GOUT_SYSREG_CMGP_PCLK + 1)
> +#define CLKS_NR_G3D                    (CLK_GOUT_G3D_SYSREG_PCLK + 1)
> +#define CLKS_NR_HSI                    (CLK_GOUT_HSI_CMU_HSI_PCLK + 1)
> +#define CLKS_NR_IS                     (CLK_GOUT_IS_SYSREG_PCLK + 1)
> +#define CLKS_NR_MFCMSCL                        (CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)
> +#define CLKS_NR_PERI                   (CLK_GOUT_WDT1_PCLK + 1)
> +#define CLKS_NR_CORE                   (CLK_GOUT_SYSREG_CORE_PCLK + 1)
> +#define CLKS_NR_DPU                    (CLK_GOUT_DPU_SYSREG_PCLK + 1)
> +
>  /* ---- CMU_TOP ------------------------------------------------------------- */
>
>  /* Register Offset definitions for CMU_TOP (0x120e0000) */
> @@ -485,7 +498,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
>         .nr_div_clks            = ARRAY_SIZE(top_div_clks),
>         .gate_clks              = top_gate_clks,
>         .nr_gate_clks           = ARRAY_SIZE(top_gate_clks),
> -       .nr_clk_ids             = TOP_NR_CLK,
> +       .nr_clk_ids             = CLKS_NR_TOP,
>         .clk_regs               = top_clk_regs,
>         .nr_clk_regs            = ARRAY_SIZE(top_clk_regs),
>  };
> @@ -625,7 +638,7 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = {
>         .nr_gate_clks           = ARRAY_SIZE(apm_gate_clks),
>         .fixed_clks             = apm_fixed_clks,
>         .nr_fixed_clks          = ARRAY_SIZE(apm_fixed_clks),
> -       .nr_clk_ids             = APM_NR_CLK,
> +       .nr_clk_ids             = CLKS_NR_APM,
>         .clk_regs               = apm_clk_regs,
>         .nr_clk_regs            = ARRAY_SIZE(apm_clk_regs),
>         .clk_name               = "dout_clkcmu_apm_bus",
> @@ -908,7 +921,7 @@ static const struct samsung_cmu_info aud_cmu_info __initconst = {
>         .nr_gate_clks           = ARRAY_SIZE(aud_gate_clks),
>         .fixed_clks             = aud_fixed_clks,
>         .nr_fixed_clks          = ARRAY_SIZE(aud_fixed_clks),
> -       .nr_clk_ids             = AUD_NR_CLK,
> +       .nr_clk_ids             = CLKS_NR_AUD,
>         .clk_regs               = aud_clk_regs,
>         .nr_clk_regs            = ARRAY_SIZE(aud_clk_regs),
>         .clk_name               = "dout_aud",
> @@ -1011,7 +1024,7 @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = {
>         .nr_gate_clks           = ARRAY_SIZE(cmgp_gate_clks),
>         .fixed_clks             = cmgp_fixed_clks,
>         .nr_fixed_clks          = ARRAY_SIZE(cmgp_fixed_clks),
> -       .nr_clk_ids             = CMGP_NR_CLK,
> +       .nr_clk_ids             = CLKS_NR_CMGP,
>         .clk_regs               = cmgp_clk_regs,
>         .nr_clk_regs            = ARRAY_SIZE(cmgp_clk_regs),
>         .clk_name               = "gout_clkcmu_cmgp_bus",
> @@ -1107,7 +1120,7 @@ static const struct samsung_cmu_info g3d_cmu_info __initconst = {
>         .nr_div_clks            = ARRAY_SIZE(g3d_div_clks),
>         .gate_clks              = g3d_gate_clks,
>         .nr_gate_clks           = ARRAY_SIZE(g3d_gate_clks),
> -       .nr_clk_ids             = G3D_NR_CLK,
> +       .nr_clk_ids             = CLKS_NR_G3D,
>         .clk_regs               = g3d_clk_regs,
>         .nr_clk_regs            = ARRAY_SIZE(g3d_clk_regs),
>         .clk_name               = "dout_g3d_switch",
> @@ -1209,7 +1222,7 @@ static const struct samsung_cmu_info hsi_cmu_info __initconst = {
>         .nr_mux_clks            = ARRAY_SIZE(hsi_mux_clks),
>         .gate_clks              = hsi_gate_clks,
>         .nr_gate_clks           = ARRAY_SIZE(hsi_gate_clks),
> -       .nr_clk_ids             = HSI_NR_CLK,
> +       .nr_clk_ids             = CLKS_NR_HSI,
>         .clk_regs               = hsi_clk_regs,
>         .nr_clk_regs            = ARRAY_SIZE(hsi_clk_regs),
>         .clk_name               = "dout_hsi_bus",
> @@ -1341,7 +1354,7 @@ static const struct samsung_cmu_info is_cmu_info __initconst = {
>         .nr_div_clks            = ARRAY_SIZE(is_div_clks),
>         .gate_clks              = is_gate_clks,
>         .nr_gate_clks           = ARRAY_SIZE(is_gate_clks),
> -       .nr_clk_ids             = IS_NR_CLK,
> +       .nr_clk_ids             = CLKS_NR_IS,
>         .clk_regs               = is_clk_regs,
>         .nr_clk_regs            = ARRAY_SIZE(is_clk_regs),
>         .clk_name               = "dout_is_bus",
> @@ -1450,7 +1463,7 @@ static const struct samsung_cmu_info mfcmscl_cmu_info __initconst = {
>         .nr_div_clks            = ARRAY_SIZE(mfcmscl_div_clks),
>         .gate_clks              = mfcmscl_gate_clks,
>         .nr_gate_clks           = ARRAY_SIZE(mfcmscl_gate_clks),
> -       .nr_clk_ids             = MFCMSCL_NR_CLK,
> +       .nr_clk_ids             = CLKS_NR_MFCMSCL,
>         .clk_regs               = mfcmscl_clk_regs,
>         .nr_clk_regs            = ARRAY_SIZE(mfcmscl_clk_regs),
>         .clk_name               = "dout_mfcmscl_mfc",
> @@ -1625,7 +1638,7 @@ static const struct samsung_cmu_info peri_cmu_info __initconst = {
>         .nr_div_clks            = ARRAY_SIZE(peri_div_clks),
>         .gate_clks              = peri_gate_clks,
>         .nr_gate_clks           = ARRAY_SIZE(peri_gate_clks),
> -       .nr_clk_ids             = PERI_NR_CLK,
> +       .nr_clk_ids             = CLKS_NR_PERI,
>         .clk_regs               = peri_clk_regs,
>         .nr_clk_regs            = ARRAY_SIZE(peri_clk_regs),
>         .clk_name               = "dout_peri_bus",
> @@ -1732,7 +1745,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
>         .nr_div_clks            = ARRAY_SIZE(core_div_clks),
>         .gate_clks              = core_gate_clks,
>         .nr_gate_clks           = ARRAY_SIZE(core_gate_clks),
> -       .nr_clk_ids             = CORE_NR_CLK,
> +       .nr_clk_ids             = CLKS_NR_CORE,
>         .clk_regs               = core_clk_regs,
>         .nr_clk_regs            = ARRAY_SIZE(core_clk_regs),
>         .clk_name               = "dout_core_bus",
> @@ -1806,7 +1819,7 @@ static const struct samsung_cmu_info dpu_cmu_info __initconst = {
>         .nr_div_clks            = ARRAY_SIZE(dpu_div_clks),
>         .gate_clks              = dpu_gate_clks,
>         .nr_gate_clks           = ARRAY_SIZE(dpu_gate_clks),
> -       .nr_clk_ids             = DPU_NR_CLK,
> +       .nr_clk_ids             = CLKS_NR_DPU,
>         .clk_regs               = dpu_clk_regs,
>         .nr_clk_regs            = ARRAY_SIZE(dpu_clk_regs),
>         .clk_name               = "dout_dpu",
> --
> 2.34.1
>

RE: [PATCH 09/11] clk: samsung: exynos850: do not define number of clocks in bindings

[Alim Akhtar]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Tuesday, August 8, 2023 1:58 PM
> To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Sylwester
> Nawrocki <s.nawrocki@samsung.com>; Tomasz Figa
> <tomasz.figa@gmail.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim
> Akhtar <alim.akhtar@samsung.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob
> Herring <robh+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org
> Subject: [PATCH 09/11] clk: samsung: exynos850: do not define number of
> clocks in bindings
> 
> Number of clocks supported by Linux drivers might vary - sometimes we add
> new clocks, not exposed previously.  Therefore this number of clocks
should
> not be in the bindings, because otherwise we should not change it.
> 
> Define number of clocks per each clock controller inside the driver
directly.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

>  drivers/clk/samsung/clk-exynos850.c | 35 ++++++++++++++++++++---------
>  1 file changed, 24 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynos850.c
b/drivers/clk/samsung/clk-
> exynos850.c
> index c32b2e6451a0..bdc1eef7d6e5 100644
> --- a/drivers/clk/samsung/clk-exynos850.c
> +++ b/drivers/clk/samsung/clk-exynos850.c
> @@ -16,6 +16,19 @@
>  #include "clk.h"
>  #include "clk-exynos-arm64.h"
> 
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define CLKS_NR_TOP			(CLK_DOUT_G3D_SWITCH +
> 1)
> +#define CLKS_NR_APM
> 	(CLK_GOUT_SYSREG_APM_PCLK + 1)
> +#define CLKS_NR_AUD
> 	(CLK_GOUT_AUD_CMU_AUD_PCLK + 1)
> +#define CLKS_NR_CMGP
> 	(CLK_GOUT_SYSREG_CMGP_PCLK + 1)
> +#define CLKS_NR_G3D
> 	(CLK_GOUT_G3D_SYSREG_PCLK + 1)
> +#define CLKS_NR_HSI			(CLK_GOUT_HSI_CMU_HSI_PCLK +
> 1)
> +#define CLKS_NR_IS			(CLK_GOUT_IS_SYSREG_PCLK + 1)
> +#define CLKS_NR_MFCMSCL
> 	(CLK_GOUT_MFCMSCL_SYSREG_PCLK + 1)
> +#define CLKS_NR_PERI			(CLK_GOUT_WDT1_PCLK + 1)
> +#define CLKS_NR_CORE
> 	(CLK_GOUT_SYSREG_CORE_PCLK + 1)
> +#define CLKS_NR_DPU
> 	(CLK_GOUT_DPU_SYSREG_PCLK + 1)
> +
>  /* ---- CMU_TOP
------------------------------------------------------------- */
> 
>  /* Register Offset definitions for CMU_TOP (0x120e0000) */ @@ -485,7
> +498,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst
> = {
>  	.nr_div_clks		= ARRAY_SIZE(top_div_clks),
>  	.gate_clks		= top_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(top_gate_clks),
> -	.nr_clk_ids		= TOP_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_TOP,
>  	.clk_regs		= top_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(top_clk_regs),
>  };
> @@ -625,7 +638,7 @@ static const struct samsung_cmu_info apm_cmu_info
> __initconst = {
>  	.nr_gate_clks		= ARRAY_SIZE(apm_gate_clks),
>  	.fixed_clks		= apm_fixed_clks,
>  	.nr_fixed_clks		= ARRAY_SIZE(apm_fixed_clks),
> -	.nr_clk_ids		= APM_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_APM,
>  	.clk_regs		= apm_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(apm_clk_regs),
>  	.clk_name		= "dout_clkcmu_apm_bus",
> @@ -908,7 +921,7 @@ static const struct samsung_cmu_info aud_cmu_info
> __initconst = {
>  	.nr_gate_clks		= ARRAY_SIZE(aud_gate_clks),
>  	.fixed_clks		= aud_fixed_clks,
>  	.nr_fixed_clks		= ARRAY_SIZE(aud_fixed_clks),
> -	.nr_clk_ids		= AUD_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_AUD,
>  	.clk_regs		= aud_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(aud_clk_regs),
>  	.clk_name		= "dout_aud",
> @@ -1011,7 +1024,7 @@ static const struct samsung_cmu_info
> cmgp_cmu_info __initconst = {
>  	.nr_gate_clks		= ARRAY_SIZE(cmgp_gate_clks),
>  	.fixed_clks		= cmgp_fixed_clks,
>  	.nr_fixed_clks		= ARRAY_SIZE(cmgp_fixed_clks),
> -	.nr_clk_ids		= CMGP_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_CMGP,
>  	.clk_regs		= cmgp_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(cmgp_clk_regs),
>  	.clk_name		= "gout_clkcmu_cmgp_bus",
> @@ -1107,7 +1120,7 @@ static const struct samsung_cmu_info
> g3d_cmu_info __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(g3d_div_clks),
>  	.gate_clks		= g3d_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(g3d_gate_clks),
> -	.nr_clk_ids		= G3D_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_G3D,
>  	.clk_regs		= g3d_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(g3d_clk_regs),
>  	.clk_name		= "dout_g3d_switch",
> @@ -1209,7 +1222,7 @@ static const struct samsung_cmu_info hsi_cmu_info
> __initconst = {
>  	.nr_mux_clks		= ARRAY_SIZE(hsi_mux_clks),
>  	.gate_clks		= hsi_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(hsi_gate_clks),
> -	.nr_clk_ids		= HSI_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_HSI,
>  	.clk_regs		= hsi_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(hsi_clk_regs),
>  	.clk_name		= "dout_hsi_bus",
> @@ -1341,7 +1354,7 @@ static const struct samsung_cmu_info is_cmu_info
> __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(is_div_clks),
>  	.gate_clks		= is_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(is_gate_clks),
> -	.nr_clk_ids		= IS_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_IS,
>  	.clk_regs		= is_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(is_clk_regs),
>  	.clk_name		= "dout_is_bus",
> @@ -1450,7 +1463,7 @@ static const struct samsung_cmu_info
> mfcmscl_cmu_info __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(mfcmscl_div_clks),
>  	.gate_clks		= mfcmscl_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(mfcmscl_gate_clks),
> -	.nr_clk_ids		= MFCMSCL_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_MFCMSCL,
>  	.clk_regs		= mfcmscl_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(mfcmscl_clk_regs),
>  	.clk_name		= "dout_mfcmscl_mfc",
> @@ -1625,7 +1638,7 @@ static const struct samsung_cmu_info
> peri_cmu_info __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(peri_div_clks),
>  	.gate_clks		= peri_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(peri_gate_clks),
> -	.nr_clk_ids		= PERI_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_PERI,
>  	.clk_regs		= peri_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(peri_clk_regs),
>  	.clk_name		= "dout_peri_bus",
> @@ -1732,7 +1745,7 @@ static const struct samsung_cmu_info
> core_cmu_info __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(core_div_clks),
>  	.gate_clks		= core_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(core_gate_clks),
> -	.nr_clk_ids		= CORE_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_CORE,
>  	.clk_regs		= core_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(core_clk_regs),
>  	.clk_name		= "dout_core_bus",
> @@ -1806,7 +1819,7 @@ static const struct samsung_cmu_info
> dpu_cmu_info __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(dpu_div_clks),
>  	.gate_clks		= dpu_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(dpu_gate_clks),
> -	.nr_clk_ids		= DPU_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_DPU,
>  	.clk_regs		= dpu_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(dpu_clk_regs),
>  	.clk_name		= "dout_dpu",
> --
> 2.34.1

[PATCH 10/11] clk: samsung: exynoautov9: do not define number of clocks in bindings

[Krzysztof Kozlowski]

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore this number of clocks
should not be in the bindings, because otherwise we should not change
it.

Define number of clocks per each clock controller inside the driver
directly.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 drivers/clk/samsung/clk-exynosautov9.c | 29 ++++++++++++++++++--------
 1 file changed, 20 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
index ddef546be545..e9c06eb93e66 100644
--- a/drivers/clk/samsung/clk-exynosautov9.c
+++ b/drivers/clk/samsung/clk-exynosautov9.c
@@ -16,6 +16,17 @@
 #include "clk.h"
 #include "clk-exynos-arm64.h"
 
+/* NOTE: Must be equal to the last clock ID increased by one */
+#define CLKS_NR_TOP			(GOUT_CLKCMU_PERIS_BUS + 1)
+#define CLKS_NR_BUSMC			(CLK_GOUT_BUSMC_SPDMA_PCLK + 1)
+#define CLKS_NR_CORE			(CLK_GOUT_CORE_CMU_CORE_PCLK + 1)
+#define CLKS_NR_FSYS0			(CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1)
+#define CLKS_NR_FSYS1			(CLK_GOUT_FSYS1_USB30_1_ACLK + 1)
+#define CLKS_NR_FSYS2			(CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1)
+#define CLKS_NR_PERIC0			(CLK_GOUT_PERIC0_PCLK_11 + 1)
+#define CLKS_NR_PERIC1			(CLK_GOUT_PERIC1_PCLK_11 + 1)
+#define CLKS_NR_PERIS			(CLK_GOUT_WDT_CLUSTER1 + 1)
+
 /* ---- CMU_TOP ------------------------------------------------------------ */
 
 /* Register Offset definitions for CMU_TOP (0x1b240000) */
@@ -941,7 +952,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst = {
 	.nr_fixed_factor_clks	= ARRAY_SIZE(top_fixed_factor_clks),
 	.gate_clks		= top_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(top_gate_clks),
-	.nr_clk_ids		= TOP_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_TOP,
 	.clk_regs		= top_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(top_clk_regs),
 };
@@ -1001,7 +1012,7 @@ static const struct samsung_cmu_info busmc_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(busmc_div_clks),
 	.gate_clks		= busmc_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(busmc_gate_clks),
-	.nr_clk_ids		= BUSMC_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_BUSMC,
 	.clk_regs		= busmc_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(busmc_clk_regs),
 	.clk_name		= "dout_clkcmu_busmc_bus",
@@ -1059,7 +1070,7 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(core_div_clks),
 	.gate_clks		= core_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(core_gate_clks),
-	.nr_clk_ids		= CORE_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_CORE,
 	.clk_regs		= core_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(core_clk_regs),
 	.clk_name		= "dout_clkcmu_core_bus",
@@ -1299,7 +1310,7 @@ static const struct samsung_cmu_info fsys0_cmu_info __initconst = {
 	.nr_mux_clks		= ARRAY_SIZE(fsys0_mux_clks),
 	.gate_clks		= fsys0_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(fsys0_gate_clks),
-	.nr_clk_ids		= FSYS0_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_FSYS0,
 	.clk_regs		= fsys0_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(fsys0_clk_regs),
 	.clk_name		= "dout_clkcmu_fsys0_bus",
@@ -1426,7 +1437,7 @@ static const struct samsung_cmu_info fsys1_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(fsys1_div_clks),
 	.gate_clks		= fsys1_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(fsys1_gate_clks),
-	.nr_clk_ids		= FSYS1_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_FSYS1,
 	.clk_regs		= fsys1_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(fsys1_clk_regs),
 	.clk_name		= "dout_clkcmu_fsys1_bus",
@@ -1493,7 +1504,7 @@ static const struct samsung_cmu_info fsys2_cmu_info __initconst = {
 	.nr_mux_clks		= ARRAY_SIZE(fsys2_mux_clks),
 	.gate_clks		= fsys2_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(fsys2_gate_clks),
-	.nr_clk_ids		= FSYS2_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_FSYS2,
 	.clk_regs		= fsys2_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(fsys2_clk_regs),
 	.clk_name		= "dout_clkcmu_fsys2_bus",
@@ -1748,7 +1759,7 @@ static const struct samsung_cmu_info peric0_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(peric0_div_clks),
 	.gate_clks		= peric0_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(peric0_gate_clks),
-	.nr_clk_ids		= PERIC0_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_PERIC0,
 	.clk_regs		= peric0_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(peric0_clk_regs),
 	.clk_name		= "dout_clkcmu_peric0_bus",
@@ -2003,7 +2014,7 @@ static const struct samsung_cmu_info peric1_cmu_info __initconst = {
 	.nr_div_clks		= ARRAY_SIZE(peric1_div_clks),
 	.gate_clks		= peric1_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(peric1_gate_clks),
-	.nr_clk_ids		= PERIC1_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_PERIC1,
 	.clk_regs		= peric1_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(peric1_clk_regs),
 	.clk_name		= "dout_clkcmu_peric1_bus",
@@ -2050,7 +2061,7 @@ static const struct samsung_cmu_info peris_cmu_info __initconst = {
 	.nr_mux_clks		= ARRAY_SIZE(peris_mux_clks),
 	.gate_clks		= peris_gate_clks,
 	.nr_gate_clks		= ARRAY_SIZE(peris_gate_clks),
-	.nr_clk_ids		= PERIS_NR_CLK,
+	.nr_clk_ids		= CLKS_NR_PERIS,
 	.clk_regs		= peris_clk_regs,
 	.nr_clk_regs		= ARRAY_SIZE(peris_clk_regs),
 	.clk_name		= "dout_clkcmu_peris_bus",
-- 
2.34.1

RE: [PATCH 10/11] clk: samsung: exynoautov9: do not define number of clocks in bindings

[Alim Akhtar]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Tuesday, August 8, 2023 1:58 PM
> To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Sylwester
> Nawrocki <s.nawrocki@samsung.com>; Tomasz Figa
> <tomasz.figa@gmail.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim
> Akhtar <alim.akhtar@samsung.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob
> Herring <robh+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org
> Subject: [PATCH 10/11] clk: samsung: exynoautov9: do not define number of
> clocks in bindings
> 
> Number of clocks supported by Linux drivers might vary - sometimes we add
> new clocks, not exposed previously.  Therefore this number of clocks
should
> not be in the bindings, because otherwise we should not change it.
> 
> Define number of clocks per each clock controller inside the driver
directly.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

>  drivers/clk/samsung/clk-exynosautov9.c | 29 ++++++++++++++++++--------
>  1 file changed, 20 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/clk/samsung/clk-exynosautov9.c
> b/drivers/clk/samsung/clk-exynosautov9.c
> index ddef546be545..e9c06eb93e66 100644
> --- a/drivers/clk/samsung/clk-exynosautov9.c
> +++ b/drivers/clk/samsung/clk-exynosautov9.c
> @@ -16,6 +16,17 @@
>  #include "clk.h"
>  #include "clk-exynos-arm64.h"
> 
> +/* NOTE: Must be equal to the last clock ID increased by one */
> +#define CLKS_NR_TOP			(GOUT_CLKCMU_PERIS_BUS
> + 1)
> +#define CLKS_NR_BUSMC
> 	(CLK_GOUT_BUSMC_SPDMA_PCLK + 1)
> +#define CLKS_NR_CORE
> 	(CLK_GOUT_CORE_CMU_CORE_PCLK + 1)
> +#define CLKS_NR_FSYS0
> 	(CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1)
> +#define CLKS_NR_FSYS1
> 	(CLK_GOUT_FSYS1_USB30_1_ACLK + 1)
> +#define CLKS_NR_FSYS2
> 	(CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1)
> +#define CLKS_NR_PERIC0			(CLK_GOUT_PERIC0_PCLK_11
> + 1)
> +#define CLKS_NR_PERIC1			(CLK_GOUT_PERIC1_PCLK_11
> + 1)
> +#define CLKS_NR_PERIS			(CLK_GOUT_WDT_CLUSTER1
> + 1)
> +
>  /* ---- CMU_TOP
------------------------------------------------------------ */
> 
>  /* Register Offset definitions for CMU_TOP (0x1b240000) */ @@ -941,7
> +952,7 @@ static const struct samsung_cmu_info top_cmu_info __initconst
> = {
>  	.nr_fixed_factor_clks	= ARRAY_SIZE(top_fixed_factor_clks),
>  	.gate_clks		= top_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(top_gate_clks),
> -	.nr_clk_ids		= TOP_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_TOP,
>  	.clk_regs		= top_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(top_clk_regs),
>  };
> @@ -1001,7 +1012,7 @@ static const struct samsung_cmu_info
> busmc_cmu_info __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(busmc_div_clks),
>  	.gate_clks		= busmc_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(busmc_gate_clks),
> -	.nr_clk_ids		= BUSMC_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_BUSMC,
>  	.clk_regs		= busmc_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(busmc_clk_regs),
>  	.clk_name		= "dout_clkcmu_busmc_bus",
> @@ -1059,7 +1070,7 @@ static const struct samsung_cmu_info
> core_cmu_info __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(core_div_clks),
>  	.gate_clks		= core_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(core_gate_clks),
> -	.nr_clk_ids		= CORE_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_CORE,
>  	.clk_regs		= core_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(core_clk_regs),
>  	.clk_name		= "dout_clkcmu_core_bus",
> @@ -1299,7 +1310,7 @@ static const struct samsung_cmu_info
> fsys0_cmu_info __initconst = {
>  	.nr_mux_clks		= ARRAY_SIZE(fsys0_mux_clks),
>  	.gate_clks		= fsys0_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(fsys0_gate_clks),
> -	.nr_clk_ids		= FSYS0_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_FSYS0,
>  	.clk_regs		= fsys0_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(fsys0_clk_regs),
>  	.clk_name		= "dout_clkcmu_fsys0_bus",
> @@ -1426,7 +1437,7 @@ static const struct samsung_cmu_info
> fsys1_cmu_info __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(fsys1_div_clks),
>  	.gate_clks		= fsys1_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(fsys1_gate_clks),
> -	.nr_clk_ids		= FSYS1_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_FSYS1,
>  	.clk_regs		= fsys1_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(fsys1_clk_regs),
>  	.clk_name		= "dout_clkcmu_fsys1_bus",
> @@ -1493,7 +1504,7 @@ static const struct samsung_cmu_info
> fsys2_cmu_info __initconst = {
>  	.nr_mux_clks		= ARRAY_SIZE(fsys2_mux_clks),
>  	.gate_clks		= fsys2_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(fsys2_gate_clks),
> -	.nr_clk_ids		= FSYS2_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_FSYS2,
>  	.clk_regs		= fsys2_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(fsys2_clk_regs),
>  	.clk_name		= "dout_clkcmu_fsys2_bus",
> @@ -1748,7 +1759,7 @@ static const struct samsung_cmu_info
> peric0_cmu_info __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(peric0_div_clks),
>  	.gate_clks		= peric0_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(peric0_gate_clks),
> -	.nr_clk_ids		= PERIC0_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_PERIC0,
>  	.clk_regs		= peric0_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(peric0_clk_regs),
>  	.clk_name		= "dout_clkcmu_peric0_bus",
> @@ -2003,7 +2014,7 @@ static const struct samsung_cmu_info
> peric1_cmu_info __initconst = {
>  	.nr_div_clks		= ARRAY_SIZE(peric1_div_clks),
>  	.gate_clks		= peric1_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(peric1_gate_clks),
> -	.nr_clk_ids		= PERIC1_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_PERIC1,
>  	.clk_regs		= peric1_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(peric1_clk_regs),
>  	.clk_name		= "dout_clkcmu_peric1_bus",
> @@ -2050,7 +2061,7 @@ static const struct samsung_cmu_info
> peris_cmu_info __initconst = {
>  	.nr_mux_clks		= ARRAY_SIZE(peris_mux_clks),
>  	.gate_clks		= peris_gate_clks,
>  	.nr_gate_clks		= ARRAY_SIZE(peris_gate_clks),
> -	.nr_clk_ids		= PERIS_NR_CLK,
> +	.nr_clk_ids		= CLKS_NR_PERIS,
>  	.clk_regs		= peris_clk_regs,
>  	.nr_clk_regs		= ARRAY_SIZE(peris_clk_regs),
>  	.clk_name		= "dout_clkcmu_peris_bus",
> --
> 2.34.1

[PATCH 11/11] dt-bindings: clock: samsung: remove define with number of clocks

[Krzysztof Kozlowski]

Number of clocks supported by Linux drivers might vary - sometimes we
add new clocks, not exposed previously.  Therefore this number of clocks
should not be in the bindings, because otherwise we should not change
it.  Remove it entirely from the bindings, once Linux drivers stopped
using them.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
 include/dt-bindings/clock/exynos3250.h        | 18 --------
 include/dt-bindings/clock/exynos4.h           |  5 ---
 include/dt-bindings/clock/exynos5250.h        |  3 --
 include/dt-bindings/clock/exynos5260-clk.h    | 25 -----------
 include/dt-bindings/clock/exynos5410.h        |  2 -
 include/dt-bindings/clock/exynos5420.h        |  3 --
 include/dt-bindings/clock/exynos5433.h        | 42 -------------------
 include/dt-bindings/clock/exynos7885.h        |  4 --
 include/dt-bindings/clock/exynos850.h         | 10 -----
 .../dt-bindings/clock/samsung,exynosautov9.h  | 18 --------
 10 files changed, 130 deletions(-)

diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
index fe8214017b46..cc7268151843 100644
--- a/include/dt-bindings/clock/exynos3250.h
+++ b/include/dt-bindings/clock/exynos3250.h
@@ -256,12 +256,6 @@
 #define CLK_SCLK_UART2			248
 #define CLK_SCLK_MMC2			249
 
-/*
- * Total number of clocks of main CMU.
- * NOTE: Must be equal to last clock ID increased by one.
- */
-#define CLK_NR_CLKS			250
-
 /*
  * CMU DMC
  */
@@ -283,12 +277,6 @@
 #define CLK_DIV_DMCP			19
 #define CLK_DIV_DMCD			20
 
-/*
- * Total number of clocks of main CMU.
- * NOTE: Must be equal to last clock ID increased by one.
- */
-#define NR_CLKS_DMC			21
-
 /*
  * CMU ISP
  */
@@ -344,10 +332,4 @@
 #define CLK_ASYNCAXIM			46
 #define CLK_SCLK_MPWM_ISP		47
 
-/*
- * Total number of clocks of CMU_ISP.
- * NOTE: Must be equal to last clock ID increased by one.
- */
-#define NR_CLKS_ISP			48
-
 #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
index acbfbab875ec..4ebff79ed9e2 100644
--- a/include/dt-bindings/clock/exynos4.h
+++ b/include/dt-bindings/clock/exynos4.h
@@ -239,9 +239,6 @@
 #define CLK_DIV_GDR		460
 #define CLK_DIV_CORE2		461
 
-/* must be greater than maximal clock id */
-#define CLK_NR_CLKS		462
-
 /* Exynos4x12 ISP clocks */
 #define CLK_ISP_FIMC_ISP		 1
 #define CLK_ISP_FIMC_DRC		 2
@@ -275,6 +272,4 @@
 #define CLK_ISP_DIV_MCUISP0		29
 #define CLK_ISP_DIV_MCUISP1		30
 
-#define CLK_NR_ISP_CLKS			31
-
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
index 4680da7357d3..2337c028bbe1 100644
--- a/include/dt-bindings/clock/exynos5250.h
+++ b/include/dt-bindings/clock/exynos5250.h
@@ -177,7 +177,4 @@
 #define CLK_MOUT_MPLL		1029
 #define CLK_MOUT_VPLLSRC	1030
 
-/* must be greater than maximal clock id */
-#define CLK_NR_CLKS		1031
-
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
diff --git a/include/dt-bindings/clock/exynos5260-clk.h b/include/dt-bindings/clock/exynos5260-clk.h
index 98a58cbd81b2..dfde40ea40f0 100644
--- a/include/dt-bindings/clock/exynos5260-clk.h
+++ b/include/dt-bindings/clock/exynos5260-clk.h
@@ -137,8 +137,6 @@
 #define PHYCLK_USBHOST20_PHY_CLK48MOHCI			122
 #define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK		123
 #define PHYCLK_USBDRD30_UDRD30_PHYCLOCK			124
-#define TOP_NR_CLK					125
-
 
 /* List Of Clocks For CMU_EGL */
 
@@ -153,8 +151,6 @@
 #define EGL_DOUT_ACLK_EGL				9
 #define EGL_DOUT_EGL2					10
 #define EGL_DOUT_EGL1					11
-#define EGL_NR_CLK					12
-
 
 /* List Of Clocks For CMU_KFC */
 
@@ -168,8 +164,6 @@
 #define KFC_DOUT_KFC_ATCLK				8
 #define KFC_DOUT_KFC2					9
 #define KFC_DOUT_KFC1					10
-#define KFC_NR_CLK					11
-
 
 /* List Of Clocks For CMU_MIF */
 
@@ -200,8 +194,6 @@
 #define MIF_CLK_INTMEM					25
 #define MIF_SCLK_LPDDR3PHY_WRAP_U1			26
 #define MIF_SCLK_LPDDR3PHY_WRAP_U0			27
-#define MIF_NR_CLK					28
-
 
 /* List Of Clocks For CMU_G3D */
 
@@ -211,8 +203,6 @@
 #define G3D_DOUT_ACLK_G3D				4
 #define G3D_CLK_G3D_HPM					5
 #define G3D_CLK_G3D					6
-#define G3D_NR_CLK					7
-
 
 /* List Of Clocks For CMU_AUD */
 
@@ -231,8 +221,6 @@
 #define AUD_SCLK_AUD_UART				13
 #define AUD_SCLK_PCM					14
 #define AUD_SCLK_I2S					15
-#define AUD_NR_CLK					16
-
 
 /* List Of Clocks For CMU_MFC */
 
@@ -241,8 +229,6 @@
 #define MFC_CLK_MFC					3
 #define MFC_CLK_SMMU2_MFCM1				4
 #define MFC_CLK_SMMU2_MFCM0				5
-#define MFC_NR_CLK					6
-
 
 /* List Of Clocks For CMU_GSCL */
 
@@ -272,8 +258,6 @@
 #define GSCL_CLK_SMMU3_MSCL1				24
 #define GSCL_SCLK_CSIS1_WRAP				25
 #define GSCL_SCLK_CSIS0_WRAP				26
-#define GSCL_NR_CLK					27
-
 
 /* List Of Clocks For CMU_FSYS */
 
@@ -295,8 +279,6 @@
 #define FSYS_CLK_SMMU_RTIC				16
 #define FSYS_PHYCLK_USBDRD30				17
 #define FSYS_PHYCLK_USBHOST20				18
-#define FSYS_NR_CLK					19
-
 
 /* List Of Clocks For CMU_PERI */
 
@@ -366,8 +348,6 @@
 #define PERI_SCLK_SPDIF					64
 #define PERI_SCLK_I2S					65
 #define PERI_SCLK_PCM1					66
-#define PERI_NR_CLK					67
-
 
 /* List Of Clocks For CMU_DISP */
 
@@ -406,8 +386,6 @@
 #define DISP_CLK_DP					33
 #define DISP_SCLK_PIXEL					34
 #define DISP_MOUT_HDMI_PHY_PIXEL_USER			35
-#define DISP_NR_CLK					36
-
 
 /* List Of Clocks For CMU_G2D */
 
@@ -423,8 +401,6 @@
 #define G2D_CLK_SMMU_SSS				10
 #define G2D_CLK_SMMU_MDMA				11
 #define G2D_CLK_SMMU3_G2D				12
-#define G2D_NR_CLK					13
-
 
 /* List Of Clocks For CMU_ISP */
 
@@ -461,6 +437,5 @@
 #define ISP_SCLK_SPI0_EXT				31
 #define ISP_SCLK_SPI1_EXT				32
 #define ISP_SCLK_UART_EXT				33
-#define ISP_NR_CLK					34
 
 #endif
diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
index 86c2ad56c5ef..7a1a93f8df6c 100644
--- a/include/dt-bindings/clock/exynos5410.h
+++ b/include/dt-bindings/clock/exynos5410.h
@@ -61,6 +61,4 @@
 #define CLK_USBD301		367
 #define CLK_SSS			471
 
-#define CLK_NR_CLKS		512
-
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 9fffc6ceaadd..73e82527a9e9 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -271,7 +271,4 @@
 #define CLK_DOUT_PCLK_DREX0	798
 #define CLK_DOUT_PCLK_DREX1	799
 
-/* must be greater than maximal clock id */
-#define CLK_NR_CLKS		800
-
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
index 25ffa53573a5..d12c1a963fa1 100644
--- a/include/dt-bindings/clock/exynos5433.h
+++ b/include/dt-bindings/clock/exynos5433.h
@@ -188,8 +188,6 @@
 #define CLK_SCLK_ISP_SPI0_CAM1		252
 #define CLK_SCLK_HDMI_SPDIF_DISP	253
 
-#define TOP_NR_CLK			254
-
 /* CMU_CPIF */
 #define CLK_FOUT_MPHY_PLL		1
 
@@ -200,8 +198,6 @@
 #define CLK_SCLK_MPHY_PLL		11
 #define CLK_SCLK_UFS_MPHY		11
 
-#define CPIF_NR_CLK			12
-
 /* CMU_MIF */
 #define CLK_FOUT_MEM0_PLL		1
 #define CLK_FOUT_MEM1_PLL		2
@@ -396,8 +392,6 @@
 #define CLK_SCLK_BUS_PLL_APOLLO		199
 #define CLK_SCLK_BUS_PLL_ATLAS		200
 
-#define MIF_NR_CLK			201
-
 /* CMU_PERIC */
 #define CLK_PCLK_SPI2			1
 #define CLK_PCLK_SPI1			2
@@ -468,8 +462,6 @@
 #define CLK_DIV_SCLK_SCI		70
 #define CLK_DIV_SCLK_SC_IN		71
 
-#define PERIC_NR_CLK			72
-
 /* CMU_PERIS */
 #define CLK_PCLK_HPM_APBIF		1
 #define CLK_PCLK_TMU1_APBIF		2
@@ -513,8 +505,6 @@
 #define CLK_SCLK_ANTIRBK_CNT		40
 #define CLK_SCLK_OTP_CON		41
 
-#define PERIS_NR_CLK			42
-
 /* CMU_FSYS */
 #define CLK_MOUT_ACLK_FSYS_200_USER	1
 #define CLK_MOUT_SCLK_MMC2_USER		2
@@ -621,8 +611,6 @@
 #define CLK_SCLK_USBDRD30		114
 #define CLK_PCIE			115
 
-#define FSYS_NR_CLK			116
-
 /* CMU_G2D */
 #define CLK_MUX_ACLK_G2D_266_USER	1
 #define CLK_MUX_ACLK_G2D_400_USER	2
@@ -653,8 +641,6 @@
 #define CLK_PCLK_G2D			25
 #define CLK_PCLK_SMMU_G2D		26
 
-#define G2D_NR_CLK			27
-
 /* CMU_DISP */
 #define CLK_FOUT_DISP_PLL				1
 
@@ -771,8 +757,6 @@
 #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY		114
 #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY		115
 
-#define DISP_NR_CLK					116
-
 /* CMU_AUD */
 #define CLK_MOUT_AUD_PLL_USER				1
 #define CLK_MOUT_SCLK_AUD_PCM				2
@@ -824,8 +808,6 @@
 #define CLK_SCLK_I2S_BCLK				46
 #define CLK_SCLK_AUD_I2S				47
 
-#define AUD_NR_CLK					48
-
 /* CMU_BUS{0|1|2} */
 #define CLK_DIV_PCLK_BUS_133				1
 
@@ -840,8 +822,6 @@
 #define CLK_ACLK_BUS2BEND_400				9  /* Only CMU_BUS2 */
 #define CLK_ACLK_BUS2RTND_400				10 /* Only CMU_BUS2 */
 
-#define BUSx_NR_CLK					11
-
 /* CMU_G3D */
 #define CLK_FOUT_G3D_PLL				1
 
@@ -865,8 +845,6 @@
 #define CLK_PCLK_SYSREG_G3D				18
 #define CLK_SCLK_HPM_G3D				19
 
-#define G3D_NR_CLK					20
-
 /* CMU_GSCL */
 #define CLK_MOUT_ACLK_GSCL_111_USER			1
 #define CLK_MOUT_ACLK_GSCL_333_USER			2
@@ -898,8 +876,6 @@
 #define CLK_PCLK_SMMU_GSCL1				27
 #define CLK_PCLK_SMMU_GSCL2				28
 
-#define GSCL_NR_CLK					29
-
 /* CMU_APOLLO */
 #define CLK_FOUT_APOLLO_PLL				1
 
@@ -935,8 +911,6 @@
 #define CLK_SCLK_HPM_APOLLO				29
 #define CLK_SCLK_APOLLO					30
 
-#define APOLLO_NR_CLK					31
-
 /* CMU_ATLAS */
 #define CLK_FOUT_ATLAS_PLL				1
 
@@ -981,8 +955,6 @@
 #define CLK_ATCLK					38
 #define CLK_SCLK_ATLAS					39
 
-#define ATLAS_NR_CLK					40
-
 /* CMU_MSCL */
 #define CLK_MOUT_SCLK_JPEG_USER				1
 #define CLK_MOUT_ACLK_MSCL_400_USER			2
@@ -1016,8 +988,6 @@
 #define CLK_PCLK_SMMU_JPEG				28
 #define CLK_SCLK_JPEG					29
 
-#define MSCL_NR_CLK					30
-
 /* CMU_MFC */
 #define CLK_MOUT_ACLK_MFC_400_USER			1
 
@@ -1040,8 +1010,6 @@
 #define CLK_PCLK_SMMU_MFC_1				17
 #define CLK_PCLK_SMMU_MFC_0				18
 
-#define MFC_NR_CLK					19
-
 /* CMU_HEVC */
 #define CLK_MOUT_ACLK_HEVC_400_USER			1
 
@@ -1064,8 +1032,6 @@
 #define CLK_PCLK_SMMU_HEVC_1				17
 #define CLK_PCLK_SMMU_HEVC_0				18
 
-#define HEVC_NR_CLK					19
-
 /* CMU_ISP */
 #define CLK_MOUT_ACLK_ISP_DIS_400_USER			1
 #define CLK_MOUT_ACLK_ISP_400_USER			2
@@ -1147,8 +1113,6 @@
 #define CLK_SCLK_PIXELASYNCS_ISPC			76
 #define CLK_SCLK_PIXELASYNCM_ISPC			77
 
-#define ISP_NR_CLK					78
-
 /* CMU_CAM0 */
 #define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY			1
 #define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY		2
@@ -1285,8 +1249,6 @@
 #define CLK_SCLK_PIXELASYNCM_LITE_C_INIT		132
 #define CLK_SCLK_PIXELASYNCS_LITE_C_INIT		133
 
-#define CAM0_NR_CLK					134
-
 /* CMU_CAM1 */
 #define CLK_PHYCLK_RXBYTEECLKHS0_S2B			1
 
@@ -1404,12 +1366,8 @@
 #define CLK_ATCLK_ISP					111
 #define CLK_SCLK_ISP_CA5				112
 
-#define CAM1_NR_CLK					113
-
 /* CMU_IMEM */
 #define CLK_ACLK_SLIMSSS		2
 #define CLK_PCLK_SLIMSSS		35
 
-#define IMEM_NR_CLK			36
-
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h
index 8256e7430b63..255e3aa94323 100644
--- a/include/dt-bindings/clock/exynos7885.h
+++ b/include/dt-bindings/clock/exynos7885.h
@@ -69,7 +69,6 @@
 #define CLK_GOUT_FSYS_MMC_EMBD		58
 #define CLK_GOUT_FSYS_MMC_SDIO		59
 #define CLK_GOUT_FSYS_USB30DRD		60
-#define TOP_NR_CLK			61
 
 /* CMU_CORE */
 #define CLK_MOUT_CORE_BUS_USER			1
@@ -86,7 +85,6 @@
 #define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE	12
 #define CLK_GOUT_TREX_P_CORE_PCLK		13
 #define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE	14
-#define CORE_NR_CLK				15
 
 /* CMU_PERI */
 #define CLK_MOUT_PERI_BUS_USER		1
@@ -132,7 +130,6 @@
 #define CLK_GOUT_SYSREG_PERI_PCLK	41
 #define CLK_GOUT_WDT0_PCLK		42
 #define CLK_GOUT_WDT1_PCLK		43
-#define PERI_NR_CLK			44
 
 /* CMU_FSYS */
 #define CLK_MOUT_FSYS_BUS_USER		1
@@ -146,6 +143,5 @@
 #define CLK_GOUT_MMC_EMBD_SDCLKIN	8
 #define CLK_GOUT_MMC_SDIO_ACLK		9
 #define CLK_GOUT_MMC_SDIO_SDCLKIN	10
-#define FSYS_NR_CLK			11
 
 #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */
diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
index afacba338c91..3090e09c9a55 100644
--- a/include/dt-bindings/clock/exynos850.h
+++ b/include/dt-bindings/clock/exynos850.h
@@ -88,7 +88,6 @@
 #define CLK_MOUT_G3D_SWITCH		76
 #define CLK_GOUT_G3D_SWITCH		77
 #define CLK_DOUT_G3D_SWITCH		78
-#define TOP_NR_CLK			79
 
 /* CMU_APM */
 #define CLK_RCO_I3C_PMIC		1
@@ -115,7 +114,6 @@
 #define CLK_GOUT_GPIO_ALIVE_PCLK	22
 #define CLK_GOUT_PMU_ALIVE_PCLK		23
 #define CLK_GOUT_SYSREG_APM_PCLK	24
-#define APM_NR_CLK			25
 
 /* CMU_AUD */
 #define CLK_DOUT_AUD_AUDIF		1
@@ -179,7 +177,6 @@
 #define IOCLK_AUDIOCDCLK6		59
 #define TICK_USB			60
 #define CLK_GOUT_AUD_CMU_AUD_PCLK	61
-#define AUD_NR_CLK			62
 
 /* CMU_CMGP */
 #define CLK_RCO_CMGP			1
@@ -197,7 +194,6 @@
 #define CLK_GOUT_CMGP_USI1_IPCLK	13
 #define CLK_GOUT_CMGP_USI1_PCLK		14
 #define CLK_GOUT_SYSREG_CMGP_PCLK	15
-#define CMGP_NR_CLK			16
 
 /* CMU_G3D */
 #define CLK_FOUT_G3D_PLL		1
@@ -212,7 +208,6 @@
 #define CLK_GOUT_G3D_BUSD_CLK		10
 #define CLK_GOUT_G3D_BUSP_CLK		11
 #define CLK_GOUT_G3D_SYSREG_PCLK	12
-#define G3D_NR_CLK			13
 
 /* CMU_HSI */
 #define CLK_MOUT_HSI_BUS_USER		1
@@ -231,7 +226,6 @@
 #define CLK_GOUT_HSI_PPMU_ACLK		14
 #define CLK_GOUT_HSI_PPMU_PCLK		15
 #define CLK_GOUT_HSI_CMU_HSI_PCLK	16
-#define HSI_NR_CLK			17
 
 /* CMU_IS */
 #define CLK_MOUT_IS_BUS_USER		1
@@ -257,7 +251,6 @@
 #define CLK_GOUT_IS_SYSMMU_IS0_CLK	21
 #define CLK_GOUT_IS_SYSMMU_IS1_CLK	22
 #define CLK_GOUT_IS_SYSREG_PCLK		23
-#define IS_NR_CLK			24
 
 /* CMU_MFCMSCL */
 #define CLK_MOUT_MFCMSCL_MFC_USER		1
@@ -275,7 +268,6 @@
 #define CLK_GOUT_MFCMSCL_PPMU_PCLK		13
 #define CLK_GOUT_MFCMSCL_SYSMMU_CLK		14
 #define CLK_GOUT_MFCMSCL_SYSREG_PCLK		15
-#define MFCMSCL_NR_CLK				16
 
 /* CMU_PERI */
 #define CLK_MOUT_PERI_BUS_USER		1
@@ -312,7 +304,6 @@
 #define CLK_GOUT_UART_PCLK		32
 #define CLK_GOUT_WDT0_PCLK		33
 #define CLK_GOUT_WDT1_PCLK		34
-#define PERI_NR_CLK			35
 
 /* CMU_CORE */
 #define CLK_MOUT_CORE_BUS_USER		1
@@ -329,7 +320,6 @@
 #define CLK_GOUT_SSS_PCLK		12
 #define CLK_GOUT_GPIO_CORE_PCLK		13
 #define CLK_GOUT_SYSREG_CORE_PCLK	14
-#define CORE_NR_CLK			15
 
 /* CMU_DPU */
 #define CLK_MOUT_DPU_USER		1
diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
index 42133af6d6b9..3065375c2d8b 100644
--- a/include/dt-bindings/clock/samsung,exynosautov9.h
+++ b/include/dt-bindings/clock/samsung,exynosautov9.h
@@ -166,16 +166,12 @@
 #define GOUT_CLKCMU_PERIC1_IP		248
 #define GOUT_CLKCMU_PERIS_BUS		249
 
-#define TOP_NR_CLK			250
-
 /* CMU_BUSMC */
 #define CLK_MOUT_BUSMC_BUS_USER		1
 #define CLK_DOUT_BUSMC_BUSP		2
 #define CLK_GOUT_BUSMC_PDMA0_PCLK	3
 #define CLK_GOUT_BUSMC_SPDMA_PCLK	4
 
-#define BUSMC_NR_CLK			5
-
 /* CMU_CORE */
 #define CLK_MOUT_CORE_BUS_USER		1
 #define CLK_DOUT_CORE_BUSP		2
@@ -183,8 +179,6 @@
 #define CLK_GOUT_CORE_CCI_PCLK		4
 #define CLK_GOUT_CORE_CMU_CORE_PCLK	5
 
-#define CORE_NR_CLK			6
-
 /* CMU_FSYS0 */
 #define CLK_MOUT_FSYS0_BUS_USER		1
 #define CLK_MOUT_FSYS0_PCIE_USER	2
@@ -226,8 +220,6 @@
 #define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK		35
 #define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK		36
 
-#define FSYS0_NR_CLK			37
-
 /* CMU_FSYS1 */
 #define FOUT_MMC_PLL				1
 
@@ -251,8 +243,6 @@
 #define CLK_GOUT_FSYS1_USB30_0_ACLK		17
 #define CLK_GOUT_FSYS1_USB30_1_ACLK		18
 
-#define FSYS1_NR_CLK				19
-
 /* CMU_FSYS2 */
 #define CLK_MOUT_FSYS2_BUS_USER		1
 #define CLK_MOUT_FSYS2_UFS_EMBD_USER	2
@@ -262,8 +252,6 @@
 #define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK	6
 #define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO	7
 
-#define FSYS2_NR_CLK			8
-
 /* CMU_PERIC0 */
 #define CLK_MOUT_PERIC0_BUS_USER	1
 #define CLK_MOUT_PERIC0_IP_USER		2
@@ -308,8 +296,6 @@
 #define CLK_GOUT_PERIC0_PCLK_10		42
 #define CLK_GOUT_PERIC0_PCLK_11		43
 
-#define PERIC0_NR_CLK			44
-
 /* CMU_PERIC1 */
 #define CLK_MOUT_PERIC1_BUS_USER	1
 #define CLK_MOUT_PERIC1_IP_USER		2
@@ -354,14 +340,10 @@
 #define CLK_GOUT_PERIC1_PCLK_10		42
 #define CLK_GOUT_PERIC1_PCLK_11		43
 
-#define PERIC1_NR_CLK			44
-
 /* CMU_PERIS */
 #define CLK_MOUT_PERIS_BUS_USER		1
 #define CLK_GOUT_SYSREG_PERIS_PCLK	2
 #define CLK_GOUT_WDT_CLUSTER0		3
 #define CLK_GOUT_WDT_CLUSTER1		4
 
-#define PERIS_NR_CLK			5
-
 #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */
-- 
2.34.1

Re: [PATCH 11/11] dt-bindings: clock: samsung: remove define with number of clocks

[Conor Dooley]

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On Tue, Aug 08, 2023 at 10:27:38AM +0200, Krzysztof Kozlowski wrote:
> Number of clocks supported by Linux drivers might vary - sometimes we
> add new clocks, not exposed previously.  Therefore this number of clocks
> should not be in the bindings, because otherwise we should not change
> it.

This sentence reads super awkwardly, not by any means important to
change, but I'd likely word it "Therefore these numbers of clocks should
not be in the bindings, as that prevents changing them".

> Remove it entirely from the bindings, once Linux drivers stopped
> using them.

I figure there are no consumers in other projects then? If so,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
>  include/dt-bindings/clock/exynos3250.h        | 18 --------
>  include/dt-bindings/clock/exynos4.h           |  5 ---
>  include/dt-bindings/clock/exynos5250.h        |  3 --
>  include/dt-bindings/clock/exynos5260-clk.h    | 25 -----------
>  include/dt-bindings/clock/exynos5410.h        |  2 -
>  include/dt-bindings/clock/exynos5420.h        |  3 --
>  include/dt-bindings/clock/exynos5433.h        | 42 -------------------
>  include/dt-bindings/clock/exynos7885.h        |  4 --
>  include/dt-bindings/clock/exynos850.h         | 10 -----
>  .../dt-bindings/clock/samsung,exynosautov9.h  | 18 --------
>  10 files changed, 130 deletions(-)
> 
> diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
> index fe8214017b46..cc7268151843 100644
> --- a/include/dt-bindings/clock/exynos3250.h
> +++ b/include/dt-bindings/clock/exynos3250.h
> @@ -256,12 +256,6 @@
>  #define CLK_SCLK_UART2			248
>  #define CLK_SCLK_MMC2			249
>  
> -/*
> - * Total number of clocks of main CMU.
> - * NOTE: Must be equal to last clock ID increased by one.
> - */
> -#define CLK_NR_CLKS			250
> -
>  /*
>   * CMU DMC
>   */
> @@ -283,12 +277,6 @@
>  #define CLK_DIV_DMCP			19
>  #define CLK_DIV_DMCD			20
>  
> -/*
> - * Total number of clocks of main CMU.
> - * NOTE: Must be equal to last clock ID increased by one.
> - */
> -#define NR_CLKS_DMC			21
> -
>  /*
>   * CMU ISP
>   */
> @@ -344,10 +332,4 @@
>  #define CLK_ASYNCAXIM			46
>  #define CLK_SCLK_MPWM_ISP		47
>  
> -/*
> - * Total number of clocks of CMU_ISP.
> - * NOTE: Must be equal to last clock ID increased by one.
> - */
> -#define NR_CLKS_ISP			48
> -
>  #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
> diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
> index acbfbab875ec..4ebff79ed9e2 100644
> --- a/include/dt-bindings/clock/exynos4.h
> +++ b/include/dt-bindings/clock/exynos4.h
> @@ -239,9 +239,6 @@
>  #define CLK_DIV_GDR		460
>  #define CLK_DIV_CORE2		461
>  
> -/* must be greater than maximal clock id */
> -#define CLK_NR_CLKS		462
> -
>  /* Exynos4x12 ISP clocks */
>  #define CLK_ISP_FIMC_ISP		 1
>  #define CLK_ISP_FIMC_DRC		 2
> @@ -275,6 +272,4 @@
>  #define CLK_ISP_DIV_MCUISP0		29
>  #define CLK_ISP_DIV_MCUISP1		30
>  
> -#define CLK_NR_ISP_CLKS			31
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
> diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
> index 4680da7357d3..2337c028bbe1 100644
> --- a/include/dt-bindings/clock/exynos5250.h
> +++ b/include/dt-bindings/clock/exynos5250.h
> @@ -177,7 +177,4 @@
>  #define CLK_MOUT_MPLL		1029
>  #define CLK_MOUT_VPLLSRC	1030
>  
> -/* must be greater than maximal clock id */
> -#define CLK_NR_CLKS		1031
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
> diff --git a/include/dt-bindings/clock/exynos5260-clk.h b/include/dt-bindings/clock/exynos5260-clk.h
> index 98a58cbd81b2..dfde40ea40f0 100644
> --- a/include/dt-bindings/clock/exynos5260-clk.h
> +++ b/include/dt-bindings/clock/exynos5260-clk.h
> @@ -137,8 +137,6 @@
>  #define PHYCLK_USBHOST20_PHY_CLK48MOHCI			122
>  #define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK		123
>  #define PHYCLK_USBDRD30_UDRD30_PHYCLOCK			124
> -#define TOP_NR_CLK					125
> -
>  
>  /* List Of Clocks For CMU_EGL */
>  
> @@ -153,8 +151,6 @@
>  #define EGL_DOUT_ACLK_EGL				9
>  #define EGL_DOUT_EGL2					10
>  #define EGL_DOUT_EGL1					11
> -#define EGL_NR_CLK					12
> -
>  
>  /* List Of Clocks For CMU_KFC */
>  
> @@ -168,8 +164,6 @@
>  #define KFC_DOUT_KFC_ATCLK				8
>  #define KFC_DOUT_KFC2					9
>  #define KFC_DOUT_KFC1					10
> -#define KFC_NR_CLK					11
> -
>  
>  /* List Of Clocks For CMU_MIF */
>  
> @@ -200,8 +194,6 @@
>  #define MIF_CLK_INTMEM					25
>  #define MIF_SCLK_LPDDR3PHY_WRAP_U1			26
>  #define MIF_SCLK_LPDDR3PHY_WRAP_U0			27
> -#define MIF_NR_CLK					28
> -
>  
>  /* List Of Clocks For CMU_G3D */
>  
> @@ -211,8 +203,6 @@
>  #define G3D_DOUT_ACLK_G3D				4
>  #define G3D_CLK_G3D_HPM					5
>  #define G3D_CLK_G3D					6
> -#define G3D_NR_CLK					7
> -
>  
>  /* List Of Clocks For CMU_AUD */
>  
> @@ -231,8 +221,6 @@
>  #define AUD_SCLK_AUD_UART				13
>  #define AUD_SCLK_PCM					14
>  #define AUD_SCLK_I2S					15
> -#define AUD_NR_CLK					16
> -
>  
>  /* List Of Clocks For CMU_MFC */
>  
> @@ -241,8 +229,6 @@
>  #define MFC_CLK_MFC					3
>  #define MFC_CLK_SMMU2_MFCM1				4
>  #define MFC_CLK_SMMU2_MFCM0				5
> -#define MFC_NR_CLK					6
> -
>  
>  /* List Of Clocks For CMU_GSCL */
>  
> @@ -272,8 +258,6 @@
>  #define GSCL_CLK_SMMU3_MSCL1				24
>  #define GSCL_SCLK_CSIS1_WRAP				25
>  #define GSCL_SCLK_CSIS0_WRAP				26
> -#define GSCL_NR_CLK					27
> -
>  
>  /* List Of Clocks For CMU_FSYS */
>  
> @@ -295,8 +279,6 @@
>  #define FSYS_CLK_SMMU_RTIC				16
>  #define FSYS_PHYCLK_USBDRD30				17
>  #define FSYS_PHYCLK_USBHOST20				18
> -#define FSYS_NR_CLK					19
> -
>  
>  /* List Of Clocks For CMU_PERI */
>  
> @@ -366,8 +348,6 @@
>  #define PERI_SCLK_SPDIF					64
>  #define PERI_SCLK_I2S					65
>  #define PERI_SCLK_PCM1					66
> -#define PERI_NR_CLK					67
> -
>  
>  /* List Of Clocks For CMU_DISP */
>  
> @@ -406,8 +386,6 @@
>  #define DISP_CLK_DP					33
>  #define DISP_SCLK_PIXEL					34
>  #define DISP_MOUT_HDMI_PHY_PIXEL_USER			35
> -#define DISP_NR_CLK					36
> -
>  
>  /* List Of Clocks For CMU_G2D */
>  
> @@ -423,8 +401,6 @@
>  #define G2D_CLK_SMMU_SSS				10
>  #define G2D_CLK_SMMU_MDMA				11
>  #define G2D_CLK_SMMU3_G2D				12
> -#define G2D_NR_CLK					13
> -
>  
>  /* List Of Clocks For CMU_ISP */
>  
> @@ -461,6 +437,5 @@
>  #define ISP_SCLK_SPI0_EXT				31
>  #define ISP_SCLK_SPI1_EXT				32
>  #define ISP_SCLK_UART_EXT				33
> -#define ISP_NR_CLK					34
>  
>  #endif
> diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
> index 86c2ad56c5ef..7a1a93f8df6c 100644
> --- a/include/dt-bindings/clock/exynos5410.h
> +++ b/include/dt-bindings/clock/exynos5410.h
> @@ -61,6 +61,4 @@
>  #define CLK_USBD301		367
>  #define CLK_SSS			471
>  
> -#define CLK_NR_CLKS		512
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
> diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
> index 9fffc6ceaadd..73e82527a9e9 100644
> --- a/include/dt-bindings/clock/exynos5420.h
> +++ b/include/dt-bindings/clock/exynos5420.h
> @@ -271,7 +271,4 @@
>  #define CLK_DOUT_PCLK_DREX0	798
>  #define CLK_DOUT_PCLK_DREX1	799
>  
> -/* must be greater than maximal clock id */
> -#define CLK_NR_CLKS		800
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
> diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
> index 25ffa53573a5..d12c1a963fa1 100644
> --- a/include/dt-bindings/clock/exynos5433.h
> +++ b/include/dt-bindings/clock/exynos5433.h
> @@ -188,8 +188,6 @@
>  #define CLK_SCLK_ISP_SPI0_CAM1		252
>  #define CLK_SCLK_HDMI_SPDIF_DISP	253
>  
> -#define TOP_NR_CLK			254
> -
>  /* CMU_CPIF */
>  #define CLK_FOUT_MPHY_PLL		1
>  
> @@ -200,8 +198,6 @@
>  #define CLK_SCLK_MPHY_PLL		11
>  #define CLK_SCLK_UFS_MPHY		11
>  
> -#define CPIF_NR_CLK			12
> -
>  /* CMU_MIF */
>  #define CLK_FOUT_MEM0_PLL		1
>  #define CLK_FOUT_MEM1_PLL		2
> @@ -396,8 +392,6 @@
>  #define CLK_SCLK_BUS_PLL_APOLLO		199
>  #define CLK_SCLK_BUS_PLL_ATLAS		200
>  
> -#define MIF_NR_CLK			201
> -
>  /* CMU_PERIC */
>  #define CLK_PCLK_SPI2			1
>  #define CLK_PCLK_SPI1			2
> @@ -468,8 +462,6 @@
>  #define CLK_DIV_SCLK_SCI		70
>  #define CLK_DIV_SCLK_SC_IN		71
>  
> -#define PERIC_NR_CLK			72
> -
>  /* CMU_PERIS */
>  #define CLK_PCLK_HPM_APBIF		1
>  #define CLK_PCLK_TMU1_APBIF		2
> @@ -513,8 +505,6 @@
>  #define CLK_SCLK_ANTIRBK_CNT		40
>  #define CLK_SCLK_OTP_CON		41
>  
> -#define PERIS_NR_CLK			42
> -
>  /* CMU_FSYS */
>  #define CLK_MOUT_ACLK_FSYS_200_USER	1
>  #define CLK_MOUT_SCLK_MMC2_USER		2
> @@ -621,8 +611,6 @@
>  #define CLK_SCLK_USBDRD30		114
>  #define CLK_PCIE			115
>  
> -#define FSYS_NR_CLK			116
> -
>  /* CMU_G2D */
>  #define CLK_MUX_ACLK_G2D_266_USER	1
>  #define CLK_MUX_ACLK_G2D_400_USER	2
> @@ -653,8 +641,6 @@
>  #define CLK_PCLK_G2D			25
>  #define CLK_PCLK_SMMU_G2D		26
>  
> -#define G2D_NR_CLK			27
> -
>  /* CMU_DISP */
>  #define CLK_FOUT_DISP_PLL				1
>  
> @@ -771,8 +757,6 @@
>  #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY		114
>  #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY		115
>  
> -#define DISP_NR_CLK					116
> -
>  /* CMU_AUD */
>  #define CLK_MOUT_AUD_PLL_USER				1
>  #define CLK_MOUT_SCLK_AUD_PCM				2
> @@ -824,8 +808,6 @@
>  #define CLK_SCLK_I2S_BCLK				46
>  #define CLK_SCLK_AUD_I2S				47
>  
> -#define AUD_NR_CLK					48
> -
>  /* CMU_BUS{0|1|2} */
>  #define CLK_DIV_PCLK_BUS_133				1
>  
> @@ -840,8 +822,6 @@
>  #define CLK_ACLK_BUS2BEND_400				9  /* Only CMU_BUS2 */
>  #define CLK_ACLK_BUS2RTND_400				10 /* Only CMU_BUS2 */
>  
> -#define BUSx_NR_CLK					11
> -
>  /* CMU_G3D */
>  #define CLK_FOUT_G3D_PLL				1
>  
> @@ -865,8 +845,6 @@
>  #define CLK_PCLK_SYSREG_G3D				18
>  #define CLK_SCLK_HPM_G3D				19
>  
> -#define G3D_NR_CLK					20
> -
>  /* CMU_GSCL */
>  #define CLK_MOUT_ACLK_GSCL_111_USER			1
>  #define CLK_MOUT_ACLK_GSCL_333_USER			2
> @@ -898,8 +876,6 @@
>  #define CLK_PCLK_SMMU_GSCL1				27
>  #define CLK_PCLK_SMMU_GSCL2				28
>  
> -#define GSCL_NR_CLK					29
> -
>  /* CMU_APOLLO */
>  #define CLK_FOUT_APOLLO_PLL				1
>  
> @@ -935,8 +911,6 @@
>  #define CLK_SCLK_HPM_APOLLO				29
>  #define CLK_SCLK_APOLLO					30
>  
> -#define APOLLO_NR_CLK					31
> -
>  /* CMU_ATLAS */
>  #define CLK_FOUT_ATLAS_PLL				1
>  
> @@ -981,8 +955,6 @@
>  #define CLK_ATCLK					38
>  #define CLK_SCLK_ATLAS					39
>  
> -#define ATLAS_NR_CLK					40
> -
>  /* CMU_MSCL */
>  #define CLK_MOUT_SCLK_JPEG_USER				1
>  #define CLK_MOUT_ACLK_MSCL_400_USER			2
> @@ -1016,8 +988,6 @@
>  #define CLK_PCLK_SMMU_JPEG				28
>  #define CLK_SCLK_JPEG					29
>  
> -#define MSCL_NR_CLK					30
> -
>  /* CMU_MFC */
>  #define CLK_MOUT_ACLK_MFC_400_USER			1
>  
> @@ -1040,8 +1010,6 @@
>  #define CLK_PCLK_SMMU_MFC_1				17
>  #define CLK_PCLK_SMMU_MFC_0				18
>  
> -#define MFC_NR_CLK					19
> -
>  /* CMU_HEVC */
>  #define CLK_MOUT_ACLK_HEVC_400_USER			1
>  
> @@ -1064,8 +1032,6 @@
>  #define CLK_PCLK_SMMU_HEVC_1				17
>  #define CLK_PCLK_SMMU_HEVC_0				18
>  
> -#define HEVC_NR_CLK					19
> -
>  /* CMU_ISP */
>  #define CLK_MOUT_ACLK_ISP_DIS_400_USER			1
>  #define CLK_MOUT_ACLK_ISP_400_USER			2
> @@ -1147,8 +1113,6 @@
>  #define CLK_SCLK_PIXELASYNCS_ISPC			76
>  #define CLK_SCLK_PIXELASYNCM_ISPC			77
>  
> -#define ISP_NR_CLK					78
> -
>  /* CMU_CAM0 */
>  #define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY			1
>  #define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY		2
> @@ -1285,8 +1249,6 @@
>  #define CLK_SCLK_PIXELASYNCM_LITE_C_INIT		132
>  #define CLK_SCLK_PIXELASYNCS_LITE_C_INIT		133
>  
> -#define CAM0_NR_CLK					134
> -
>  /* CMU_CAM1 */
>  #define CLK_PHYCLK_RXBYTEECLKHS0_S2B			1
>  
> @@ -1404,12 +1366,8 @@
>  #define CLK_ATCLK_ISP					111
>  #define CLK_SCLK_ISP_CA5				112
>  
> -#define CAM1_NR_CLK					113
> -
>  /* CMU_IMEM */
>  #define CLK_ACLK_SLIMSSS		2
>  #define CLK_PCLK_SLIMSSS		35
>  
> -#define IMEM_NR_CLK			36
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
> diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h
> index 8256e7430b63..255e3aa94323 100644
> --- a/include/dt-bindings/clock/exynos7885.h
> +++ b/include/dt-bindings/clock/exynos7885.h
> @@ -69,7 +69,6 @@
>  #define CLK_GOUT_FSYS_MMC_EMBD		58
>  #define CLK_GOUT_FSYS_MMC_SDIO		59
>  #define CLK_GOUT_FSYS_USB30DRD		60
> -#define TOP_NR_CLK			61
>  
>  /* CMU_CORE */
>  #define CLK_MOUT_CORE_BUS_USER			1
> @@ -86,7 +85,6 @@
>  #define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE	12
>  #define CLK_GOUT_TREX_P_CORE_PCLK		13
>  #define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE	14
> -#define CORE_NR_CLK				15
>  
>  /* CMU_PERI */
>  #define CLK_MOUT_PERI_BUS_USER		1
> @@ -132,7 +130,6 @@
>  #define CLK_GOUT_SYSREG_PERI_PCLK	41
>  #define CLK_GOUT_WDT0_PCLK		42
>  #define CLK_GOUT_WDT1_PCLK		43
> -#define PERI_NR_CLK			44
>  
>  /* CMU_FSYS */
>  #define CLK_MOUT_FSYS_BUS_USER		1
> @@ -146,6 +143,5 @@
>  #define CLK_GOUT_MMC_EMBD_SDCLKIN	8
>  #define CLK_GOUT_MMC_SDIO_ACLK		9
>  #define CLK_GOUT_MMC_SDIO_SDCLKIN	10
> -#define FSYS_NR_CLK			11
>  
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */
> diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
> index afacba338c91..3090e09c9a55 100644
> --- a/include/dt-bindings/clock/exynos850.h
> +++ b/include/dt-bindings/clock/exynos850.h
> @@ -88,7 +88,6 @@
>  #define CLK_MOUT_G3D_SWITCH		76
>  #define CLK_GOUT_G3D_SWITCH		77
>  #define CLK_DOUT_G3D_SWITCH		78
> -#define TOP_NR_CLK			79
>  
>  /* CMU_APM */
>  #define CLK_RCO_I3C_PMIC		1
> @@ -115,7 +114,6 @@
>  #define CLK_GOUT_GPIO_ALIVE_PCLK	22
>  #define CLK_GOUT_PMU_ALIVE_PCLK		23
>  #define CLK_GOUT_SYSREG_APM_PCLK	24
> -#define APM_NR_CLK			25
>  
>  /* CMU_AUD */
>  #define CLK_DOUT_AUD_AUDIF		1
> @@ -179,7 +177,6 @@
>  #define IOCLK_AUDIOCDCLK6		59
>  #define TICK_USB			60
>  #define CLK_GOUT_AUD_CMU_AUD_PCLK	61
> -#define AUD_NR_CLK			62
>  
>  /* CMU_CMGP */
>  #define CLK_RCO_CMGP			1
> @@ -197,7 +194,6 @@
>  #define CLK_GOUT_CMGP_USI1_IPCLK	13
>  #define CLK_GOUT_CMGP_USI1_PCLK		14
>  #define CLK_GOUT_SYSREG_CMGP_PCLK	15
> -#define CMGP_NR_CLK			16
>  
>  /* CMU_G3D */
>  #define CLK_FOUT_G3D_PLL		1
> @@ -212,7 +208,6 @@
>  #define CLK_GOUT_G3D_BUSD_CLK		10
>  #define CLK_GOUT_G3D_BUSP_CLK		11
>  #define CLK_GOUT_G3D_SYSREG_PCLK	12
> -#define G3D_NR_CLK			13
>  
>  /* CMU_HSI */
>  #define CLK_MOUT_HSI_BUS_USER		1
> @@ -231,7 +226,6 @@
>  #define CLK_GOUT_HSI_PPMU_ACLK		14
>  #define CLK_GOUT_HSI_PPMU_PCLK		15
>  #define CLK_GOUT_HSI_CMU_HSI_PCLK	16
> -#define HSI_NR_CLK			17
>  
>  /* CMU_IS */
>  #define CLK_MOUT_IS_BUS_USER		1
> @@ -257,7 +251,6 @@
>  #define CLK_GOUT_IS_SYSMMU_IS0_CLK	21
>  #define CLK_GOUT_IS_SYSMMU_IS1_CLK	22
>  #define CLK_GOUT_IS_SYSREG_PCLK		23
> -#define IS_NR_CLK			24
>  
>  /* CMU_MFCMSCL */
>  #define CLK_MOUT_MFCMSCL_MFC_USER		1
> @@ -275,7 +268,6 @@
>  #define CLK_GOUT_MFCMSCL_PPMU_PCLK		13
>  #define CLK_GOUT_MFCMSCL_SYSMMU_CLK		14
>  #define CLK_GOUT_MFCMSCL_SYSREG_PCLK		15
> -#define MFCMSCL_NR_CLK				16
>  
>  /* CMU_PERI */
>  #define CLK_MOUT_PERI_BUS_USER		1
> @@ -312,7 +304,6 @@
>  #define CLK_GOUT_UART_PCLK		32
>  #define CLK_GOUT_WDT0_PCLK		33
>  #define CLK_GOUT_WDT1_PCLK		34
> -#define PERI_NR_CLK			35
>  
>  /* CMU_CORE */
>  #define CLK_MOUT_CORE_BUS_USER		1
> @@ -329,7 +320,6 @@
>  #define CLK_GOUT_SSS_PCLK		12
>  #define CLK_GOUT_GPIO_CORE_PCLK		13
>  #define CLK_GOUT_SYSREG_CORE_PCLK	14
> -#define CORE_NR_CLK			15
>  
>  /* CMU_DPU */
>  #define CLK_MOUT_DPU_USER		1
> diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
> index 42133af6d6b9..3065375c2d8b 100644
> --- a/include/dt-bindings/clock/samsung,exynosautov9.h
> +++ b/include/dt-bindings/clock/samsung,exynosautov9.h
> @@ -166,16 +166,12 @@
>  #define GOUT_CLKCMU_PERIC1_IP		248
>  #define GOUT_CLKCMU_PERIS_BUS		249
>  
> -#define TOP_NR_CLK			250
> -
>  /* CMU_BUSMC */
>  #define CLK_MOUT_BUSMC_BUS_USER		1
>  #define CLK_DOUT_BUSMC_BUSP		2
>  #define CLK_GOUT_BUSMC_PDMA0_PCLK	3
>  #define CLK_GOUT_BUSMC_SPDMA_PCLK	4
>  
> -#define BUSMC_NR_CLK			5
> -
>  /* CMU_CORE */
>  #define CLK_MOUT_CORE_BUS_USER		1
>  #define CLK_DOUT_CORE_BUSP		2
> @@ -183,8 +179,6 @@
>  #define CLK_GOUT_CORE_CCI_PCLK		4
>  #define CLK_GOUT_CORE_CMU_CORE_PCLK	5
>  
> -#define CORE_NR_CLK			6
> -
>  /* CMU_FSYS0 */
>  #define CLK_MOUT_FSYS0_BUS_USER		1
>  #define CLK_MOUT_FSYS0_PCIE_USER	2
> @@ -226,8 +220,6 @@
>  #define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK		35
>  #define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK		36
>  
> -#define FSYS0_NR_CLK			37
> -
>  /* CMU_FSYS1 */
>  #define FOUT_MMC_PLL				1
>  
> @@ -251,8 +243,6 @@
>  #define CLK_GOUT_FSYS1_USB30_0_ACLK		17
>  #define CLK_GOUT_FSYS1_USB30_1_ACLK		18
>  
> -#define FSYS1_NR_CLK				19
> -
>  /* CMU_FSYS2 */
>  #define CLK_MOUT_FSYS2_BUS_USER		1
>  #define CLK_MOUT_FSYS2_UFS_EMBD_USER	2
> @@ -262,8 +252,6 @@
>  #define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK	6
>  #define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO	7
>  
> -#define FSYS2_NR_CLK			8
> -
>  /* CMU_PERIC0 */
>  #define CLK_MOUT_PERIC0_BUS_USER	1
>  #define CLK_MOUT_PERIC0_IP_USER		2
> @@ -308,8 +296,6 @@
>  #define CLK_GOUT_PERIC0_PCLK_10		42
>  #define CLK_GOUT_PERIC0_PCLK_11		43
>  
> -#define PERIC0_NR_CLK			44
> -
>  /* CMU_PERIC1 */
>  #define CLK_MOUT_PERIC1_BUS_USER	1
>  #define CLK_MOUT_PERIC1_IP_USER		2
> @@ -354,14 +340,10 @@
>  #define CLK_GOUT_PERIC1_PCLK_10		42
>  #define CLK_GOUT_PERIC1_PCLK_11		43
>  
> -#define PERIC1_NR_CLK			44
> -
>  /* CMU_PERIS */
>  #define CLK_MOUT_PERIS_BUS_USER		1
>  #define CLK_GOUT_SYSREG_PERIS_PCLK	2
>  #define CLK_GOUT_WDT_CLUSTER0		3
>  #define CLK_GOUT_WDT_CLUSTER1		4
>  
> -#define PERIS_NR_CLK			5
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */
> -- 
> 2.34.1
> 

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Re: [PATCH 11/11] dt-bindings: clock: samsung: remove define with number of clocks

[Krzysztof Kozlowski]

On 08/08/2023 12:53, Conor Dooley wrote:
> On Tue, Aug 08, 2023 at 10:27:38AM +0200, Krzysztof Kozlowski wrote:
>> Number of clocks supported by Linux drivers might vary - sometimes we
>> add new clocks, not exposed previously.  Therefore this number of clocks
>> should not be in the bindings, because otherwise we should not change
>> it.
> 
> This sentence reads super awkwardly, not by any means important to
> change, but I'd likely word it "Therefore these numbers of clocks should
> not be in the bindings, as that prevents changing them".

That's better, thanks.

> 
>> Remove it entirely from the bindings, once Linux drivers stopped
>> using them.
> 
> I figure there are no consumers in other projects then? If so,

Difficult to say, nothing known to me. Anyway these are not clock IDs,
so if anyone actually relied on number of clocks in the bindings, they
would have trouble in the first place.


> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>


Best regards,
Krzysztof

Re: [PATCH 11/11] dt-bindings: clock: samsung: remove define with number of clocks

[Sam Protsenko]

On Tue, 8 Aug 2023 at 11:23, Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> Number of clocks supported by Linux drivers might vary - sometimes we
> add new clocks, not exposed previously.  Therefore this number of clocks
> should not be in the bindings, because otherwise we should not change
> it.  Remove it entirely from the bindings, once Linux drivers stopped
> using them.
>
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---

Reviewed-by: Sam Protsenko <semen.protsenko@linaro.org>

>  include/dt-bindings/clock/exynos3250.h        | 18 --------
>  include/dt-bindings/clock/exynos4.h           |  5 ---
>  include/dt-bindings/clock/exynos5250.h        |  3 --
>  include/dt-bindings/clock/exynos5260-clk.h    | 25 -----------
>  include/dt-bindings/clock/exynos5410.h        |  2 -
>  include/dt-bindings/clock/exynos5420.h        |  3 --
>  include/dt-bindings/clock/exynos5433.h        | 42 -------------------
>  include/dt-bindings/clock/exynos7885.h        |  4 --
>  include/dt-bindings/clock/exynos850.h         | 10 -----
>  .../dt-bindings/clock/samsung,exynosautov9.h  | 18 --------
>  10 files changed, 130 deletions(-)
>
> diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-bindings/clock/exynos3250.h
> index fe8214017b46..cc7268151843 100644
> --- a/include/dt-bindings/clock/exynos3250.h
> +++ b/include/dt-bindings/clock/exynos3250.h
> @@ -256,12 +256,6 @@
>  #define CLK_SCLK_UART2                 248
>  #define CLK_SCLK_MMC2                  249
>
> -/*
> - * Total number of clocks of main CMU.
> - * NOTE: Must be equal to last clock ID increased by one.
> - */
> -#define CLK_NR_CLKS                    250
> -
>  /*
>   * CMU DMC
>   */
> @@ -283,12 +277,6 @@
>  #define CLK_DIV_DMCP                   19
>  #define CLK_DIV_DMCD                   20
>
> -/*
> - * Total number of clocks of main CMU.
> - * NOTE: Must be equal to last clock ID increased by one.
> - */
> -#define NR_CLKS_DMC                    21
> -
>  /*
>   * CMU ISP
>   */
> @@ -344,10 +332,4 @@
>  #define CLK_ASYNCAXIM                  46
>  #define CLK_SCLK_MPWM_ISP              47
>
> -/*
> - * Total number of clocks of CMU_ISP.
> - * NOTE: Must be equal to last clock ID increased by one.
> - */
> -#define NR_CLKS_ISP                    48
> -
>  #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */
> diff --git a/include/dt-bindings/clock/exynos4.h b/include/dt-bindings/clock/exynos4.h
> index acbfbab875ec..4ebff79ed9e2 100644
> --- a/include/dt-bindings/clock/exynos4.h
> +++ b/include/dt-bindings/clock/exynos4.h
> @@ -239,9 +239,6 @@
>  #define CLK_DIV_GDR            460
>  #define CLK_DIV_CORE2          461
>
> -/* must be greater than maximal clock id */
> -#define CLK_NR_CLKS            462
> -
>  /* Exynos4x12 ISP clocks */
>  #define CLK_ISP_FIMC_ISP                1
>  #define CLK_ISP_FIMC_DRC                2
> @@ -275,6 +272,4 @@
>  #define CLK_ISP_DIV_MCUISP0            29
>  #define CLK_ISP_DIV_MCUISP1            30
>
> -#define CLK_NR_ISP_CLKS                        31
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */
> diff --git a/include/dt-bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
> index 4680da7357d3..2337c028bbe1 100644
> --- a/include/dt-bindings/clock/exynos5250.h
> +++ b/include/dt-bindings/clock/exynos5250.h
> @@ -177,7 +177,4 @@
>  #define CLK_MOUT_MPLL          1029
>  #define CLK_MOUT_VPLLSRC       1030
>
> -/* must be greater than maximal clock id */
> -#define CLK_NR_CLKS            1031
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */
> diff --git a/include/dt-bindings/clock/exynos5260-clk.h b/include/dt-bindings/clock/exynos5260-clk.h
> index 98a58cbd81b2..dfde40ea40f0 100644
> --- a/include/dt-bindings/clock/exynos5260-clk.h
> +++ b/include/dt-bindings/clock/exynos5260-clk.h
> @@ -137,8 +137,6 @@
>  #define PHYCLK_USBHOST20_PHY_CLK48MOHCI                        122
>  #define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK               123
>  #define PHYCLK_USBDRD30_UDRD30_PHYCLOCK                        124
> -#define TOP_NR_CLK                                     125
> -
>
>  /* List Of Clocks For CMU_EGL */
>
> @@ -153,8 +151,6 @@
>  #define EGL_DOUT_ACLK_EGL                              9
>  #define EGL_DOUT_EGL2                                  10
>  #define EGL_DOUT_EGL1                                  11
> -#define EGL_NR_CLK                                     12
> -
>
>  /* List Of Clocks For CMU_KFC */
>
> @@ -168,8 +164,6 @@
>  #define KFC_DOUT_KFC_ATCLK                             8
>  #define KFC_DOUT_KFC2                                  9
>  #define KFC_DOUT_KFC1                                  10
> -#define KFC_NR_CLK                                     11
> -
>
>  /* List Of Clocks For CMU_MIF */
>
> @@ -200,8 +194,6 @@
>  #define MIF_CLK_INTMEM                                 25
>  #define MIF_SCLK_LPDDR3PHY_WRAP_U1                     26
>  #define MIF_SCLK_LPDDR3PHY_WRAP_U0                     27
> -#define MIF_NR_CLK                                     28
> -
>
>  /* List Of Clocks For CMU_G3D */
>
> @@ -211,8 +203,6 @@
>  #define G3D_DOUT_ACLK_G3D                              4
>  #define G3D_CLK_G3D_HPM                                        5
>  #define G3D_CLK_G3D                                    6
> -#define G3D_NR_CLK                                     7
> -
>
>  /* List Of Clocks For CMU_AUD */
>
> @@ -231,8 +221,6 @@
>  #define AUD_SCLK_AUD_UART                              13
>  #define AUD_SCLK_PCM                                   14
>  #define AUD_SCLK_I2S                                   15
> -#define AUD_NR_CLK                                     16
> -
>
>  /* List Of Clocks For CMU_MFC */
>
> @@ -241,8 +229,6 @@
>  #define MFC_CLK_MFC                                    3
>  #define MFC_CLK_SMMU2_MFCM1                            4
>  #define MFC_CLK_SMMU2_MFCM0                            5
> -#define MFC_NR_CLK                                     6
> -
>
>  /* List Of Clocks For CMU_GSCL */
>
> @@ -272,8 +258,6 @@
>  #define GSCL_CLK_SMMU3_MSCL1                           24
>  #define GSCL_SCLK_CSIS1_WRAP                           25
>  #define GSCL_SCLK_CSIS0_WRAP                           26
> -#define GSCL_NR_CLK                                    27
> -
>
>  /* List Of Clocks For CMU_FSYS */
>
> @@ -295,8 +279,6 @@
>  #define FSYS_CLK_SMMU_RTIC                             16
>  #define FSYS_PHYCLK_USBDRD30                           17
>  #define FSYS_PHYCLK_USBHOST20                          18
> -#define FSYS_NR_CLK                                    19
> -
>
>  /* List Of Clocks For CMU_PERI */
>
> @@ -366,8 +348,6 @@
>  #define PERI_SCLK_SPDIF                                        64
>  #define PERI_SCLK_I2S                                  65
>  #define PERI_SCLK_PCM1                                 66
> -#define PERI_NR_CLK                                    67
> -
>
>  /* List Of Clocks For CMU_DISP */
>
> @@ -406,8 +386,6 @@
>  #define DISP_CLK_DP                                    33
>  #define DISP_SCLK_PIXEL                                        34
>  #define DISP_MOUT_HDMI_PHY_PIXEL_USER                  35
> -#define DISP_NR_CLK                                    36
> -
>
>  /* List Of Clocks For CMU_G2D */
>
> @@ -423,8 +401,6 @@
>  #define G2D_CLK_SMMU_SSS                               10
>  #define G2D_CLK_SMMU_MDMA                              11
>  #define G2D_CLK_SMMU3_G2D                              12
> -#define G2D_NR_CLK                                     13
> -
>
>  /* List Of Clocks For CMU_ISP */
>
> @@ -461,6 +437,5 @@
>  #define ISP_SCLK_SPI0_EXT                              31
>  #define ISP_SCLK_SPI1_EXT                              32
>  #define ISP_SCLK_UART_EXT                              33
> -#define ISP_NR_CLK                                     34
>
>  #endif
> diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-bindings/clock/exynos5410.h
> index 86c2ad56c5ef..7a1a93f8df6c 100644
> --- a/include/dt-bindings/clock/exynos5410.h
> +++ b/include/dt-bindings/clock/exynos5410.h
> @@ -61,6 +61,4 @@
>  #define CLK_USBD301            367
>  #define CLK_SSS                        471
>
> -#define CLK_NR_CLKS            512
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */
> diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
> index 9fffc6ceaadd..73e82527a9e9 100644
> --- a/include/dt-bindings/clock/exynos5420.h
> +++ b/include/dt-bindings/clock/exynos5420.h
> @@ -271,7 +271,4 @@
>  #define CLK_DOUT_PCLK_DREX0    798
>  #define CLK_DOUT_PCLK_DREX1    799
>
> -/* must be greater than maximal clock id */
> -#define CLK_NR_CLKS            800
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */
> diff --git a/include/dt-bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
> index 25ffa53573a5..d12c1a963fa1 100644
> --- a/include/dt-bindings/clock/exynos5433.h
> +++ b/include/dt-bindings/clock/exynos5433.h
> @@ -188,8 +188,6 @@
>  #define CLK_SCLK_ISP_SPI0_CAM1         252
>  #define CLK_SCLK_HDMI_SPDIF_DISP       253
>
> -#define TOP_NR_CLK                     254
> -
>  /* CMU_CPIF */
>  #define CLK_FOUT_MPHY_PLL              1
>
> @@ -200,8 +198,6 @@
>  #define CLK_SCLK_MPHY_PLL              11
>  #define CLK_SCLK_UFS_MPHY              11
>
> -#define CPIF_NR_CLK                    12
> -
>  /* CMU_MIF */
>  #define CLK_FOUT_MEM0_PLL              1
>  #define CLK_FOUT_MEM1_PLL              2
> @@ -396,8 +392,6 @@
>  #define CLK_SCLK_BUS_PLL_APOLLO                199
>  #define CLK_SCLK_BUS_PLL_ATLAS         200
>
> -#define MIF_NR_CLK                     201
> -
>  /* CMU_PERIC */
>  #define CLK_PCLK_SPI2                  1
>  #define CLK_PCLK_SPI1                  2
> @@ -468,8 +462,6 @@
>  #define CLK_DIV_SCLK_SCI               70
>  #define CLK_DIV_SCLK_SC_IN             71
>
> -#define PERIC_NR_CLK                   72
> -
>  /* CMU_PERIS */
>  #define CLK_PCLK_HPM_APBIF             1
>  #define CLK_PCLK_TMU1_APBIF            2
> @@ -513,8 +505,6 @@
>  #define CLK_SCLK_ANTIRBK_CNT           40
>  #define CLK_SCLK_OTP_CON               41
>
> -#define PERIS_NR_CLK                   42
> -
>  /* CMU_FSYS */
>  #define CLK_MOUT_ACLK_FSYS_200_USER    1
>  #define CLK_MOUT_SCLK_MMC2_USER                2
> @@ -621,8 +611,6 @@
>  #define CLK_SCLK_USBDRD30              114
>  #define CLK_PCIE                       115
>
> -#define FSYS_NR_CLK                    116
> -
>  /* CMU_G2D */
>  #define CLK_MUX_ACLK_G2D_266_USER      1
>  #define CLK_MUX_ACLK_G2D_400_USER      2
> @@ -653,8 +641,6 @@
>  #define CLK_PCLK_G2D                   25
>  #define CLK_PCLK_SMMU_G2D              26
>
> -#define G2D_NR_CLK                     27
> -
>  /* CMU_DISP */
>  #define CLK_FOUT_DISP_PLL                              1
>
> @@ -771,8 +757,6 @@
>  #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY            114
>  #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY             115
>
> -#define DISP_NR_CLK                                    116
> -
>  /* CMU_AUD */
>  #define CLK_MOUT_AUD_PLL_USER                          1
>  #define CLK_MOUT_SCLK_AUD_PCM                          2
> @@ -824,8 +808,6 @@
>  #define CLK_SCLK_I2S_BCLK                              46
>  #define CLK_SCLK_AUD_I2S                               47
>
> -#define AUD_NR_CLK                                     48
> -
>  /* CMU_BUS{0|1|2} */
>  #define CLK_DIV_PCLK_BUS_133                           1
>
> @@ -840,8 +822,6 @@
>  #define CLK_ACLK_BUS2BEND_400                          9  /* Only CMU_BUS2 */
>  #define CLK_ACLK_BUS2RTND_400                          10 /* Only CMU_BUS2 */
>
> -#define BUSx_NR_CLK                                    11
> -
>  /* CMU_G3D */
>  #define CLK_FOUT_G3D_PLL                               1
>
> @@ -865,8 +845,6 @@
>  #define CLK_PCLK_SYSREG_G3D                            18
>  #define CLK_SCLK_HPM_G3D                               19
>
> -#define G3D_NR_CLK                                     20
> -
>  /* CMU_GSCL */
>  #define CLK_MOUT_ACLK_GSCL_111_USER                    1
>  #define CLK_MOUT_ACLK_GSCL_333_USER                    2
> @@ -898,8 +876,6 @@
>  #define CLK_PCLK_SMMU_GSCL1                            27
>  #define CLK_PCLK_SMMU_GSCL2                            28
>
> -#define GSCL_NR_CLK                                    29
> -
>  /* CMU_APOLLO */
>  #define CLK_FOUT_APOLLO_PLL                            1
>
> @@ -935,8 +911,6 @@
>  #define CLK_SCLK_HPM_APOLLO                            29
>  #define CLK_SCLK_APOLLO                                        30
>
> -#define APOLLO_NR_CLK                                  31
> -
>  /* CMU_ATLAS */
>  #define CLK_FOUT_ATLAS_PLL                             1
>
> @@ -981,8 +955,6 @@
>  #define CLK_ATCLK                                      38
>  #define CLK_SCLK_ATLAS                                 39
>
> -#define ATLAS_NR_CLK                                   40
> -
>  /* CMU_MSCL */
>  #define CLK_MOUT_SCLK_JPEG_USER                                1
>  #define CLK_MOUT_ACLK_MSCL_400_USER                    2
> @@ -1016,8 +988,6 @@
>  #define CLK_PCLK_SMMU_JPEG                             28
>  #define CLK_SCLK_JPEG                                  29
>
> -#define MSCL_NR_CLK                                    30
> -
>  /* CMU_MFC */
>  #define CLK_MOUT_ACLK_MFC_400_USER                     1
>
> @@ -1040,8 +1010,6 @@
>  #define CLK_PCLK_SMMU_MFC_1                            17
>  #define CLK_PCLK_SMMU_MFC_0                            18
>
> -#define MFC_NR_CLK                                     19
> -
>  /* CMU_HEVC */
>  #define CLK_MOUT_ACLK_HEVC_400_USER                    1
>
> @@ -1064,8 +1032,6 @@
>  #define CLK_PCLK_SMMU_HEVC_1                           17
>  #define CLK_PCLK_SMMU_HEVC_0                           18
>
> -#define HEVC_NR_CLK                                    19
> -
>  /* CMU_ISP */
>  #define CLK_MOUT_ACLK_ISP_DIS_400_USER                 1
>  #define CLK_MOUT_ACLK_ISP_400_USER                     2
> @@ -1147,8 +1113,6 @@
>  #define CLK_SCLK_PIXELASYNCS_ISPC                      76
>  #define CLK_SCLK_PIXELASYNCM_ISPC                      77
>
> -#define ISP_NR_CLK                                     78
> -
>  /* CMU_CAM0 */
>  #define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY                        1
>  #define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY               2
> @@ -1285,8 +1249,6 @@
>  #define CLK_SCLK_PIXELASYNCM_LITE_C_INIT               132
>  #define CLK_SCLK_PIXELASYNCS_LITE_C_INIT               133
>
> -#define CAM0_NR_CLK                                    134
> -
>  /* CMU_CAM1 */
>  #define CLK_PHYCLK_RXBYTEECLKHS0_S2B                   1
>
> @@ -1404,12 +1366,8 @@
>  #define CLK_ATCLK_ISP                                  111
>  #define CLK_SCLK_ISP_CA5                               112
>
> -#define CAM1_NR_CLK                                    113
> -
>  /* CMU_IMEM */
>  #define CLK_ACLK_SLIMSSS               2
>  #define CLK_PCLK_SLIMSSS               35
>
> -#define IMEM_NR_CLK                    36
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */
> diff --git a/include/dt-bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h
> index 8256e7430b63..255e3aa94323 100644
> --- a/include/dt-bindings/clock/exynos7885.h
> +++ b/include/dt-bindings/clock/exynos7885.h
> @@ -69,7 +69,6 @@
>  #define CLK_GOUT_FSYS_MMC_EMBD         58
>  #define CLK_GOUT_FSYS_MMC_SDIO         59
>  #define CLK_GOUT_FSYS_USB30DRD         60
> -#define TOP_NR_CLK                     61
>
>  /* CMU_CORE */
>  #define CLK_MOUT_CORE_BUS_USER                 1
> @@ -86,7 +85,6 @@
>  #define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE       12
>  #define CLK_GOUT_TREX_P_CORE_PCLK              13
>  #define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE       14
> -#define CORE_NR_CLK                            15
>
>  /* CMU_PERI */
>  #define CLK_MOUT_PERI_BUS_USER         1
> @@ -132,7 +130,6 @@
>  #define CLK_GOUT_SYSREG_PERI_PCLK      41
>  #define CLK_GOUT_WDT0_PCLK             42
>  #define CLK_GOUT_WDT1_PCLK             43
> -#define PERI_NR_CLK                    44
>
>  /* CMU_FSYS */
>  #define CLK_MOUT_FSYS_BUS_USER         1
> @@ -146,6 +143,5 @@
>  #define CLK_GOUT_MMC_EMBD_SDCLKIN      8
>  #define CLK_GOUT_MMC_SDIO_ACLK         9
>  #define CLK_GOUT_MMC_SDIO_SDCLKIN      10
> -#define FSYS_NR_CLK                    11
>
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */
> diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
> index afacba338c91..3090e09c9a55 100644
> --- a/include/dt-bindings/clock/exynos850.h
> +++ b/include/dt-bindings/clock/exynos850.h
> @@ -88,7 +88,6 @@
>  #define CLK_MOUT_G3D_SWITCH            76
>  #define CLK_GOUT_G3D_SWITCH            77
>  #define CLK_DOUT_G3D_SWITCH            78
> -#define TOP_NR_CLK                     79
>
>  /* CMU_APM */
>  #define CLK_RCO_I3C_PMIC               1
> @@ -115,7 +114,6 @@
>  #define CLK_GOUT_GPIO_ALIVE_PCLK       22
>  #define CLK_GOUT_PMU_ALIVE_PCLK                23
>  #define CLK_GOUT_SYSREG_APM_PCLK       24
> -#define APM_NR_CLK                     25
>
>  /* CMU_AUD */
>  #define CLK_DOUT_AUD_AUDIF             1
> @@ -179,7 +177,6 @@
>  #define IOCLK_AUDIOCDCLK6              59
>  #define TICK_USB                       60
>  #define CLK_GOUT_AUD_CMU_AUD_PCLK      61
> -#define AUD_NR_CLK                     62
>
>  /* CMU_CMGP */
>  #define CLK_RCO_CMGP                   1
> @@ -197,7 +194,6 @@
>  #define CLK_GOUT_CMGP_USI1_IPCLK       13
>  #define CLK_GOUT_CMGP_USI1_PCLK                14
>  #define CLK_GOUT_SYSREG_CMGP_PCLK      15
> -#define CMGP_NR_CLK                    16
>
>  /* CMU_G3D */
>  #define CLK_FOUT_G3D_PLL               1
> @@ -212,7 +208,6 @@
>  #define CLK_GOUT_G3D_BUSD_CLK          10
>  #define CLK_GOUT_G3D_BUSP_CLK          11
>  #define CLK_GOUT_G3D_SYSREG_PCLK       12
> -#define G3D_NR_CLK                     13
>
>  /* CMU_HSI */
>  #define CLK_MOUT_HSI_BUS_USER          1
> @@ -231,7 +226,6 @@
>  #define CLK_GOUT_HSI_PPMU_ACLK         14
>  #define CLK_GOUT_HSI_PPMU_PCLK         15
>  #define CLK_GOUT_HSI_CMU_HSI_PCLK      16
> -#define HSI_NR_CLK                     17
>
>  /* CMU_IS */
>  #define CLK_MOUT_IS_BUS_USER           1
> @@ -257,7 +251,6 @@
>  #define CLK_GOUT_IS_SYSMMU_IS0_CLK     21
>  #define CLK_GOUT_IS_SYSMMU_IS1_CLK     22
>  #define CLK_GOUT_IS_SYSREG_PCLK                23
> -#define IS_NR_CLK                      24
>
>  /* CMU_MFCMSCL */
>  #define CLK_MOUT_MFCMSCL_MFC_USER              1
> @@ -275,7 +268,6 @@
>  #define CLK_GOUT_MFCMSCL_PPMU_PCLK             13
>  #define CLK_GOUT_MFCMSCL_SYSMMU_CLK            14
>  #define CLK_GOUT_MFCMSCL_SYSREG_PCLK           15
> -#define MFCMSCL_NR_CLK                         16
>
>  /* CMU_PERI */
>  #define CLK_MOUT_PERI_BUS_USER         1
> @@ -312,7 +304,6 @@
>  #define CLK_GOUT_UART_PCLK             32
>  #define CLK_GOUT_WDT0_PCLK             33
>  #define CLK_GOUT_WDT1_PCLK             34
> -#define PERI_NR_CLK                    35
>
>  /* CMU_CORE */
>  #define CLK_MOUT_CORE_BUS_USER         1
> @@ -329,7 +320,6 @@
>  #define CLK_GOUT_SSS_PCLK              12
>  #define CLK_GOUT_GPIO_CORE_PCLK                13
>  #define CLK_GOUT_SYSREG_CORE_PCLK      14
> -#define CORE_NR_CLK                    15
>
>  /* CMU_DPU */
>  #define CLK_MOUT_DPU_USER              1
> diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
> index 42133af6d6b9..3065375c2d8b 100644
> --- a/include/dt-bindings/clock/samsung,exynosautov9.h
> +++ b/include/dt-bindings/clock/samsung,exynosautov9.h
> @@ -166,16 +166,12 @@
>  #define GOUT_CLKCMU_PERIC1_IP          248
>  #define GOUT_CLKCMU_PERIS_BUS          249
>
> -#define TOP_NR_CLK                     250
> -
>  /* CMU_BUSMC */
>  #define CLK_MOUT_BUSMC_BUS_USER                1
>  #define CLK_DOUT_BUSMC_BUSP            2
>  #define CLK_GOUT_BUSMC_PDMA0_PCLK      3
>  #define CLK_GOUT_BUSMC_SPDMA_PCLK      4
>
> -#define BUSMC_NR_CLK                   5
> -
>  /* CMU_CORE */
>  #define CLK_MOUT_CORE_BUS_USER         1
>  #define CLK_DOUT_CORE_BUSP             2
> @@ -183,8 +179,6 @@
>  #define CLK_GOUT_CORE_CCI_PCLK         4
>  #define CLK_GOUT_CORE_CMU_CORE_PCLK    5
>
> -#define CORE_NR_CLK                    6
> -
>  /* CMU_FSYS0 */
>  #define CLK_MOUT_FSYS0_BUS_USER                1
>  #define CLK_MOUT_FSYS0_PCIE_USER       2
> @@ -226,8 +220,6 @@
>  #define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK               35
>  #define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK               36
>
> -#define FSYS0_NR_CLK                   37
> -
>  /* CMU_FSYS1 */
>  #define FOUT_MMC_PLL                           1
>
> @@ -251,8 +243,6 @@
>  #define CLK_GOUT_FSYS1_USB30_0_ACLK            17
>  #define CLK_GOUT_FSYS1_USB30_1_ACLK            18
>
> -#define FSYS1_NR_CLK                           19
> -
>  /* CMU_FSYS2 */
>  #define CLK_MOUT_FSYS2_BUS_USER                1
>  #define CLK_MOUT_FSYS2_UFS_EMBD_USER   2
> @@ -262,8 +252,6 @@
>  #define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK  6
>  #define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO        7
>
> -#define FSYS2_NR_CLK                   8
> -
>  /* CMU_PERIC0 */
>  #define CLK_MOUT_PERIC0_BUS_USER       1
>  #define CLK_MOUT_PERIC0_IP_USER                2
> @@ -308,8 +296,6 @@
>  #define CLK_GOUT_PERIC0_PCLK_10                42
>  #define CLK_GOUT_PERIC0_PCLK_11                43
>
> -#define PERIC0_NR_CLK                  44
> -
>  /* CMU_PERIC1 */
>  #define CLK_MOUT_PERIC1_BUS_USER       1
>  #define CLK_MOUT_PERIC1_IP_USER                2
> @@ -354,14 +340,10 @@
>  #define CLK_GOUT_PERIC1_PCLK_10                42
>  #define CLK_GOUT_PERIC1_PCLK_11                43
>
> -#define PERIC1_NR_CLK                  44
> -
>  /* CMU_PERIS */
>  #define CLK_MOUT_PERIS_BUS_USER                1
>  #define CLK_GOUT_SYSREG_PERIS_PCLK     2
>  #define CLK_GOUT_WDT_CLUSTER0          3
>  #define CLK_GOUT_WDT_CLUSTER1          4
>
> -#define PERIS_NR_CLK                   5
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */
> --
> 2.34.1
>

RE: [PATCH 11/11] dt-bindings: clock: samsung: remove define with number of clocks

[Alim Akhtar]

> -----Original Message-----
> From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Sent: Tuesday, August 8, 2023 1:58 PM
> To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Sylwester
> Nawrocki <s.nawrocki@samsung.com>; Tomasz Figa
> <tomasz.figa@gmail.com>; Chanwoo Choi <cw00.choi@samsung.com>; Alim
> Akhtar <alim.akhtar@samsung.com>; Michael Turquette
> <mturquette@baylibre.com>; Stephen Boyd <sboyd@kernel.org>; Rob
> Herring <robh+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> linux-samsung-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-kernel@vger.kernel.org;
> devicetree@vger.kernel.org
> Subject: [PATCH 11/11] dt-bindings: clock: samsung: remove define with
> number of clocks
> 
> Number of clocks supported by Linux drivers might vary - sometimes we add
> new clocks, not exposed previously.  Therefore this number of clocks
should
> not be in the bindings, because otherwise we should not change it.  Remove
> it entirely from the bindings, once Linux drivers stopped using them.
> 
> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> ---
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>

>  include/dt-bindings/clock/exynos3250.h        | 18 --------
>  include/dt-bindings/clock/exynos4.h           |  5 ---
>  include/dt-bindings/clock/exynos5250.h        |  3 --
>  include/dt-bindings/clock/exynos5260-clk.h    | 25 -----------
>  include/dt-bindings/clock/exynos5410.h        |  2 -
>  include/dt-bindings/clock/exynos5420.h        |  3 --
>  include/dt-bindings/clock/exynos5433.h        | 42 -------------------
>  include/dt-bindings/clock/exynos7885.h        |  4 --
>  include/dt-bindings/clock/exynos850.h         | 10 -----
>  .../dt-bindings/clock/samsung,exynosautov9.h  | 18 --------
>  10 files changed, 130 deletions(-)
> 
> diff --git a/include/dt-bindings/clock/exynos3250.h b/include/dt-
> bindings/clock/exynos3250.h
> index fe8214017b46..cc7268151843 100644
> --- a/include/dt-bindings/clock/exynos3250.h
> +++ b/include/dt-bindings/clock/exynos3250.h
> @@ -256,12 +256,6 @@
>  #define CLK_SCLK_UART2			248
>  #define CLK_SCLK_MMC2			249
> 
> -/*
> - * Total number of clocks of main CMU.
> - * NOTE: Must be equal to last clock ID increased by one.
> - */
> -#define CLK_NR_CLKS			250
> -
>  /*
>   * CMU DMC
>   */
> @@ -283,12 +277,6 @@
>  #define CLK_DIV_DMCP			19
>  #define CLK_DIV_DMCD			20
> 
> -/*
> - * Total number of clocks of main CMU.
> - * NOTE: Must be equal to last clock ID increased by one.
> - */
> -#define NR_CLKS_DMC			21
> -
>  /*
>   * CMU ISP
>   */
> @@ -344,10 +332,4 @@
>  #define CLK_ASYNCAXIM			46
>  #define CLK_SCLK_MPWM_ISP		47
> 
> -/*
> - * Total number of clocks of CMU_ISP.
> - * NOTE: Must be equal to last clock ID increased by one.
> - */
> -#define NR_CLKS_ISP			48
> -
>  #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_EXYNOS3250_CLOCK_H */ diff
> --git a/include/dt-bindings/clock/exynos4.h b/include/dt-
> bindings/clock/exynos4.h
> index acbfbab875ec..4ebff79ed9e2 100644
> --- a/include/dt-bindings/clock/exynos4.h
> +++ b/include/dt-bindings/clock/exynos4.h
> @@ -239,9 +239,6 @@
>  #define CLK_DIV_GDR		460
>  #define CLK_DIV_CORE2		461
> 
> -/* must be greater than maximal clock id */
> -#define CLK_NR_CLKS		462
> -
>  /* Exynos4x12 ISP clocks */
>  #define CLK_ISP_FIMC_ISP		 1
>  #define CLK_ISP_FIMC_DRC		 2
> @@ -275,6 +272,4 @@
>  #define CLK_ISP_DIV_MCUISP0		29
>  #define CLK_ISP_DIV_MCUISP1		30
> 
> -#define CLK_NR_ISP_CLKS			31
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ diff --git a/include/dt-
> bindings/clock/exynos5250.h b/include/dt-bindings/clock/exynos5250.h
> index 4680da7357d3..2337c028bbe1 100644
> --- a/include/dt-bindings/clock/exynos5250.h
> +++ b/include/dt-bindings/clock/exynos5250.h
> @@ -177,7 +177,4 @@
>  #define CLK_MOUT_MPLL		1029
>  #define CLK_MOUT_VPLLSRC	1030
> 
> -/* must be greater than maximal clock id */
> -#define CLK_NR_CLKS		1031
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ diff --git a/include/dt-
> bindings/clock/exynos5260-clk.h b/include/dt-bindings/clock/exynos5260-
> clk.h
> index 98a58cbd81b2..dfde40ea40f0 100644
> --- a/include/dt-bindings/clock/exynos5260-clk.h
> +++ b/include/dt-bindings/clock/exynos5260-clk.h
> @@ -137,8 +137,6 @@
>  #define PHYCLK_USBHOST20_PHY_CLK48MOHCI			122
>  #define PHYCLK_USBDRD30_UDRD30_PIPE_PCLK		123
>  #define PHYCLK_USBDRD30_UDRD30_PHYCLOCK			124
> -#define TOP_NR_CLK					125
> -
> 
>  /* List Of Clocks For CMU_EGL */
> 
> @@ -153,8 +151,6 @@
>  #define EGL_DOUT_ACLK_EGL				9
>  #define EGL_DOUT_EGL2					10
>  #define EGL_DOUT_EGL1					11
> -#define EGL_NR_CLK					12
> -
> 
>  /* List Of Clocks For CMU_KFC */
> 
> @@ -168,8 +164,6 @@
>  #define KFC_DOUT_KFC_ATCLK				8
>  #define KFC_DOUT_KFC2					9
>  #define KFC_DOUT_KFC1					10
> -#define KFC_NR_CLK					11
> -
> 
>  /* List Of Clocks For CMU_MIF */
> 
> @@ -200,8 +194,6 @@
>  #define MIF_CLK_INTMEM					25
>  #define MIF_SCLK_LPDDR3PHY_WRAP_U1			26
>  #define MIF_SCLK_LPDDR3PHY_WRAP_U0			27
> -#define MIF_NR_CLK					28
> -
> 
>  /* List Of Clocks For CMU_G3D */
> 
> @@ -211,8 +203,6 @@
>  #define G3D_DOUT_ACLK_G3D				4
>  #define G3D_CLK_G3D_HPM					5
>  #define G3D_CLK_G3D					6
> -#define G3D_NR_CLK					7
> -
> 
>  /* List Of Clocks For CMU_AUD */
> 
> @@ -231,8 +221,6 @@
>  #define AUD_SCLK_AUD_UART				13
>  #define AUD_SCLK_PCM					14
>  #define AUD_SCLK_I2S					15
> -#define AUD_NR_CLK					16
> -
> 
>  /* List Of Clocks For CMU_MFC */
> 
> @@ -241,8 +229,6 @@
>  #define MFC_CLK_MFC					3
>  #define MFC_CLK_SMMU2_MFCM1				4
>  #define MFC_CLK_SMMU2_MFCM0				5
> -#define MFC_NR_CLK					6
> -
> 
>  /* List Of Clocks For CMU_GSCL */
> 
> @@ -272,8 +258,6 @@
>  #define GSCL_CLK_SMMU3_MSCL1				24
>  #define GSCL_SCLK_CSIS1_WRAP				25
>  #define GSCL_SCLK_CSIS0_WRAP				26
> -#define GSCL_NR_CLK					27
> -
> 
>  /* List Of Clocks For CMU_FSYS */
> 
> @@ -295,8 +279,6 @@
>  #define FSYS_CLK_SMMU_RTIC				16
>  #define FSYS_PHYCLK_USBDRD30				17
>  #define FSYS_PHYCLK_USBHOST20				18
> -#define FSYS_NR_CLK					19
> -
> 
>  /* List Of Clocks For CMU_PERI */
> 
> @@ -366,8 +348,6 @@
>  #define PERI_SCLK_SPDIF					64
>  #define PERI_SCLK_I2S					65
>  #define PERI_SCLK_PCM1					66
> -#define PERI_NR_CLK					67
> -
> 
>  /* List Of Clocks For CMU_DISP */
> 
> @@ -406,8 +386,6 @@
>  #define DISP_CLK_DP					33
>  #define DISP_SCLK_PIXEL					34
>  #define DISP_MOUT_HDMI_PHY_PIXEL_USER			35
> -#define DISP_NR_CLK					36
> -
> 
>  /* List Of Clocks For CMU_G2D */
> 
> @@ -423,8 +401,6 @@
>  #define G2D_CLK_SMMU_SSS				10
>  #define G2D_CLK_SMMU_MDMA				11
>  #define G2D_CLK_SMMU3_G2D				12
> -#define G2D_NR_CLK					13
> -
> 
>  /* List Of Clocks For CMU_ISP */
> 
> @@ -461,6 +437,5 @@
>  #define ISP_SCLK_SPI0_EXT				31
>  #define ISP_SCLK_SPI1_EXT				32
>  #define ISP_SCLK_UART_EXT				33
> -#define ISP_NR_CLK					34
> 
>  #endif
> diff --git a/include/dt-bindings/clock/exynos5410.h b/include/dt-
> bindings/clock/exynos5410.h
> index 86c2ad56c5ef..7a1a93f8df6c 100644
> --- a/include/dt-bindings/clock/exynos5410.h
> +++ b/include/dt-bindings/clock/exynos5410.h
> @@ -61,6 +61,4 @@
>  #define CLK_USBD301		367
>  #define CLK_SSS			471
> 
> -#define CLK_NR_CLKS		512
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5410_H */ diff --git a/include/dt-
> bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
> index 9fffc6ceaadd..73e82527a9e9 100644
> --- a/include/dt-bindings/clock/exynos5420.h
> +++ b/include/dt-bindings/clock/exynos5420.h
> @@ -271,7 +271,4 @@
>  #define CLK_DOUT_PCLK_DREX0	798
>  #define CLK_DOUT_PCLK_DREX1	799
> 
> -/* must be greater than maximal clock id */
> -#define CLK_NR_CLKS		800
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS_5420_H */ diff --git a/include/dt-
> bindings/clock/exynos5433.h b/include/dt-bindings/clock/exynos5433.h
> index 25ffa53573a5..d12c1a963fa1 100644
> --- a/include/dt-bindings/clock/exynos5433.h
> +++ b/include/dt-bindings/clock/exynos5433.h
> @@ -188,8 +188,6 @@
>  #define CLK_SCLK_ISP_SPI0_CAM1		252
>  #define CLK_SCLK_HDMI_SPDIF_DISP	253
> 
> -#define TOP_NR_CLK			254
> -
>  /* CMU_CPIF */
>  #define CLK_FOUT_MPHY_PLL		1
> 
> @@ -200,8 +198,6 @@
>  #define CLK_SCLK_MPHY_PLL		11
>  #define CLK_SCLK_UFS_MPHY		11
> 
> -#define CPIF_NR_CLK			12
> -
>  /* CMU_MIF */
>  #define CLK_FOUT_MEM0_PLL		1
>  #define CLK_FOUT_MEM1_PLL		2
> @@ -396,8 +392,6 @@
>  #define CLK_SCLK_BUS_PLL_APOLLO		199
>  #define CLK_SCLK_BUS_PLL_ATLAS		200
> 
> -#define MIF_NR_CLK			201
> -
>  /* CMU_PERIC */
>  #define CLK_PCLK_SPI2			1
>  #define CLK_PCLK_SPI1			2
> @@ -468,8 +462,6 @@
>  #define CLK_DIV_SCLK_SCI		70
>  #define CLK_DIV_SCLK_SC_IN		71
> 
> -#define PERIC_NR_CLK			72
> -
>  /* CMU_PERIS */
>  #define CLK_PCLK_HPM_APBIF		1
>  #define CLK_PCLK_TMU1_APBIF		2
> @@ -513,8 +505,6 @@
>  #define CLK_SCLK_ANTIRBK_CNT		40
>  #define CLK_SCLK_OTP_CON		41
> 
> -#define PERIS_NR_CLK			42
> -
>  /* CMU_FSYS */
>  #define CLK_MOUT_ACLK_FSYS_200_USER	1
>  #define CLK_MOUT_SCLK_MMC2_USER		2
> @@ -621,8 +611,6 @@
>  #define CLK_SCLK_USBDRD30		114
>  #define CLK_PCIE			115
> 
> -#define FSYS_NR_CLK			116
> -
>  /* CMU_G2D */
>  #define CLK_MUX_ACLK_G2D_266_USER	1
>  #define CLK_MUX_ACLK_G2D_400_USER	2
> @@ -653,8 +641,6 @@
>  #define CLK_PCLK_G2D			25
>  #define CLK_PCLK_SMMU_G2D		26
> 
> -#define G2D_NR_CLK			27
> -
>  /* CMU_DISP */
>  #define CLK_FOUT_DISP_PLL				1
> 
> @@ -771,8 +757,6 @@
>  #define CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY		114
>  #define CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY		115
> 
> -#define DISP_NR_CLK					116
> -
>  /* CMU_AUD */
>  #define CLK_MOUT_AUD_PLL_USER				1
>  #define CLK_MOUT_SCLK_AUD_PCM				2
> @@ -824,8 +808,6 @@
>  #define CLK_SCLK_I2S_BCLK				46
>  #define CLK_SCLK_AUD_I2S				47
> 
> -#define AUD_NR_CLK					48
> -
>  /* CMU_BUS{0|1|2} */
>  #define CLK_DIV_PCLK_BUS_133				1
> 
> @@ -840,8 +822,6 @@
>  #define CLK_ACLK_BUS2BEND_400				9  /* Only
> CMU_BUS2 */
>  #define CLK_ACLK_BUS2RTND_400				10 /* Only
> CMU_BUS2 */
> 
> -#define BUSx_NR_CLK					11
> -
>  /* CMU_G3D */
>  #define CLK_FOUT_G3D_PLL				1
> 
> @@ -865,8 +845,6 @@
>  #define CLK_PCLK_SYSREG_G3D				18
>  #define CLK_SCLK_HPM_G3D				19
> 
> -#define G3D_NR_CLK					20
> -
>  /* CMU_GSCL */
>  #define CLK_MOUT_ACLK_GSCL_111_USER			1
>  #define CLK_MOUT_ACLK_GSCL_333_USER			2
> @@ -898,8 +876,6 @@
>  #define CLK_PCLK_SMMU_GSCL1				27
>  #define CLK_PCLK_SMMU_GSCL2				28
> 
> -#define GSCL_NR_CLK					29
> -
>  /* CMU_APOLLO */
>  #define CLK_FOUT_APOLLO_PLL				1
> 
> @@ -935,8 +911,6 @@
>  #define CLK_SCLK_HPM_APOLLO				29
>  #define CLK_SCLK_APOLLO					30
> 
> -#define APOLLO_NR_CLK					31
> -
>  /* CMU_ATLAS */
>  #define CLK_FOUT_ATLAS_PLL				1
> 
> @@ -981,8 +955,6 @@
>  #define CLK_ATCLK					38
>  #define CLK_SCLK_ATLAS					39
> 
> -#define ATLAS_NR_CLK					40
> -
>  /* CMU_MSCL */
>  #define CLK_MOUT_SCLK_JPEG_USER				1
>  #define CLK_MOUT_ACLK_MSCL_400_USER			2
> @@ -1016,8 +988,6 @@
>  #define CLK_PCLK_SMMU_JPEG				28
>  #define CLK_SCLK_JPEG					29
> 
> -#define MSCL_NR_CLK					30
> -
>  /* CMU_MFC */
>  #define CLK_MOUT_ACLK_MFC_400_USER			1
> 
> @@ -1040,8 +1010,6 @@
>  #define CLK_PCLK_SMMU_MFC_1				17
>  #define CLK_PCLK_SMMU_MFC_0				18
> 
> -#define MFC_NR_CLK					19
> -
>  /* CMU_HEVC */
>  #define CLK_MOUT_ACLK_HEVC_400_USER			1
> 
> @@ -1064,8 +1032,6 @@
>  #define CLK_PCLK_SMMU_HEVC_1				17
>  #define CLK_PCLK_SMMU_HEVC_0				18
> 
> -#define HEVC_NR_CLK					19
> -
>  /* CMU_ISP */
>  #define CLK_MOUT_ACLK_ISP_DIS_400_USER			1
>  #define CLK_MOUT_ACLK_ISP_400_USER			2
> @@ -1147,8 +1113,6 @@
>  #define CLK_SCLK_PIXELASYNCS_ISPC			76
>  #define CLK_SCLK_PIXELASYNCM_ISPC			77
> 
> -#define ISP_NR_CLK					78
> -
>  /* CMU_CAM0 */
>  #define CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY			1
>  #define CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY		2
> @@ -1285,8 +1249,6 @@
>  #define CLK_SCLK_PIXELASYNCM_LITE_C_INIT		132
>  #define CLK_SCLK_PIXELASYNCS_LITE_C_INIT		133
> 
> -#define CAM0_NR_CLK					134
> -
>  /* CMU_CAM1 */
>  #define CLK_PHYCLK_RXBYTEECLKHS0_S2B			1
> 
> @@ -1404,12 +1366,8 @@
>  #define CLK_ATCLK_ISP					111
>  #define CLK_SCLK_ISP_CA5				112
> 
> -#define CAM1_NR_CLK					113
> -
>  /* CMU_IMEM */
>  #define CLK_ACLK_SLIMSSS		2
>  #define CLK_PCLK_SLIMSSS		35
> 
> -#define IMEM_NR_CLK			36
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS5433_H */ diff --git a/include/dt-
> bindings/clock/exynos7885.h b/include/dt-bindings/clock/exynos7885.h
> index 8256e7430b63..255e3aa94323 100644
> --- a/include/dt-bindings/clock/exynos7885.h
> +++ b/include/dt-bindings/clock/exynos7885.h
> @@ -69,7 +69,6 @@
>  #define CLK_GOUT_FSYS_MMC_EMBD		58
>  #define CLK_GOUT_FSYS_MMC_SDIO		59
>  #define CLK_GOUT_FSYS_USB30DRD		60
> -#define TOP_NR_CLK			61
> 
>  /* CMU_CORE */
>  #define CLK_MOUT_CORE_BUS_USER			1
> @@ -86,7 +85,6 @@
>  #define CLK_GOUT_TREX_P_CORE_CCLK_P_CORE	12
>  #define CLK_GOUT_TREX_P_CORE_PCLK		13
>  #define CLK_GOUT_TREX_P_CORE_PCLK_P_CORE	14
> -#define CORE_NR_CLK				15
> 
>  /* CMU_PERI */
>  #define CLK_MOUT_PERI_BUS_USER		1
> @@ -132,7 +130,6 @@
>  #define CLK_GOUT_SYSREG_PERI_PCLK	41
>  #define CLK_GOUT_WDT0_PCLK		42
>  #define CLK_GOUT_WDT1_PCLK		43
> -#define PERI_NR_CLK			44
> 
>  /* CMU_FSYS */
>  #define CLK_MOUT_FSYS_BUS_USER		1
> @@ -146,6 +143,5 @@
>  #define CLK_GOUT_MMC_EMBD_SDCLKIN	8
>  #define CLK_GOUT_MMC_SDIO_ACLK		9
>  #define CLK_GOUT_MMC_SDIO_SDCLKIN	10
> -#define FSYS_NR_CLK			11
> 
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOS_7885_H */ diff --git a/include/dt-
> bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
> index afacba338c91..3090e09c9a55 100644
> --- a/include/dt-bindings/clock/exynos850.h
> +++ b/include/dt-bindings/clock/exynos850.h
> @@ -88,7 +88,6 @@
>  #define CLK_MOUT_G3D_SWITCH		76
>  #define CLK_GOUT_G3D_SWITCH		77
>  #define CLK_DOUT_G3D_SWITCH		78
> -#define TOP_NR_CLK			79
> 
>  /* CMU_APM */
>  #define CLK_RCO_I3C_PMIC		1
> @@ -115,7 +114,6 @@
>  #define CLK_GOUT_GPIO_ALIVE_PCLK	22
>  #define CLK_GOUT_PMU_ALIVE_PCLK		23
>  #define CLK_GOUT_SYSREG_APM_PCLK	24
> -#define APM_NR_CLK			25
> 
>  /* CMU_AUD */
>  #define CLK_DOUT_AUD_AUDIF		1
> @@ -179,7 +177,6 @@
>  #define IOCLK_AUDIOCDCLK6		59
>  #define TICK_USB			60
>  #define CLK_GOUT_AUD_CMU_AUD_PCLK	61
> -#define AUD_NR_CLK			62
> 
>  /* CMU_CMGP */
>  #define CLK_RCO_CMGP			1
> @@ -197,7 +194,6 @@
>  #define CLK_GOUT_CMGP_USI1_IPCLK	13
>  #define CLK_GOUT_CMGP_USI1_PCLK		14
>  #define CLK_GOUT_SYSREG_CMGP_PCLK	15
> -#define CMGP_NR_CLK			16
> 
>  /* CMU_G3D */
>  #define CLK_FOUT_G3D_PLL		1
> @@ -212,7 +208,6 @@
>  #define CLK_GOUT_G3D_BUSD_CLK		10
>  #define CLK_GOUT_G3D_BUSP_CLK		11
>  #define CLK_GOUT_G3D_SYSREG_PCLK	12
> -#define G3D_NR_CLK			13
> 
>  /* CMU_HSI */
>  #define CLK_MOUT_HSI_BUS_USER		1
> @@ -231,7 +226,6 @@
>  #define CLK_GOUT_HSI_PPMU_ACLK		14
>  #define CLK_GOUT_HSI_PPMU_PCLK		15
>  #define CLK_GOUT_HSI_CMU_HSI_PCLK	16
> -#define HSI_NR_CLK			17
> 
>  /* CMU_IS */
>  #define CLK_MOUT_IS_BUS_USER		1
> @@ -257,7 +251,6 @@
>  #define CLK_GOUT_IS_SYSMMU_IS0_CLK	21
>  #define CLK_GOUT_IS_SYSMMU_IS1_CLK	22
>  #define CLK_GOUT_IS_SYSREG_PCLK		23
> -#define IS_NR_CLK			24
> 
>  /* CMU_MFCMSCL */
>  #define CLK_MOUT_MFCMSCL_MFC_USER		1
> @@ -275,7 +268,6 @@
>  #define CLK_GOUT_MFCMSCL_PPMU_PCLK		13
>  #define CLK_GOUT_MFCMSCL_SYSMMU_CLK		14
>  #define CLK_GOUT_MFCMSCL_SYSREG_PCLK		15
> -#define MFCMSCL_NR_CLK				16
> 
>  /* CMU_PERI */
>  #define CLK_MOUT_PERI_BUS_USER		1
> @@ -312,7 +304,6 @@
>  #define CLK_GOUT_UART_PCLK		32
>  #define CLK_GOUT_WDT0_PCLK		33
>  #define CLK_GOUT_WDT1_PCLK		34
> -#define PERI_NR_CLK			35
> 
>  /* CMU_CORE */
>  #define CLK_MOUT_CORE_BUS_USER		1
> @@ -329,7 +320,6 @@
>  #define CLK_GOUT_SSS_PCLK		12
>  #define CLK_GOUT_GPIO_CORE_PCLK		13
>  #define CLK_GOUT_SYSREG_CORE_PCLK	14
> -#define CORE_NR_CLK			15
> 
>  /* CMU_DPU */
>  #define CLK_MOUT_DPU_USER		1
> diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h
b/include/dt-
> bindings/clock/samsung,exynosautov9.h
> index 42133af6d6b9..3065375c2d8b 100644
> --- a/include/dt-bindings/clock/samsung,exynosautov9.h
> +++ b/include/dt-bindings/clock/samsung,exynosautov9.h
> @@ -166,16 +166,12 @@
>  #define GOUT_CLKCMU_PERIC1_IP		248
>  #define GOUT_CLKCMU_PERIS_BUS		249
> 
> -#define TOP_NR_CLK			250
> -
>  /* CMU_BUSMC */
>  #define CLK_MOUT_BUSMC_BUS_USER		1
>  #define CLK_DOUT_BUSMC_BUSP		2
>  #define CLK_GOUT_BUSMC_PDMA0_PCLK	3
>  #define CLK_GOUT_BUSMC_SPDMA_PCLK	4
> 
> -#define BUSMC_NR_CLK			5
> -
>  /* CMU_CORE */
>  #define CLK_MOUT_CORE_BUS_USER		1
>  #define CLK_DOUT_CORE_BUSP		2
> @@ -183,8 +179,6 @@
>  #define CLK_GOUT_CORE_CCI_PCLK		4
>  #define CLK_GOUT_CORE_CMU_CORE_PCLK	5
> 
> -#define CORE_NR_CLK			6
> -
>  /* CMU_FSYS0 */
>  #define CLK_MOUT_FSYS0_BUS_USER		1
>  #define CLK_MOUT_FSYS0_PCIE_USER	2
> @@ -226,8 +220,6 @@
>  #define CLK_GOUT_FSYS0_PCIE_GEN3A_4L_CLK		35
>  #define CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK		36
> 
> -#define FSYS0_NR_CLK			37
> -
>  /* CMU_FSYS1 */
>  #define FOUT_MMC_PLL				1
> 
> @@ -251,8 +243,6 @@
>  #define CLK_GOUT_FSYS1_USB30_0_ACLK		17
>  #define CLK_GOUT_FSYS1_USB30_1_ACLK		18
> 
> -#define FSYS1_NR_CLK				19
> -
>  /* CMU_FSYS2 */
>  #define CLK_MOUT_FSYS2_BUS_USER		1
>  #define CLK_MOUT_FSYS2_UFS_EMBD_USER	2
> @@ -262,8 +252,6 @@
>  #define CLK_GOUT_FSYS2_UFS_EMBD1_ACLK	6
>  #define CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO	7
> 
> -#define FSYS2_NR_CLK			8
> -
>  /* CMU_PERIC0 */
>  #define CLK_MOUT_PERIC0_BUS_USER	1
>  #define CLK_MOUT_PERIC0_IP_USER		2
> @@ -308,8 +296,6 @@
>  #define CLK_GOUT_PERIC0_PCLK_10		42
>  #define CLK_GOUT_PERIC0_PCLK_11		43
> 
> -#define PERIC0_NR_CLK			44
> -
>  /* CMU_PERIC1 */
>  #define CLK_MOUT_PERIC1_BUS_USER	1
>  #define CLK_MOUT_PERIC1_IP_USER		2
> @@ -354,14 +340,10 @@
>  #define CLK_GOUT_PERIC1_PCLK_10		42
>  #define CLK_GOUT_PERIC1_PCLK_11		43
> 
> -#define PERIC1_NR_CLK			44
> -
>  /* CMU_PERIS */
>  #define CLK_MOUT_PERIS_BUS_USER		1
>  #define CLK_GOUT_SYSREG_PERIS_PCLK	2
>  #define CLK_GOUT_WDT_CLUSTER0		3
>  #define CLK_GOUT_WDT_CLUSTER1		4
> 
> -#define PERIS_NR_CLK			5
> -
>  #endif /* _DT_BINDINGS_CLOCK_EXYNOSAUTOV9_H */
> --
> 2.34.1

Re: [PATCH 00/11] clk: samsung: remove number of clocks from bindings

[Chanwoo Choi]

Hi,

On 23. 8. 8. 17:27, Krzysztof Kozlowski wrote:
> Hi,
> 
> No dependencies, patches can be taken in one set via my clk tree.
> 
> Best regards,
> Krzysztof
> 
> Krzysztof Kozlowski (11):
>   clk: samsung: exynos3250: do not define number of clocks in bindings
>   clk: samsung: exynos4: do not define number of clocks in bindings
>   clk: samsung: exynos5250: do not define number of clocks in bindings
>   clk: samsung: exynos5260: do not define number of clocks in bindings
>   clk: samsung: exynos5410: do not define number of clocks in bindings
>   clk: samsung: exynos5420: do not define number of clocks in bindings
>   clk: samsung: exynos5433: do not define number of clocks in bindings
>   clk: samsung: exynos7885: do not define number of clocks in bindings
>   clk: samsung: exynos850: do not define number of clocks in bindings
>   clk: samsung: exynoautov9: do not define number of clocks in bindings
>   dt-bindings: clock: samsung: remove define with number of clocks
> 
>  drivers/clk/samsung/clk-exynos3250.c          | 11 +++-
>  drivers/clk/samsung/clk-exynos4.c             |  5 +-
>  drivers/clk/samsung/clk-exynos4412-isp.c      |  5 +-
>  drivers/clk/samsung/clk-exynos5250.c          |  5 +-
>  drivers/clk/samsung/clk-exynos5260.c          | 41 ++++++++----
>  drivers/clk/samsung/clk-exynos5410.c          |  5 +-
>  drivers/clk/samsung/clk-exynos5420.c          |  5 +-
>  drivers/clk/samsung/clk-exynos5433.c          | 65 +++++++++++++------
>  drivers/clk/samsung/clk-exynos7885.c          | 14 ++--
>  drivers/clk/samsung/clk-exynos850.c           | 35 ++++++----
>  drivers/clk/samsung/clk-exynosautov9.c        | 29 ++++++---
>  include/dt-bindings/clock/exynos3250.h        | 18 -----
>  include/dt-bindings/clock/exynos4.h           |  5 --
>  include/dt-bindings/clock/exynos5250.h        |  3 -
>  include/dt-bindings/clock/exynos5260-clk.h    | 25 -------
>  include/dt-bindings/clock/exynos5410.h        |  2 -
>  include/dt-bindings/clock/exynos5420.h        |  3 -
>  include/dt-bindings/clock/exynos5433.h        | 42 ------------
>  include/dt-bindings/clock/exynos7885.h        |  4 --
>  include/dt-bindings/clock/exynos850.h         | 10 ---
>  .../dt-bindings/clock/samsung,exynosautov9.h  | 18 -----
>  21 files changed, 154 insertions(+), 196 deletions(-)
> 

There are no behavior changes.
It remove the unused clock id from binding header file.
I will remove the confusion of user of clock. Thanks.

Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>

-- 
Best Regards,
Samsung Electronics
Chanwoo Choi

Re: [PATCH 00/11] clk: samsung: remove number of clocks from bindings

[Krzysztof Kozlowski]

On Tue, 08 Aug 2023 10:27:27 +0200, Krzysztof Kozlowski wrote:
> No dependencies, patches can be taken in one set via my clk tree.
> 
> Best regards,
> Krzysztof
> 
> Krzysztof Kozlowski (11):
>   clk: samsung: exynos3250: do not define number of clocks in bindings
>   clk: samsung: exynos4: do not define number of clocks in bindings
>   clk: samsung: exynos5250: do not define number of clocks in bindings
>   clk: samsung: exynos5260: do not define number of clocks in bindings
>   clk: samsung: exynos5410: do not define number of clocks in bindings
>   clk: samsung: exynos5420: do not define number of clocks in bindings
>   clk: samsung: exynos5433: do not define number of clocks in bindings
>   clk: samsung: exynos7885: do not define number of clocks in bindings
>   clk: samsung: exynos850: do not define number of clocks in bindings
>   clk: samsung: exynoautov9: do not define number of clocks in bindings
>   dt-bindings: clock: samsung: remove define with number of clocks
> 
> [...]

Applied, thanks!

Fixed commit msg language as suggested by Conor.

[01/11] clk: samsung: exynos3250: do not define number of clocks in bindings
        https://git.kernel.org/krzk/linux/c/ec01691c9c631ae465ff0438172738d68bca828b
[02/11] clk: samsung: exynos4: do not define number of clocks in bindings
        https://git.kernel.org/krzk/linux/c/826951d90658199a1a1098e823b6205aaea09b0f
[03/11] clk: samsung: exynos5250: do not define number of clocks in bindings
        https://git.kernel.org/krzk/linux/c/835dc5ac296073b9ca3a2fda86568bb1b9377dee
[04/11] clk: samsung: exynos5260: do not define number of clocks in bindings
        https://git.kernel.org/krzk/linux/c/727d0f0640755eb6e41725d63a506d510078fa8f
[05/11] clk: samsung: exynos5410: do not define number of clocks in bindings
        https://git.kernel.org/krzk/linux/c/678417694b8ec22d31d7605352196ffce9bfe128
[06/11] clk: samsung: exynos5420: do not define number of clocks in bindings
        https://git.kernel.org/krzk/linux/c/62eef444cf300ea8a5498a98bfcfd6eb0e53dd3e
[07/11] clk: samsung: exynos5433: do not define number of clocks in bindings
        https://git.kernel.org/krzk/linux/c/6a44298ddbdde13bc7d84168bd4d256521aef439
[08/11] clk: samsung: exynos7885: do not define number of clocks in bindings
        https://git.kernel.org/krzk/linux/c/ef4923c8e0523d83b7cd4918760e03b03b2b08ad
[09/11] clk: samsung: exynos850: do not define number of clocks in bindings
        https://git.kernel.org/krzk/linux/c/56d62cd46dee861080e2484e1bdcc9f892add060
[10/11] clk: samsung: exynoautov9: do not define number of clocks in bindings
        https://git.kernel.org/krzk/linux/c/901a0c690f547dbe24fd599e7fc58d7cbf69599b
[11/11] dt-bindings: clock: samsung: remove define with number of clocks
        https://git.kernel.org/krzk/linux/c/b3f9581affb03ed28ff1905b649e66904f29b9e4

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>