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Tue, 17 Jun 2025 17:10:19 +0000 (GMT) From: "Pritam Manohar Sutar" To: "'Neil Armstrong'" , , , , , , , , , , , , Cc: , , , , , , , , , In-Reply-To: <9455a4e1-6352-4832-ac9f-2816f889c3a4@linaro.org> Subject: RE: [PATCH v3 9/9] arm64: dts: exynos: ExynosAutov920: add USB and USB SS combo phy nodes Date: Tue, 17 Jun 2025 22:40:18 +0530 Message-ID: <000001dbdfaa$b605f640$2211e2c0$@samsung.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQNTkACKxnsdZBPuyPiYuNftoBZF1gGRKuf5ApVTYEcCparjMbDhz82w Content-Language: en-in X-CMS-MailID: 20250617171023epcas5p3e6e775a8c375edeca1ef9dd0ee905a50 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-542,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250613055106epcas5p46a2e5e2d6f0e8811644643f6282fd9ca References: <20250613055613.866909-1-pritam.sutar@samsung.com> <20250613055613.866909-10-pritam.sutar@samsung.com> <9455a4e1-6352-4832-ac9f-2816f889c3a4@linaro.org> Hi Neil,=20 > -----Original Message----- > From: neil.armstrong=40linaro.org > Sent: 13 June 2025 02:42 PM > To: Pritam Manohar Sutar ; vkoul=40kernel.org= ; > kishon=40kernel.org; robh=40kernel.org; krzk+dt=40kernel.org; > conor+dt=40kernel.org; alim.akhtar=40samsung.com; andre.draszik=40linaro.= org; > peter.griffin=40linaro.org; kauschluss=40disroot.org; > ivo.ivanov.ivanov1=40gmail.com; m.szyprowski=40samsung.com; > s.nawrocki=40samsung.com > Cc: linux-phy=40lists.infradead.org; devicetree=40vger.kernel.org; linux- > kernel=40vger.kernel.org; linux-arm-kernel=40lists.infradead.org; linux- > samsung-soc=40vger.kernel.org; rosa.pila=40samsung.com; > dev.tailor=40samsung.com; faraz.ata=40samsung.com; > muhammed.ali=40samsung.com; selvarasu.g=40samsung.com > Subject: Re: =5BPATCH v3 9/9=5D arm64: dts: exynos: ExynosAutov920: add U= SB > and USB SS combo phy nodes >=20 > On 13/06/2025 07:56, Pritam Manohar Sutar wrote: > > Update the USB 3.1 DRD controller and USB31DRD phy nodes to support SS > > combo phy for this soc. > > > > The USB 3.1 DRD controller has the following features: > > * DWC3 compatible > > * compliant with both USB device 3.1 and USB device 2.0 standards > > * compliant with USB host 3.1 and USB host 2.0 standards > > * supports USB device 3.1 and USB device 2.0 interfaces > > * supports USB host 3.1 and USB host 2.0 interfaces > > * full-speed (12 Mbps) and high-speed (480 Mbps) modes with USB device > > 2.0 interface > > * super-speed (5 Gbps) mode with USB device 3.1 Gen1 interface > > * super-speed plus (10 Gbps) mode with USB device 3.1 Gen2 interface > > * single USB port which can be used for USB 3.1 or USB 2.0 > > * on-chip USB PHY transceiver > > * supports up to 16 bi-directional endpoints > > * compliant with xHCI 1.1 specification > > > > USB3.1 SSP+(10Gbps) is supported in this commit and SS phy in combo > > phy only supports PIPE3 interface and it is added in index 0 of SS phy. > > UTMI+ and PIPE3 PHY interfaces are specified in =22phys=22 property, > > UTMI+ (index 0 HS phy) and PIPE3 (index 0 SS phy). > > > > Signed-off-by: Pritam Manohar Sutar > > --- > > .../arm64/boot/dts/exynos/exynosautov920-sadk.dts =7C 4 ++++ > > arch/arm64/boot/dts/exynos/exynosautov920.dtsi =7C 15 > +++++++++++++-- > > 2 files changed, 17 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts > > b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts > > index a21386bd9af3..40588f7c9998 100644 > > --- a/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts > > +++ b/arch/arm64/boot/dts/exynos/exynosautov920-sadk.dts > > =40=40 -88,6 +88,10 =40=40 &xtcxo =7B > > =7D; > > > > /* usb */ > > +&usbdrd31_ssphy =7B > > + status =3D =22okay=22; > > +=7D; > > + > > &usbdrd31_hsphy =7B > > status =3D =22okay=22; > > =7D; > > diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > > b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > > index 4efc005cae80..5ee7fad346b9 100644 > > --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > > +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > > =40=40 -1048,6 +1048,17 =40=40 pinctrl_hsi1: pinctrl=4016450000 =7B > > interrupts =3D ; > > =7D; > > > > + usbdrd31_ssphy: phy=4016480000 =7B > > + compatible =3D =22samsung,exynosautov920-usb31drd- > ssphy=22; > > + reg =3D <0x16480000 0x0200>; > > + clocks =3D <&cmu_hsi1 CLK_MOUT_HSI1_NOC_USER>, > > + <&cmu_hsi1 CLK_MOUT_HSI1_USBDRD>; > > + clock-names =3D =22phy=22, =22ref=22; > > + =23phy-cells =3D <1>; > > + samsung,pmu-syscon =3D <&pmu_system_controller>; > > + status =3D =22disabled=22; > > + =7D; > > + > > usbdrd31_hsphy: phy=4016490000 =7B > > compatible =3D =22samsung,exynosautov920-usbdrd- > hsphy=22; > > reg =3D <0x16490000 0x0200>; > > =40=40 -1109,8 +1120,8 =40=40 usbdrd31_dwc3: usb=400 =7B > > <&cmu_hsi1 > CLK_MOUT_HSI1_USBDRD>; > > clock-names =3D =22ref=22, =22susp_clk=22; > > interrupts =3D IRQ_TYPE_LEVEL_HIGH>; > > - phys =3D <&usbdrd31_hsphy 0>; > > - phy-names =3D =22usb2-phy=22; > > + phys =3D <&usbdrd31_hsphy 0>, > <&usbdrd31_ssphy 0>; > > + phy-names =3D =22usb2-phy=22, =22usb3-phy=22; > > snps,has-lpm-erratum; > > snps,dis_u2_susphy_quirk; > > snps,dis_u3_susphy_quirk; >=20 > I think at least patch 6 & 9 should be squashed. >=20 Patch 6 and 9 are posted to add support for HS and SS phys in combo phy sep= arately. We will squash them in next version of patch-set (v4).=20 > Neil Thank you. Regards, Pritam