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Mon, 1 Sep 2025 03:33:53 +0000 (GMT) From: "Ravi Patel" To: "'Krzysztof Kozlowski'" Cc: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , In-Reply-To: <20250829-attentive-watchful-guan-b79ccc@kuoka> Subject: RE: [PATCH v3 08/10] arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support Date: Mon, 1 Sep 2025 09:03:52 +0530 Message-ID: <000001dc1af1$4026d700$c0748500$@samsung.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQHHo9j0Rv1rvZf0N1R8AXn4x9PYUAJmRP9VAu8V1FcBMgRwRbRyXiFg Content-Language: en-in X-CMS-MailID: 20250901033358epcas5p155659ad43787629cdd3221f359b8a72a X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250825120735epcas5p3c86b9db5f17c0938f1d53ef6014ab342 References: <20250825114436.46882-1-ravi.patel@samsung.com> <20250825114436.46882-9-ravi.patel@samsung.com> <20250829-attentive-watchful-guan-b79ccc@kuoka> > -----Original Message----- > From: Krzysztof Kozlowski > Sent: 29 August 2025 13:26 ... > Subject: Re: [PATCH v3 08/10] arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support > > On Mon, Aug 25, 2025 at 05:14:34PM +0530, Ravi Patel wrote: > > config ARCH_AXIADO > > bool "Axiado SoC Family" > > select GPIOLIB > > diff --git a/arch/arm64/boot/dts/exynos/Makefile b/arch/arm64/boot/dts/exynos/Makefile > > index bdb9e9813e50..bcca63136557 100644 > > --- a/arch/arm64/boot/dts/exynos/Makefile > > +++ b/arch/arm64/boot/dts/exynos/Makefile > > @@ -1,4 +1,5 @@ > > # SPDX-License-Identifier: GPL-2.0 > > +subdir-y += axis > > subdir-y += google > > > > dtb-$(CONFIG_ARCH_EXYNOS) += \ > > diff --git a/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h > > new file mode 100644 > > index 000000000000..70bd1dcac85e > > --- /dev/null > > +++ b/arch/arm64/boot/dts/exynos/axis/artpec-pinctrl.h > > @@ -0,0 +1,36 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > Does not match rest of licenses. > > > +/* > > + * Axis ARTPEC-8 SoC device tree pinctrl constants > > + * > > + * Copyright (c) 2025 Samsung Electronics Co., Ltd. > > + * https://www.samsung.com > > + * Copyright (c) 2025 Axis Communications AB. > > + * https://www.axis.com > > + */ > > + > > +#ifndef __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ > > +#define __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ > > + > > +#define ARTPEC_PIN_PULL_NONE 0 ... > > +#define ARTPEC_PIN_DRV_SR6 0xd > > + > > +#endif /* __DTS_ARM64_SAMSUNG_EXYNOS_AXIS_ARTPEC_PINCTRL_H__ */ > > diff --git a/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi > > new file mode 100644 > > index 000000000000..8d239a70f1b4 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/exynos/axis/artpec8-pinctrl.dtsi > > @@ -0,0 +1,120 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > This is Dual license, so why pincltr header is not? Thanks for the review. I will update the Dual license in pinctrl header in the next version. Thanks, Ravi > > Best regards, > Krzysztof