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Mon, 8 Jul 2024 11:05:21 +0000 (GMT) Received: from epsmgmc1p1new.samsung.com (unknown [182.195.42.40]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20240708110521epsmtrp1e1b21bfdbf88dda5bf258d4dcd0bab66~gOBVCOb4q2572525725epsmtrp1Y; Mon, 8 Jul 2024 11:05:21 +0000 (GMT) X-AuditID: b6c32a4a-e57f970000002705-52-668bc7f27dc8 Received: from epsmtip2.samsung.com ( [182.195.34.31]) by epsmgmc1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id E6.37.07412.1F7CB866; Mon, 8 Jul 2024 20:05:21 +0900 (KST) Received: from INBRO002756 (unknown [107.122.12.5]) by epsmtip2.samsung.com (KnoxPortal) with ESMTPA id 20240708110519epsmtip215208df90841a394d1b63b8a70720e50~gOBTJektR1337213372epsmtip2H; Mon, 8 Jul 2024 11:05:19 +0000 (GMT) From: "Alim Akhtar" To: "'Sunyeal Hong'" , "'Krzysztof Kozlowski'" , "'Sylwester Nawrocki'" , "'Chanwoo Choi'" , "'Michael Turquette'" , "'Stephen Boyd'" , "'Rob Herring'" , "'Conor Dooley'" Cc: , , , , In-Reply-To: <20240707231331.3433340-3-sunyeal.hong@samsung.com> Subject: RE: [PATCH v2 2/4] arm64: dts: exynos: add initial CMU clock nodes in Exynos Auto v920 Date: Mon, 8 Jul 2024 16:35:18 +0530 Message-ID: <000101dad126$b964e2d0$2c2ea870$@samsung.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQJHtUpDsgLCeLIQdS8546uqgvLWdQIAh4UhAdGvMNqw9FDbkA== Content-Language: en-us X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrKJsWRmVeSWpSXmKPExsWy7bCmpu6n491pBqs/WFus2XuOyeL6l+es FvOPnGO1OH9+A7vFpsfXWC0+9txjtbi8aw6bxYzz+5gsLp5ytfi/Zwe7xeE37awW/65tZLFo WraeyYHX4/2NVnaPTas62Tw2L6n36NuyitHj8ya5ANaobJuM1MSU1CKF1Lzk/JTMvHRbJe/g eOd4UzMDQ11DSwtzJYW8xNxUWyUXnwBdt8wcoBOVFMoSc0qBQgGJxcVK+nY2RfmlJakKGfnF JbZKqQUpOQUmBXrFibnFpXnpenmpJVaGBgZGpkCFCdkZb79pFSyWr1j86yVbA+MKyS5GTg4J AROJ7XOusncxcnEICexmlPjz5g4jhPOJUaJ16X4mCOcbo8Tta6uZYVqePDsEVbWXUeLttq9s EM4LRonpy96BVbEJ6ErsWNzGBmKLCNxjkvi41xykiFlgHaPE5plHgDZycHAKOEjc2aoJUiMs kCjx+ckEJpAwi4CKxNZfYGN4BSwl7u3bzAJhC0qcnPkEzGYW0JZYtvA11EEKEj+fLmOFWOUk sb/jCBNEjbjEy6NHwH6TEDjAIfFu1Q4WiAYXidtbX7JB2MISr45vYYewpSRe9rdB2dkSxy/O gqqpkOhu/QgVt5fY+egmC8idzAKaEut36UPs4pPo/f0E7HwJAV6JjjYhiGpVieZ3V6G2SktM 7O5mhbA9JL5fb2CfwKg4C8lns5B8NgvJB7MQli1gZFnFKJlaUJybnlpsWmCUl1oOj+7k/NxN jOD0q+W1g/Hhgw96hxiZOBgPMUpwMCuJ8J5+3J4mxJuSWFmVWpQfX1Sak1p8iNEUGNoTmaVE k/OBGSCvJN7QxNLAxMzMzMTS2MxQSZz3devcFCGB9MSS1OzU1ILUIpg+Jg5OqQam2Gv6uy26 bz/+s+ZqgNRpQ5Gnq13VIr2eJ2/dVCT6vm1aptSt98UfG6LWSTfeu9d38x2v5Of7D97f+mo/ XavYvu3nsgRHY9nkquaNJs+0n5srb3mUpzrVW4F36YGuJcdSRde/Xe78gJOtasu/uvef4nmr b096Y3JKteViv2vxJ7sIlyKme09rGJ4KBjVo7dj3uFPG6uV3zeq19bXOnKycXZwfbdakf36X usVacrXd28wpU2f9XOGWsnFNxN9wbt7Xp8J/3Uy61XwoY04ya5J/X0WhZ6Jjv4TRldgIhRf7 ZrH8YK+7zVuxfdqW888SVhisP963vXNNh/7e3DufGD7FWfdw9v/uCveVztr1fmamEktxRqKh FnNRcSIAAWQtd0gEAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprHIsWRmVeSWpSXmKPExsWy7bCSvO7H491pBhPeS1ms2XuOyeL6l+es FvOPnGO1OH9+A7vFpsfXWC0+9txjtbi8aw6bxYzz+5gsLp5ytfi/Zwe7xeE37awW/65tZLFo WraeyYHX4/2NVnaPTas62Tw2L6n36NuyitHj8ya5ANYoLpuU1JzMstQifbsErozL7etZCq7J Vjw7/pO5gfGmeBcjJ4eEgInEk2eHGLsYuTiEBHYzSmyY/oYNIiEtcX3jBHYIW1hi5b/n7BBF zxglbh/bBVbEJqArsWNxG5gtIvCESWLr4WiQImaBTYwS53bfBEsICRxllHi4PaOLkYODU8BB 4s5WTZCwsEC8xNtH75hBwiwCKhJbfzGDhHkFLCXu7dvMAmELSpyc+QTMZhbQlnh68ymcvWzh a2aI2xQkfj5dxgpxgpPE/o4jTBA14hIvjx5hn8AoPAvJqFlIRs1CMmoWkpYFjCyrGCVTC4pz 03OTDQsM81LL9YoTc4tL89L1kvNzNzGCo1BLYwfjvfn/9A4xMnEwHmKU4GBWEuE9/bg9TYg3 JbGyKrUoP76oNCe1+BCjNAeLkjiv4YzZKUIC6YklqdmpqQWpRTBZJg5OqQamgoObauP+fjgv PUfi/zutSMdvwdNVW0/vkNmhL+6mGLVsf2xzWf7il19qlnbfnn41dfst8dXP2BLYvB6xZSZu MYgLSFmcfed29sWYt49+Tphvol6Y+dnik/C0/2sWnHbRntT69M7nJXfvb1xpsG0Ng7ZDG+sO VqUVR5UX+qta7z0oul9xt9fLb4xVs6XVP+U8nsBodPbR56UZmw/ZSZvNVzRs6v7onGBqVdZk 0um9w/jVMiZ5/iwOoQ1esZt/dpydmdNQVTI7pFsiR+6odfQh/8itzmum5+8TWm+2svuQj3JG mKSs8OV9Z2cd2H+uatLML2/rU3bzPXzVfr6HtYbZ/v6Dq3sn6jzkr3Zenhx3UImlOCPRUIu5 qDgRAGHeitMxAwAA X-CMS-MailID: 20240708110521epcas5p4a58dda213051749c1b402db30c6545a9 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20240707231445epcas2p2cf78684e3cbcf8ed914a0d8e52115216 References: <20240707231331.3433340-1-sunyeal.hong@samsung.com> <20240707231331.3433340-3-sunyeal.hong@samsung.com> > -----Original Message----- > From: Sunyeal Hong > Sent: Monday, July 8, 2024 4:43 AM > To: Krzysztof Kozlowski ; Sylwester Nawrocki > ; Chanwoo Choi ; > Alim Akhtar ; Michael Turquette > ; Stephen Boyd ; Rob > Herring ; Conor Dooley > Cc: linux-samsung-soc=40vger.kernel.org; linux-clk=40vger.kernel.org; > devicetree=40vger.kernel.org; linux-arm-kernel=40lists.infradead.org; lin= ux- > kernel=40vger.kernel.org; Sunyeal Hong > Subject: =5BPATCH v2 2/4=5D arm64: dts: exynos: add initial CMU clock nod= es in > Exynos Auto v920 >=20 > Add cmu_top, cmu_peric0 clock nodes and > switch USI clocks instead of dummy fixed-rate-clock. >=20 > Signed-off-by: Sunyeal Hong > --- > .../arm64/boot/dts/exynos/exynosautov920.dtsi =7C 40 +++++++++++++------ > 1 file changed, 27 insertions(+), 13 deletions(-) >=20 > diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > index c1c8566d74f5..54fc32074379 100644 > --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi > =40=40 -6,6 +6,7 =40=40 > * > */ >=20 > +=23include > =23include > =23include >=20 > =40=40 -38,17 +39,6 =40=40 xtcxo: clock =7B > clock-output-names =3D =22oscclk=22; > =7D; >=20 > - /* > - * FIXME: Keep the stub clock for serial driver, until proper clock > - * driver is implemented. > - */ > - clock_usi: clock-usi =7B > - compatible =3D =22fixed-clock=22; > - =23clock-cells =3D <0>; > - clock-frequency =3D <200000000>; > - clock-output-names =3D =22usi=22; > - =7D; > - > cpus: cpus =7B > =23address-cells =3D <2>; > =23size-cells =3D <0>; > =40=40 -182,6 +172,28 =40=40 chipid=4010000000 =7B > reg =3D <0x10000000 0x24>; > =7D; >=20 > + cmu_peric0: clock-controller=4010800000 =7B > + compatible =3D =22samsung,exynosautov920-cmu- > peric0=22; > + reg =3D <0x10800000 0x8000>; Please cross check the size of the register range, this looks to be more th= en what is needed.=20 > + =23clock-cells =3D <1>; > + > + clocks =3D <&xtcxo>, > + <&cmu_top DOUT_CLKCMU_PERIC0_NOC>, > + <&cmu_top DOUT_CLKCMU_PERIC0_IP>; > + clock-names =3D =22oscclk=22, > + =22noc=22, > + =22ip=22; > + =7D; > + > + cmu_top: clock-controller=4011000000 =7B > + compatible =3D =22samsung,exynosautov920-cmu-top=22; > + reg =3D <0x11000000 0x8000>; > + =23clock-cells =3D <1>; > + > + clocks =3D <&xtcxo>; > + clock-names =3D =22oscclk=22; > + =7D; > + > gic: interrupt-controller=4010400000 =7B > compatible =3D =22arm,gic-v3=22; > =23interrupt-cells =3D <3>; > =40=40 -213,7 +225,8 =40=40 usi_0: usi=40108800c0 =7B > =23address-cells =3D <1>; > =23size-cells =3D <1>; > ranges; > - clocks =3D <&clock_usi>, <&clock_usi>; > + clocks =3D <&cmu_peric0 > CLK_MOUT_PERIC0_NOC_USER>, > + <&cmu_peric0 > CLK_DOUT_PERIC0_USI00_USI>; > clock-names =3D =22pclk=22, =22ipclk=22; > status =3D =22disabled=22; >=20 > =40=40 -224,7 +237,8 =40=40 serial_0: serial=4010880000 =7B > interrupts =3D IRQ_TYPE_LEVEL_HIGH>; > pinctrl-names =3D =22default=22; > pinctrl-0 =3D <&uart0_bus>; > - clocks =3D <&clock_usi>, <&clock_usi>; > + clocks =3D <&cmu_peric0 > CLK_MOUT_PERIC0_NOC_USER>, > + <&cmu_peric0 > CLK_DOUT_PERIC0_USI00_USI>; > clock-names =3D =22uart=22, =22clk_uart_baud0=22; > samsung,uart-fifosize =3D <256>; > status =3D =22disabled=22; > -- > 2.45.2