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Fri, 4 Jul 2025 13:09:13 +0000 (GMT) From: "Pankaj Dubey" To: "'Krzysztof Kozlowski'" , "'Shradha Todi'" , "'Rob Herring'" Cc: , , , , , , , , , , , , , , , , , , , In-Reply-To: <5ea33054-8a08-4bb3-81e7-d832c53979dc@kernel.org> Subject: RE: [PATCH v2 07/10] dt-bindings: phy: Add PHY bindings support for FSD SoC Date: Fri, 4 Jul 2025 18:39:12 +0530 Message-ID: <000101dbece4$d8694d80$893be880$@samsung.com> Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQFUClgbainc6hQuKSBO0V8ttZVgkwGg1JXJAfs/ltABn1f9rAD4JQ8bAeFf3fQB1zUu0wGsyVLstNTsxXA= Content-Language: en-us X-CMS-MailID: 20250704130916epcas5p2ccff0f947268712a35e5e80977bf5806 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" CMS-TYPE: 105P cpgsPolicy: CPGSC10-541,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250625165319epcas5p3721c19f6e6b482438c62dd1ef784de03 References: <20250625165229.3458-1-shradha.t@samsung.com> <20250625165229.3458-8-shradha.t@samsung.com> <20250627211721.GA153863-robh@kernel.org> <02af01dbea78$24f01310$6ed03930$@samsung.com> <02bf01dbea8c$fc835cb0$f58a1610$@samsung.com> <5ea33054-8a08-4bb3-81e7-d832c53979dc@kernel.org> > -----Original Message----- > From: Krzysztof Kozlowski > Sent: Thursday, July 3, 2025 1:48 AM > To: Shradha Todi ; 'Rob Herring' > > Cc: linux-pci=40vger.kernel.org; devicetree=40vger.kernel.org; linux-arm- > kernel=40lists.infradead.org; linux-samsung-soc=40vger.kernel.org; linux- > kernel=40vger.kernel.org; linux-phy=40lists.infradead.org; linux-fsd=40te= sla.com; > mani=40kernel.org; lpieralisi=40kernel.org; kw=40linux.com; > bhelgaas=40google.com; jingoohan1=40gmail.com; krzk+dt=40kernel.org; > conor+dt=40kernel.org; alim.akhtar=40samsung.com; vkoul=40kernel.org; > kishon=40kernel.org; arnd=40arndb.de; m.szyprowski=40samsung.com; > jh80.chung=40samsung.com; pankaj.dubey=40samsung.com > Subject: Re: =5BPATCH v2 07/10=5D dt-bindings: phy: Add PHY bindings supp= ort for > FSD SoC >=20 > On 01/07/2025 15:35, Shradha Todi wrote: > >>> does not support auto adaptation so we need to tune the PHYs > >>> according to the use case (considering channel loss, etc). This is > >>> why we > >> > >> So not same? Decide. Either it is same or not, cannot be both. > >> > >> If you mean that some wiring is different on the board, then how does > >> it differ in soc thus how it is per-soc property? If these are > >> use-cases, then how is even suitable for DT? > >> > >> I use your Tesla FSD differently and then I exchange DTSI and compatib= les? > >> > >> You are no describing real problem and both binding and your > >> explanations are vague and imprecise. Binding tells nothing about it, > >> so it is example of skipping important decisions. > >> > >>> have 2 different SW PHY initialization sequence depending on the > >>> instance number. Do you think having different compatible (something > >>> like > >>> tesla,fsd-pcie-phy0 and tesla,fsd-pcie-phy1) and having phy ID as > >>> platform data is okay in this case? I actually took reference from fi= les like: > >> > >> And in different use case on same soc you are going to reverse > >> compatibles or instance IDs? > >> > > > > Even though both the PHYs are exactly identical in terms of hardware, > > they need to be programmed/initialized/configured differently. > > > > Sorry for my misuse of the word =22use-case=22. To clarify, these > > configurations will always remain the same for FSD SoC even if you use = it > differently. > > > > I will use different compatibles for them as I understand that it is > > the best option. >=20 > I still do not see the difference in hardware explained. >=20 Hi Krzysztof=20 Let me add more details and see if that makes sense to understand the inten= tion behind the current design of the PHY driver. In FSD SoC, the two PHY instances, although having identical hardware desig= n and register maps, are placed in different locations (Placement and routing) in= side the SoC and have distinct PHY-to-Controller topologies.=20 One instance is connected to two PCIe controllers, while the other is conne= cted to only one. As a result, they experience different analog environments, inclu= ding varying channel losses and noise profiles. Since these PHYs lack internal adaptation mechanisms and f/w based tuning, manual register programming is required for analog tuning, such as equaliza= tion, de-emphasis, and gain. To ensure optimal signal integrity, it is essential = to use different register values for each PHY instance, despite their identical hardware des= ign. This is because the same register values may not be suitable for both insta= nces due to their differing environments and topologies. Do let us know if this explains the intention behind separate programming s= equence for both instance of the PHY? Thanks, Pankaj Dubey > Best regards, > Krzysztof