From: "Chanho Park" <chanho61.park@samsung.com>
To: "'Krzysztof Kozlowski'" <krzysztof.kozlowski@linaro.org>,
"'Andi Shyti'" <andi@etezian.org>,
"'Mark Brown'" <broonie@kernel.org>,
"'Rob Herring'" <robh+dt@kernel.org>,
"'Krzysztof Kozlowski'" <krzysztof.kozlowski+dt@linaro.org>
Cc: "'Alim Akhtar'" <alim.akhtar@samsung.com>,
<devicetree@vger.kernel.org>, <linux-spi@vger.kernel.org>,
<linux-samsung-soc@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: RE: [PATCH 3/5] spi: s3c64xx: support custom value of internal clock divider
Date: Tue, 28 Jun 2022 10:51:52 +0900 [thread overview]
Message-ID: <000201d88a91$a33d3c60$e9b7b520$@samsung.com> (raw)
In-Reply-To: <3a7f2faa-0d42-02e6-fb1a-216be1120ff3@linaro.org>
> Subject: Re: [PATCH 3/5] spi: s3c64xx: support custom value of internal
> clock divider
>
> On 27/06/2022 08:47, Chanho Park wrote:
> > Modern exynos SoCs such as Exynos Auto v9 has different internal clock
> > divider, for example "4". To support this internal value, this adds
> > clk_div of the s3c64xx_spi_port_config and use it if it is specified.
> > Otherwise, use "2" which is the previous default value.
> >
> > Signed-off-by: Chanho Park <chanho61.park@samsung.com>
> > ---
> > drivers/spi/spi-s3c64xx.c | 23 +++++++++++++++--------
> > 1 file changed, 15 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
> > index e17c74c0d7de..dd5fc8570bce 100644
> > --- a/drivers/spi/spi-s3c64xx.c
> > +++ b/drivers/spi/spi-s3c64xx.c
> > @@ -131,6 +131,7 @@ struct s3c64xx_spi_dma_data {
> > * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS
> register.
> > * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
> > * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
> > + * @clk_div: Internal clock divider, if not specified, use 2 as the
> default.
> > * @quirks: Bitmask of known quirks
> > * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
> > * @clk_from_cmu: True, if the controller does not include a clock
> > mux and @@ -148,6 +149,7 @@ struct s3c64xx_spi_port_config {
> > int rx_lvl_offset;
> > int tx_st_done;
> > int quirks;
> > + int clk_div;
> > bool high_speed;
> > bool clk_from_cmu;
> > bool clk_ioclk;
> > @@ -620,6 +622,7 @@ static int s3c64xx_spi_config(struct
> s3c64xx_spi_driver_data *sdd)
> > void __iomem *regs = sdd->regs;
> > int ret;
> > u32 val;
> > + u32 div = sdd->port_conf->clk_div ? sdd->port_conf->clk_div : 2;
>
> I would prefer to explicitly set '2' as clk_div for existing variants.
> Such assignments in the code are usually trickier to find/read.
Make sense. It can be more clear what value is using.
I'll apply it next patchset.
Best Regards,
Chanho Park
next prev parent reply other threads:[~2022-06-28 1:51 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20220627064931epcas2p1944df2c6c54339de17e32c7116837f52@epcas2p1.samsung.com>
2022-06-27 6:47 ` [PATCH 0/5] spi support for Exynos Auto v9 SoC Chanho Park
[not found] ` <CGME20220627064931epcas2p4d90034c1fe583a3460f0e4613e83e6d0@epcas2p4.samsung.com>
2022-06-27 6:47 ` [PATCH 1/5] spi: spi-s3c64xx: increase MAX_SPI_PORTS to 12 Chanho Park
2022-06-27 9:37 ` Krzysztof Kozlowski
[not found] ` <CGME20220627064931epcas2p3052d80fd448aed36b9414e7733c251f5@epcas2p3.samsung.com>
2022-06-27 6:47 ` [PATCH 2/5] spi: s3c64xx: support loopback mode Chanho Park
2022-06-27 9:38 ` Krzysztof Kozlowski
[not found] ` <CGME20220627064931epcas2p2e1dc352f41895b294d7945c2239de362@epcas2p2.samsung.com>
2022-06-27 6:47 ` [PATCH 3/5] spi: s3c64xx: support custom value of internal clock divider Chanho Park
2022-06-27 9:40 ` Krzysztof Kozlowski
2022-06-28 1:51 ` Chanho Park [this message]
[not found] ` <CGME20220627064931epcas2p2ad75d53ceabb2b0f10dfb13f5fcb0ff4@epcas2p2.samsung.com>
2022-06-27 6:47 ` [PATCH 4/5] dt-bindings: samsung,spi: define exynosautov9 compatible Chanho Park
2022-06-27 9:41 ` Krzysztof Kozlowski
[not found] ` <CGME20220627064931epcas2p19407c5c3da3319cfb55dcb2c6d517256@epcas2p1.samsung.com>
2022-06-27 6:47 ` [PATCH 5/5] spi: s3c64xx: add spi port configuration for Exynos Auto v9 SoC Chanho Park
2022-06-27 9:46 ` Krzysztof Kozlowski
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