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From: Jingoo Han <jg1.han@samsung.com>
To: 'Murali Karicheri' <m-karicheri2@ti.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org
Cc: 'Santosh Shilimkar' <santosh.shilimkar@ti.com>,
	'Russell King' <linux@arm.linux.org.uk>,
	'Grant Likely' <grant.likely@linaro.org>,
	'Rob Herring' <robh+dt@kernel.org>,
	'Mohit Kumar' <mohit.kumar@st.com>,
	'Bjorn Helgaas' <bhelgaas@google.com>,
	'Pratyush Anand' <pratyush.anand@st.com>,
	'Richard Zhu' <r65037@freescale.com>,
	'Kishon Vijay Abraham I' <kishon@ti.com>,
	'Marek Vasut' <marex@denx.de>, 'Arnd Bergmann' <arnd@arndb.de>,
	'Pawel Moll' <pawel.moll@arm.com>,
	'Mark Rutland' <mark.rutland@arm.com>,
	'Ian Campbell' <ijc+devicetree@hellion.org.uk>,
	'Kumar Gala' <galak@codeaurora.org>,
	'Randy Dunlap' <rdunlap@infradead.org>,
	'Jingoo Han' <jg1.han@samsung.com>
Subject: Re: [PATCH v3 5/5] PCI: add PCI controller for Keystone PCIe h/w
Date: Tue, 08 Jul 2014 21:43:06 +0900	[thread overview]
Message-ID: <000f01cf9aaa$2a59a6b0$7f0cf410$%han@samsung.com> (raw)
In-Reply-To: <1404164720-11066-6-git-send-email-m-karicheri2@ti.com>

On Tuesday, July 01, 2014 6:45 AM, Murali Karicheri wrote:
> 
> Keystone PCIe controller is based on v3.65 version of the
> designware h/w. Main differences are
> 	1. No ATU support
> 	2. Legacy and MSI irq functions are implemented in
> 	   application register space
> 	3. MSI interrupts are multiplexed over 8 IRQ lines to the Host
> 	   side.
> All of the Application register space handing code are organized into
> pci-keystone-dw.c and the functions are called from pci-keystone.c
> to implement PCI controller driver. Also add necessary DT documentation
> for the driver.
> 
> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
> 
> CC: Santosh Shilimkar <santosh.shilimkar@ti.com>
> CC: Russell King <linux@arm.linux.org.uk>
> CC: Grant Likely <grant.likely@linaro.org>
> CC: Rob Herring <robh+dt@kernel.org>
> CC: Mohit Kumar <mohit.kumar@st.com>
> CC: Jingoo Han <jg1.han@samsung.com>
> CC: Bjorn Helgaas <bhelgaas@google.com>
> CC: Pratyush Anand <pratyush.anand@st.com>
> CC: Richard Zhu <r65037@freescale.com>
> CC: Kishon Vijay Abraham I <kishon@ti.com>
> CC: Marek Vasut <marex@denx.de>
> CC: Arnd Bergmann <arnd@arndb.de>
> CC: Pawel Moll <pawel.moll@arm.com>
> CC: Mark Rutland <mark.rutland@arm.com>
> CC: Ian Campbell <ijc+devicetree@hellion.org.uk>
> CC: Kumar Gala <galak@codeaurora.org>
> CC: Randy Dunlap <rdunlap@infradead.org>
> CC: Grant Likely <grant.likely@linaro.org>
> ---
>  .../devicetree/bindings/pci/pci-keystone.txt       |   69 +++
>  drivers/pci/host/Kconfig                           |    5 +
>  drivers/pci/host/Makefile                          |    1 +
>  drivers/pci/host/pci-keystone-dw.c                 |  523 ++++++++++++++++++++
>  drivers/pci/host/pci-keystone.c                    |  381 ++++++++++++++
>  drivers/pci/host/pci-keystone.h                    |   56 +++
>  6 files changed, 1035 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/pci-keystone.txt
>  create mode 100644 drivers/pci/host/pci-keystone-dw.c
>  create mode 100644 drivers/pci/host/pci-keystone.c
>  create mode 100644 drivers/pci/host/pci-keystone.h
> 

[.....]

> +
> +static int __init ks_pcie_probe(struct platform_device *pdev)
> +{
> +	struct device_node *np = pdev->dev.of_node;
> +	struct device *dev = &pdev->dev;
> +	struct keystone_pcie *ks_pcie;
> +	struct pcie_port *pp;
> +	struct resource *res;
> +	void __iomem *reg_p;
> +	struct phy *phy;
> +	int ret = 0;
> +	u32 val;
> +
> +	ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
> +				GFP_KERNEL);
> +	if (!ks_pcie) {
> +		dev_err(dev, "no memory for keystone pcie\n");
> +		return -ENOMEM;
> +	}
> +	pp = &ks_pcie->pp;
> +
> +	/* initialize SerDes Phy if present */
> +	phy = devm_phy_get(dev, "pcie-phy");
> +	if (phy)
> +		ret = phy_init(phy);

Why don't you check 'ret' value?
How about the following?

+	/* initialize SerDes Phy if present */
+	phy = devm_phy_get(dev, "pcie-phy");
+	if (!IS_ERR_OR_NULL(phy) {
+		ret = phy_init(phy);
+		if (ret <0)
+			return ret;
+	}


Best regards,
Jingoo Han

[....]

  parent reply	other threads:[~2014-07-08 12:43 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2014-06-30 21:45 [PATCH v3 0/5] Add Keystone PCIe controller driver Murali Karicheri
2014-06-30 21:45 ` [PATCH v3 1/5] PCI: designware: add rd[wr]_other_conf API Murali Karicheri
2014-07-07  4:11   ` Mohit KUMAR DCG
2014-07-07 16:53     ` Murali Karicheri
2014-07-08 12:17       ` Jingoo Han
2014-06-30 21:45 ` [PATCH v3 2/5] PCI: designware: refactor MSI code to work with v3.65 dw hardware Murali Karicheri
2014-07-07  4:17   ` Mohit KUMAR DCG
2014-07-07 16:53     ` Murali Karicheri
2014-07-08 12:20       ` Jingoo Han
2014-06-30 21:45 ` [PATCH v3 3/5] PCI: designware: refactor host init code to re-use on keystone PCI Murali Karicheri
2014-07-08 13:20   ` Murali Karicheri
2014-07-08 13:31     ` Jingoo Han
2014-06-30 21:45 ` [PATCH v3 4/5] PCI: designware: enhance dw core driver to support Keystone PCI host controller Murali Karicheri
     [not found]   ` <1404164720-11066-5-git-send-email-m-karicheri2-l0cyMroinI0@public.gmane.org>
2014-07-08 13:24     ` Murali Karicheri
2014-06-30 21:45 ` [PATCH v3 5/5] PCI: add PCI controller for Keystone PCIe h/w Murali Karicheri
2014-07-05 18:45   ` Bjorn Helgaas
2014-07-08 12:43   ` Jingoo Han [this message]
2014-07-08 13:25   ` Murali Karicheri
2014-07-05 18:23 ` [PATCH v3 0/5] Add Keystone PCIe controller driver Bjorn Helgaas
     [not found]   ` <20140705182332.GB28871-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>
2014-07-08 12:49     ` Murali Karicheri
2014-07-09 13:52 ` Santosh Shilimkar

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