From: "SanghoonBae" <sh86.bae@samsung.com>
To: "'Krzysztof Kozlowski'" <krzk@kernel.org>, <robh@kernel.org>,
<conor+dt@kernel.org>, <vkoul@kernel.org>,
<alim.akhtar@samsung.com>, <kishon@kernel.org>,
<m.szyprowski@samsung.com>, <jh80.chung@samsung.com>,
<shradha.t@samsung.com>
Cc: <krzk+dt@kernel.org>, <linux-kernel@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-samsung-soc@vger.kernel.org>,
<linux-phy@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>
Subject: RE: [PATCH 3/4] arm64: dts: ExynosAutov920: add PCIe PHY DT nodes
Date: Fri, 14 Nov 2025 15:57:18 +0900 [thread overview]
Message-ID: <001601dc5533$eb0049f0$c100ddd0$@samsung.com> (raw)
In-Reply-To: <ea85d388-c0c1-4b4a-96d6-d3f27622ed54@kernel.org>
> > + pcie_2l_phy: pcie-phy2l@161c6000{
>
>
>
> Node names should be generic. See also an explanation and list of examples
> (not exhaustive) in DT specification:
> https://protect2.fireeye.com/v1/url?k=d2bcf1f2-8d273f96-d2bd7abd-
> 000babda0201-1fe7eb4ecd262f65&q=1&e=8522e96d-f1a1-4b6b-baa9-
> 44344340469a&u=https%3A%2F%2Fdevicetree-
> specification.readthedocs.io%2Fen%2Flatest%2Fchapter2-devicetree-
> basics.html%23generic-names-recommendation
> If you cannot find a name matching your device, please check in kernel
> sources for similar cases or you can grow the spec (via pull request to DT
> spec repo).
I will rename the node referring the guideline you linked.
> Plus style issues... missing space.
Will add space before left brace.
> I would like to see also PCIe nodes somewhere, because I wonder if num-
> lanes should not be moved to PCI node (phy consumer) instead.
> Current approach feels better, but maybe it just duplicates num-lanes from
> the PCI?
As mentioned earlier, I plan to enable the PCIe nodes later.
However, I can share my prototype PCIe node that I am currently using for
PCIe driver testing:
pcie_0: pcie@163c0000 {
compatible = "samsung,exynosautov920-pcie";
gpios = <&gph0 1 0>; /* PERST */
reg = <0x163C0000 0x1000>, <0x12000000 0x20000>,
<0x2fffd000 0x2000>, <0x12600000 0x2000>;
reg-names = "elbi", "dbi", "config", "atu";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
device_type = "pci";
interrupts = <GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 444 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&xtcxo>;
clock-names = "ref_clk";
num-lanes = <1>;
num-viewport = <3>;
bus-range = <0x00 0xff>;
phys = <&pcie_0_phy>;
samsung,pcie-ch = <0>;
ranges = <0x82000000 0 0x20000000 0x20000000 0 0x1FFFD000>;
status = "disabled";
};
As you expected, num-lanes will be defined only in the PCIe node.
Please let me know if this composition of the DT nodes looks appropriate
to you.
next prev parent reply other threads:[~2025-11-14 6:57 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <CGME20250926073954epcas2p4b8bb4206e526b7d7860ed4378ed75f78@epcas2p4.samsung.com>
2025-09-26 7:39 ` [PATCH 0/4] Add support for ExynosAutov920 PCIe PHY Sanghoon Bae
[not found] ` <CGME20250926074011epcas2p438f7edb31c720c0950e9df986983f5a5@epcas2p4.samsung.com>
2025-09-26 7:39 ` [PATCH 1/4] dt-bindings: soc: samsung: exynos-sysreg: add hsi0 for ExynosAutov920 Sanghoon Bae
2025-10-07 6:28 ` Krzysztof Kozlowski
2025-11-14 5:36 ` 배상훈/Sanghoon Bae
[not found] ` <CGME20250926074017epcas2p18fb2fc616b92dc04ad9e018151c2ba29@epcas2p1.samsung.com>
2025-09-26 7:39 ` [PATCH 2/4] dt-bindings: phy: Add PCIe PHY support for ExynosAutov920 SoC Sanghoon Bae
2025-10-07 6:29 ` Krzysztof Kozlowski
2025-11-14 6:05 ` Sanghoon Bae
[not found] ` <CGME20250926074021epcas2p36a8dc02c84c9ca11e2318a1a8931d68a@epcas2p3.samsung.com>
2025-09-26 7:39 ` [PATCH 3/4] arm64: dts: ExynosAutov920: add PCIe PHY DT nodes Sanghoon Bae
2025-10-07 6:32 ` Krzysztof Kozlowski
2025-11-14 6:57 ` SanghoonBae [this message]
[not found] ` <CGME20250926074022epcas2p3aa1179b587beac076ef5942004c7d099@epcas2p3.samsung.com>
2025-09-26 7:39 ` [PATCH 4/4] phy: exynos: Add PCIe PHY support for ExynosAutov920 SoC Sanghoon Bae
[not found] ` <CGME20250926074033epcas2p371d57850f46c9ecb307f3ea8c6d4a57f@epcas2p3.samsung.com>
2025-09-26 7:39 ` [PATCH 0/4] Add support for ExynosAutov920 PCIe PHY Sanghoon Bae
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='001601dc5533$eb0049f0$c100ddd0$@samsung.com' \
--to=sh86.bae@samsung.com \
--cc=alim.akhtar@samsung.com \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=jh80.chung@samsung.com \
--cc=kishon@kernel.org \
--cc=krzk+dt@kernel.org \
--cc=krzk@kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=linux-samsung-soc@vger.kernel.org \
--cc=m.szyprowski@samsung.com \
--cc=robh@kernel.org \
--cc=shradha.t@samsung.com \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).