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Mon, 29 Nov 2021 14:38:27 +0100 Subject: Re: [PATCH v2 1/3] ARM: dts: stm32: Enable LVDS panel on i.Core STM32MP1 EDIMM2.2 To: Jagan Teki , Rob Herring , Maxime Coquelin CC: , , , , Matteo Lisi References: <20211112053856.18412-1-jagan@amarulasolutions.com> From: Alexandre TORGUE Message-ID: <00340d22-c2ac-4de7-7a7f-32ad89eaa235@foss.st.com> Date: Mon, 29 Nov 2021 14:38:26 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: <20211112053856.18412-1-jagan@amarulasolutions.com> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Originating-IP: [10.75.127.47] X-ClientProxiedBy: SFHDAG2NODE2.st.com (10.75.127.5) To SFHDAG2NODE2.st.com (10.75.127.5) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.790,Hydra:6.0.425,FMLib:17.0.607.475 definitions=2021-11-29_08,2021-11-28_01,2020-04-07_01 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Jagan On 11/12/21 6:38 AM, Jagan Teki wrote: > Engicam i.Core STM32MP1 EDIMM2.2 Starter Kit has plugged with > 7" LVDS panel. > > Engicam i.Core STM32MP1 SoM has SN65DSI84 DSI to LVDS bridge. > > This patch adds a display pipeline to connect DSI to SN65DSI84 > to 7" LVDS panel. > > Signed-off-by: Jagan Teki > --- > Changes for v2: > - none > > .../stm32mp157a-icore-stm32mp1-edimm2.2.dts | 85 +++++++++++++++++++ > 1 file changed, 85 insertions(+) > > diff --git a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts > index ec9f1d1cd50f..d80b4415e761 100644 > --- a/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts > +++ b/arch/arm/boot/dts/stm32mp157a-icore-stm32mp1-edimm2.2.dts > @@ -24,6 +24,91 @@ aliases { > chosen { > stdout-path = "serial0:115200n8"; > }; > + > + backlight: backlight { > + compatible = "gpio-backlight"; > + gpios = <&gpiod 13 GPIO_ACTIVE_HIGH>; > + default-on; > + }; > + > + panel { > + compatible = "yes-optoelectronics,ytc700tlag-05-201c"; > + backlight = <&backlight>; > + power-supply = <&v3v3>; > + > + port { > + panel_out_bridge: endpoint { > + remote-endpoint = <&bridge_out_panel>; > + }; > + }; > + }; > +}; > + > +&dsi { > + status = "okay"; > + phy-dsi-supply = <®18>; > + > + ports { > + port@0 { > + reg = <0>; > + dsi_in_ltdc: endpoint { > + remote-endpoint = <<dc_out_dsi>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dsi_out_bridge: endpoint { > + remote-endpoint = <&bridge_in_dsi>; > + }; > + }; > + }; > +}; > + > +&i2c6 { > + i2c-scl-falling-time-ns = <20>; > + i2c-scl-rising-time-ns = <185>; > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <&i2c6_pins_a>; > + pinctrl-1 = <&i2c6_sleep_pins_a>; > + status = "okay"; > + > + bridge@2c { > + compatible = "ti,sn65dsi84"; Running dtb_check I observe following issue: bridge@2c: ports:port@0:endpoint:data-lanes:0:0: 1 was expected From schema: /Documentation/devicetree/bindings/display/bridge/ti,sn65dsi83.yaml Note, the same issue is observed in patch[3] of the series. regards Alex > + reg = <0x2c>; > + enable-gpios = <&gpiof 15 GPIO_ACTIVE_HIGH>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + bridge_in_dsi: endpoint { > + remote-endpoint = <&dsi_out_bridge>; > + data-lanes = <0 1>; > + }; > + }; > + > + port@2 { > + reg = <2>; > + bridge_out_panel: endpoint { > + remote-endpoint = <&panel_out_bridge>; > + }; > + }; > + }; > + }; > +}; > + > +<dc { > + status = "okay"; > + > + port { > + ltdc_out_dsi: endpoint@0 { > + reg = <0>; > + remote-endpoint = <&dsi_in_ltdc>; > + }; > + }; > }; > > &sdmmc1 { >