[PATCH 0/3] support watchdog for exynosautov920

[PATCH 0/3] support watchdog for exynosautov920

[Taewan Kim]

Add support for the ExynosAutoV920 SoC. Basically this is almost
similar to ExynosAuto V9 or Exynos850 such as two watchdog instance for
each cluster but some CPU configuration are quite different.
Therefore device tree, compatibles and drvdata should be added.

Byoungtae Cho (3):
  dt-bindings: watchdog: Document ExynosAutoV920 watchdog bindings
  watchdog: s3c2410_wdt: add support for exynosautov920 SoC
  arm64: dts: exynosautov920: add watchdog DT node

 .../bindings/watchdog/samsung-wdt.yaml        |  3 ++
 .../arm64/boot/dts/exynos/exynosautov920.dtsi | 20 ++++++++++
 drivers/watchdog/s3c2410_wdt.c                | 37 ++++++++++++++++++-
 3 files changed, 59 insertions(+), 1 deletion(-)

-- 
2.46.0

[PATCH 1/3] dt-bindings: watchdog: Document ExynosAutoV920 watchdog bindings

[Taewan Kim]

From: Byoungtae Cho <bt.cho@samsung.com>

Add "samsung-exynosautov920-wdt" compatible to the dt-schema
document. ExynosAutoV920 is new SoC for automotive, similar to
exynosautov9 but some CPU configurations are quite different.

Signed-off-by: Byoungtae Cho <bt.cho@samsung.com>
Signed-off-by: Taewan Kim <trunixs.kim@samsung.com>
---
 Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
index 77a5ddd0426e..d175ae968336 100644
--- a/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
+++ b/Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml
@@ -26,6 +26,7 @@ properties:
           - samsung,exynos7-wdt                   # for Exynos7
           - samsung,exynos850-wdt                 # for Exynos850
           - samsung,exynosautov9-wdt              # for Exynosautov9
+          - samsung,exynosautov920-wdt            # for Exynosautov920
       - items:
           - enum:
               - tesla,fsd-wdt
@@ -77,6 +78,7 @@ allOf:
               - samsung,exynos7-wdt
               - samsung,exynos850-wdt
               - samsung,exynosautov9-wdt
+              - samsung,exynosautov920-wdt
     then:
       required:
         - samsung,syscon-phandle
@@ -88,6 +90,7 @@ allOf:
               - google,gs101-wdt
               - samsung,exynos850-wdt
               - samsung,exynosautov9-wdt
+              - samsung,exynosautov920-wdt
     then:
       properties:
         clocks:
-- 
2.46.0

[PATCH 2/3] watchdog: s3c2410_wdt: add support for exynosautov920 SoC

[Taewan Kim]

From: Byoungtae Cho <bt.cho@samsung.com>

Adds the compatibles and drvdata for the ExynosAuto V920 SoC. This SoC
is almost similar to ExynosAutoV9, but some CPU configurations are quite
different, so it should be added. Plus it also support DBGACK like as
GS101 SoC.

Signed-off-by: Byoungtae Cho <bt.cho@samsung.com>
Signed-off-by: Taewan Kim <trunixs.kim@samsung.com>
---
 drivers/watchdog/s3c2410_wdt.c | 37 +++++++++++++++++++++++++++++++++-
 1 file changed, 36 insertions(+), 1 deletion(-)

diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
index 686cf544d0ae..c25133348f0e 100644
--- a/drivers/watchdog/s3c2410_wdt.c
+++ b/drivers/watchdog/s3c2410_wdt.c
@@ -63,6 +63,10 @@
 #define EXYNOS850_CLUSTER1_NONCPU_INT_EN	0x1644
 #define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT	0x1520
 #define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN	0x1544
+#define EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT	0x1420
+#define EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN	0x1444
+#define EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT	0x1720
+#define EXYNOSAUTOV920_CLUSTER1_NONCPU_INT_EN	0x1744
 
 #define EXYNOS850_CLUSTER0_WDTRESET_BIT		24
 #define EXYNOS850_CLUSTER1_WDTRESET_BIT		23
@@ -303,6 +307,32 @@ static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
 		  QUIRK_HAS_DBGACK_BIT,
 };
 
+static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl0 = {
+	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN,
+	.mask_bit = 2,
+	.mask_reset_inv = true,
+	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
+	.rst_stat_bit = EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT,
+	.cnt_en_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT,
+	.cnt_en_bit = 7,
+	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
+		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
+		  QUIRK_HAS_DBGACK_BIT,
+};
+
+static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 = {
+	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_INT_EN,
+	.mask_bit = 2,
+	.mask_reset_inv = true,
+	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
+	.rst_stat_bit = EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT,
+	.cnt_en_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT,
+	.cnt_en_bit = 7,
+	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
+		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
+		  QUIRK_HAS_DBGACK_BIT,
+};
+
 static const struct of_device_id s3c2410_wdt_match[] = {
 	{ .compatible = "google,gs101-wdt",
 	  .data = &drv_data_gs101_cl0 },
@@ -320,6 +350,8 @@ static const struct of_device_id s3c2410_wdt_match[] = {
 	  .data = &drv_data_exynos850_cl0 },
 	{ .compatible = "samsung,exynosautov9-wdt",
 	  .data = &drv_data_exynosautov9_cl0 },
+	{ .compatible = "samsung,exynosautov920-wdt",
+	  .data = &drv_data_exynosautov920_cl0},
 	{},
 };
 MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
@@ -643,7 +675,8 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
 	/* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
 	if (variant == &drv_data_exynos850_cl0 ||
 	    variant == &drv_data_exynosautov9_cl0 ||
-	    variant == &drv_data_gs101_cl0) {
+	    variant == &drv_data_gs101_cl0 ||
+	    variant == &drv_data_exynosautov920_cl0) {
 		u32 index;
 		int err;
 
@@ -662,6 +695,8 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
 				variant = &drv_data_exynosautov9_cl1;
 			else if (variant == &drv_data_gs101_cl0)
 				variant = &drv_data_gs101_cl1;
+			else if (variant == &drv_data_exynosautov920_cl1)
+				variant = &drv_data_exynosautov920_cl1;
 			break;
 		default:
 			return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
-- 
2.46.0

[PATCH 3/3] arm64: dts: exynosautov920: add watchdog DT node

[Taewan Kim]

From: Byoungtae Cho <bt.cho@samsung.com>

Adds two watchdog devices for ExynosAutoV920 SoC.

Signed-off-by: Byoungtae Cho <bt.cho@samsung.com>
Signed-off-by: Taewan Kim <trunixs.kim@samsung.com>
---
 .../arm64/boot/dts/exynos/exynosautov920.dtsi | 20 +++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
index c1c8566d74f5..de210f8e5599 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
@@ -297,6 +297,26 @@ pinctrl_aud: pinctrl@1a460000 {
 			compatible = "samsung,exynosautov920-pinctrl";
 			reg = <0x1a460000 0x10000>;
 		};
+
+		watchdog_cl0: watchdog@10060000 {
+			compatible = "samsung,exynosautov920-wdt";
+			reg = <0x10060000 0x100>;
+			interrupts = <GIC_SPI 953 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&xtcxo>, <&xtcxo>;
+			clock-names = "watchdog", "watchdog_src";
+			samsung,syscon-phandle = <&pmu_system_controller>;
+			samsung,cluster-index = <0>;
+		};
+
+		watchdog_cl1: watchdog@10070000 {
+			compatible = "samsung,exynosautov920-wdt";
+			reg = <0x10070000 0x100>;
+			interrupts = <GIC_SPI 952 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&xtcxo>, <&xtcxo>;
+			clock-names = "watchdog", "watchdog_src";
+			samsung,syscon-phandle = <&pmu_system_controller>;
+			samsung,cluster-index = <1>;
+		};
 	};
 
 	timer {
-- 
2.46.0

Re: [PATCH 1/3] dt-bindings: watchdog: Document ExynosAutoV920 watchdog bindings

[Rob Herring (Arm)]

On Fri, 13 Sep 2024 17:03:23 +0900, Taewan Kim wrote:
> From: Byoungtae Cho <bt.cho@samsung.com>
> 
> Add "samsung-exynosautov920-wdt" compatible to the dt-schema
> document. ExynosAutoV920 is new SoC for automotive, similar to
> exynosautov9 but some CPU configurations are quite different.
> 
> Signed-off-by: Byoungtae Cho <bt.cho@samsung.com>
> Signed-off-by: Taewan Kim <trunixs.kim@samsung.com>
> ---
>  Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml | 3 +++
>  1 file changed, 3 insertions(+)
> 

Acked-by: Rob Herring (Arm) <robh@kernel.org>

Re: [PATCH 3/3] arm64: dts: exynosautov920: add watchdog DT node

[Krzysztof Kozlowski]

On 13/09/2024 10:03, Taewan Kim wrote:
> From: Byoungtae Cho <bt.cho@samsung.com>
> 
> Adds two watchdog devices for ExynosAutoV920 SoC.
> 
> Signed-off-by: Byoungtae Cho <bt.cho@samsung.com>
> Signed-off-by: Taewan Kim <trunixs.kim@samsung.com>
> ---
>  .../arm64/boot/dts/exynos/exynosautov920.dtsi | 20 +++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> index c1c8566d74f5..de210f8e5599 100644
> --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> @@ -297,6 +297,26 @@ pinctrl_aud: pinctrl@1a460000 {
>  			compatible = "samsung,exynosautov920-pinctrl";
>  			reg = <0x1a460000 0x10000>;
>  		};
> +
> +		watchdog_cl0: watchdog@10060000 {

Does not look like placed in correct location. 1a46 > 1006. Please
follow DTS coding style in all your works.

Best regards,
Krzysztof

Re: [PATCH 2/3] watchdog: s3c2410_wdt: add support for exynosautov920 SoC

[Krzysztof Kozlowski]

On 13/09/2024 10:03, Taewan Kim wrote:
> From: Byoungtae Cho <bt.cho@samsung.com>
> 
> Adds the compatibles and drvdata for the ExynosAuto V920 SoC. This SoC
> is almost similar to ExynosAutoV9, but some CPU configurations are quite
> different, so it should be added. Plus it also support DBGACK like as
> GS101 SoC.
> 
> Signed-off-by: Byoungtae Cho <bt.cho@samsung.com>
> Signed-off-by: Taewan Kim <trunixs.kim@samsung.com>
> ---
>  drivers/watchdog/s3c2410_wdt.c | 37 +++++++++++++++++++++++++++++++++-
>  1 file changed, 36 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index 686cf544d0ae..c25133348f0e 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c
> @@ -63,6 +63,10 @@
>  #define EXYNOS850_CLUSTER1_NONCPU_INT_EN	0x1644
>  #define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT	0x1520
>  #define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN	0x1544
> +#define EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT	0x1420
> +#define EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN	0x1444
> +#define EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT	0x1720
> +#define EXYNOSAUTOV920_CLUSTER1_NONCPU_INT_EN	0x1744
>  
>  #define EXYNOS850_CLUSTER0_WDTRESET_BIT		24
>  #define EXYNOS850_CLUSTER1_WDTRESET_BIT		23
> @@ -303,6 +307,32 @@ static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
>  		  QUIRK_HAS_DBGACK_BIT,
>  };
>  
> +static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl0 = {
> +	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN,
> +	.mask_bit = 2,
> +	.mask_reset_inv = true,
> +	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> +	.rst_stat_bit = EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT,
> +	.cnt_en_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT,
> +	.cnt_en_bit = 7,
> +	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
> +		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
> +		  QUIRK_HAS_DBGACK_BIT,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 = {
> +	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_INT_EN,
> +	.mask_bit = 2,
> +	.mask_reset_inv = true,
> +	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> +	.rst_stat_bit = EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT,
> +	.cnt_en_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT,
> +	.cnt_en_bit = 7,
> +	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
> +		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
> +		  QUIRK_HAS_DBGACK_BIT,
> +};
> +
>  static const struct of_device_id s3c2410_wdt_match[] = {
>  	{ .compatible = "google,gs101-wdt",
>  	  .data = &drv_data_gs101_cl0 },
> @@ -320,6 +350,8 @@ static const struct of_device_id s3c2410_wdt_match[] = {
>  	  .data = &drv_data_exynos850_cl0 },
>  	{ .compatible = "samsung,exynosautov9-wdt",
>  	  .data = &drv_data_exynosautov9_cl0 },
> +	{ .compatible = "samsung,exynosautov920-wdt",
> +	  .data = &drv_data_exynosautov920_cl0},

Missing space before }

>  	{},
>  };


Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 1/3] dt-bindings: watchdog: Document ExynosAutoV920 watchdog bindings

[Krzysztof Kozlowski]

On 13/09/2024 10:03, Taewan Kim wrote:
> From: Byoungtae Cho <bt.cho@samsung.com>
> 
> Add "samsung-exynosautov920-wdt" compatible to the dt-schema
> document. ExynosAutoV920 is new SoC for automotive, similar to
> exynosautov9 but some CPU configurations are quite different.
> 
> Signed-off-by: Byoungtae Cho <bt.cho@samsung.com>
> Signed-off-by: Taewan Kim <trunixs.kim@samsung.com>
> ---
>  Documentation/devicetree/bindings/watchdog/samsung-wdt.yaml | 3 +++
>  1 file changed, 3 insertions(+)
> 

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

Re: [PATCH 2/3] watchdog: s3c2410_wdt: add support for exynosautov920 SoC

[Guenter Roeck]

On 9/13/24 01:03, Taewan Kim wrote:
> From: Byoungtae Cho <bt.cho@samsung.com>
> 
> Adds the compatibles and drvdata for the ExynosAuto V920 SoC. This SoC
> is almost similar to ExynosAutoV9, but some CPU configurations are quite
> different, so it should be added. Plus it also support DBGACK like as
> GS101 SoC.
> 
> Signed-off-by: Byoungtae Cho <bt.cho@samsung.com>
> Signed-off-by: Taewan Kim <trunixs.kim@samsung.com>

Reviewed-by: Guenter Roeck <linux@roeck-us.net>

> ---
>   drivers/watchdog/s3c2410_wdt.c | 37 +++++++++++++++++++++++++++++++++-
>   1 file changed, 36 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index 686cf544d0ae..c25133348f0e 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c
> @@ -63,6 +63,10 @@
>   #define EXYNOS850_CLUSTER1_NONCPU_INT_EN	0x1644
>   #define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT	0x1520
>   #define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN	0x1544
> +#define EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT	0x1420
> +#define EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN	0x1444
> +#define EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT	0x1720
> +#define EXYNOSAUTOV920_CLUSTER1_NONCPU_INT_EN	0x1744
>   
>   #define EXYNOS850_CLUSTER0_WDTRESET_BIT		24
>   #define EXYNOS850_CLUSTER1_WDTRESET_BIT		23
> @@ -303,6 +307,32 @@ static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
>   		  QUIRK_HAS_DBGACK_BIT,
>   };
>   
> +static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl0 = {
> +	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN,
> +	.mask_bit = 2,
> +	.mask_reset_inv = true,
> +	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> +	.rst_stat_bit = EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT,
> +	.cnt_en_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT,
> +	.cnt_en_bit = 7,
> +	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
> +		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
> +		  QUIRK_HAS_DBGACK_BIT,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 = {
> +	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_INT_EN,
> +	.mask_bit = 2,
> +	.mask_reset_inv = true,
> +	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> +	.rst_stat_bit = EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT,
> +	.cnt_en_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT,
> +	.cnt_en_bit = 7,
> +	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
> +		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
> +		  QUIRK_HAS_DBGACK_BIT,
> +};
> +
>   static const struct of_device_id s3c2410_wdt_match[] = {
>   	{ .compatible = "google,gs101-wdt",
>   	  .data = &drv_data_gs101_cl0 },
> @@ -320,6 +350,8 @@ static const struct of_device_id s3c2410_wdt_match[] = {
>   	  .data = &drv_data_exynos850_cl0 },
>   	{ .compatible = "samsung,exynosautov9-wdt",
>   	  .data = &drv_data_exynosautov9_cl0 },
> +	{ .compatible = "samsung,exynosautov920-wdt",
> +	  .data = &drv_data_exynosautov920_cl0},
>   	{},
>   };
>   MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
> @@ -643,7 +675,8 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
>   	/* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
>   	if (variant == &drv_data_exynos850_cl0 ||
>   	    variant == &drv_data_exynosautov9_cl0 ||
> -	    variant == &drv_data_gs101_cl0) {
> +	    variant == &drv_data_gs101_cl0 ||
> +	    variant == &drv_data_exynosautov920_cl0) {
>   		u32 index;
>   		int err;
>   
> @@ -662,6 +695,8 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
>   				variant = &drv_data_exynosautov9_cl1;
>   			else if (variant == &drv_data_gs101_cl0)
>   				variant = &drv_data_gs101_cl1;
> +			else if (variant == &drv_data_exynosautov920_cl1)
> +				variant = &drv_data_exynosautov920_cl1;
>   			break;
>   		default:
>   			return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);

Re: [PATCH 2/3] watchdog: s3c2410_wdt: add support for exynosautov920 SoC

[Sam Protsenko]

On Fri, Sep 13, 2024 at 3:04 AM Taewan Kim <trunixs.kim@samsung.com> wrote:
>
> From: Byoungtae Cho <bt.cho@samsung.com>
>
> Adds the compatibles and drvdata for the ExynosAuto V920 SoC. This SoC
> is almost similar to ExynosAutoV9, but some CPU configurations are quite
> different, so it should be added. Plus it also support DBGACK like as
> GS101 SoC.
>
> Signed-off-by: Byoungtae Cho <bt.cho@samsung.com>
> Signed-off-by: Taewan Kim <trunixs.kim@samsung.com>
> ---
>  drivers/watchdog/s3c2410_wdt.c | 37 +++++++++++++++++++++++++++++++++-
>  1 file changed, 36 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/watchdog/s3c2410_wdt.c b/drivers/watchdog/s3c2410_wdt.c
> index 686cf544d0ae..c25133348f0e 100644
> --- a/drivers/watchdog/s3c2410_wdt.c
> +++ b/drivers/watchdog/s3c2410_wdt.c
> @@ -63,6 +63,10 @@
>  #define EXYNOS850_CLUSTER1_NONCPU_INT_EN       0x1644
>  #define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT       0x1520
>  #define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN    0x1544
> +#define EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT     0x1420
> +#define EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN  0x1444
> +#define EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT     0x1720
> +#define EXYNOSAUTOV920_CLUSTER1_NONCPU_INT_EN  0x1744
>
>  #define EXYNOS850_CLUSTER0_WDTRESET_BIT                24
>  #define EXYNOS850_CLUSTER1_WDTRESET_BIT                23
> @@ -303,6 +307,32 @@ static const struct s3c2410_wdt_variant drv_data_gs101_cl1 = {
>                   QUIRK_HAS_DBGACK_BIT,
>  };
>
> +static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl0 = {
> +       .mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN,
> +       .mask_bit = 2,
> +       .mask_reset_inv = true,
> +       .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> +       .rst_stat_bit = EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT,
> +       .cnt_en_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT,
> +       .cnt_en_bit = 7,
> +       .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
> +                 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
> +                 QUIRK_HAS_DBGACK_BIT,
> +};
> +
> +static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 = {
> +       .mask_reset_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_INT_EN,
> +       .mask_bit = 2,
> +       .mask_reset_inv = true,
> +       .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> +       .rst_stat_bit = EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT,
> +       .cnt_en_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT,
> +       .cnt_en_bit = 7,
> +       .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
> +                 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
> +                 QUIRK_HAS_DBGACK_BIT,
> +};
> +
>  static const struct of_device_id s3c2410_wdt_match[] = {
>         { .compatible = "google,gs101-wdt",
>           .data = &drv_data_gs101_cl0 },
> @@ -320,6 +350,8 @@ static const struct of_device_id s3c2410_wdt_match[] = {
>           .data = &drv_data_exynos850_cl0 },
>         { .compatible = "samsung,exynosautov9-wdt",
>           .data = &drv_data_exynosautov9_cl0 },
> +       { .compatible = "samsung,exynosautov920-wdt",
> +         .data = &drv_data_exynosautov920_cl0},
>         {},
>  };
>  MODULE_DEVICE_TABLE(of, s3c2410_wdt_match);
> @@ -643,7 +675,8 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
>         /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index */
>         if (variant == &drv_data_exynos850_cl0 ||
>             variant == &drv_data_exynosautov9_cl0 ||
> -           variant == &drv_data_gs101_cl0) {
> +           variant == &drv_data_gs101_cl0 ||
> +           variant == &drv_data_exynosautov920_cl0) {
>                 u32 index;
>                 int err;
>
> @@ -662,6 +695,8 @@ s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct s3c2410_wdt *wdt)
>                                 variant = &drv_data_exynosautov9_cl1;
>                         else if (variant == &drv_data_gs101_cl0)
>                                 variant = &drv_data_gs101_cl1;
> +                       else if (variant == &drv_data_exynosautov920_cl1)

Shouldn't it be cl0 here?

> +                               variant = &drv_data_exynosautov920_cl1;
>                         break;
>                 default:
>                         return dev_err_probe(dev, -EINVAL, "wrong cluster index: %u\n", index);
> --
> 2.46.0
>
>

RE: [PATCH 2/3] watchdog: s3c2410_wdt: add support for exynosautov920 SoC

[김태완]

Hi,

Thank you for your review.
I will apply your point to v2 patch.

Best regards,
Taewan Kim.

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Monday, September 30, 2024 9:05 PM
> To: Taewan Kim <trunixs.kim@samsung.com>; Wim Van Sebroeck <wim@linux-
> watchdog.org>; Guenter Roeck <linux@roeck-us.net>; Rob Herring
> <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley
> <conor+dt@kernel.org>; Alim Akhtar <alim.akhtar@samsung.com>
> Cc: linux-watchdog@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> samsung-soc@vger.kernel.org; Byoungtae Cho <bt.cho@samsung.com>
> Subject: Re: [PATCH 2/3] watchdog: s3c2410_wdt: add support for
> exynosautov920 SoC
> 
> On 13/09/2024 10:03, Taewan Kim wrote:
> > From: Byoungtae Cho <bt.cho@samsung.com>
> >
> > Adds the compatibles and drvdata for the ExynosAuto V920 SoC. This SoC
> > is almost similar to ExynosAutoV9, but some CPU configurations are
> > quite different, so it should be added. Plus it also support DBGACK
> > like as
> > GS101 SoC.
> >
> > Signed-off-by: Byoungtae Cho <bt.cho@samsung.com>
> > Signed-off-by: Taewan Kim <trunixs.kim@samsung.com>
> > ---
> >  drivers/watchdog/s3c2410_wdt.c | 37
> > +++++++++++++++++++++++++++++++++-
> >  1 file changed, 36 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/watchdog/s3c2410_wdt.c
> > b/drivers/watchdog/s3c2410_wdt.c index 686cf544d0ae..c25133348f0e
> > 100644
> > --- a/drivers/watchdog/s3c2410_wdt.c
> > +++ b/drivers/watchdog/s3c2410_wdt.c
> > @@ -63,6 +63,10 @@
> >  #define EXYNOS850_CLUSTER1_NONCPU_INT_EN	0x1644
> >  #define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT	0x1520
> >  #define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN	0x1544
> > +#define EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT	0x1420
> > +#define EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN	0x1444
> > +#define EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT	0x1720
> > +#define EXYNOSAUTOV920_CLUSTER1_NONCPU_INT_EN	0x1744
> >
> >  #define EXYNOS850_CLUSTER0_WDTRESET_BIT		24
> >  #define EXYNOS850_CLUSTER1_WDTRESET_BIT		23
> > @@ -303,6 +307,32 @@ static const struct s3c2410_wdt_variant
> drv_data_gs101_cl1 = {
> >  		  QUIRK_HAS_DBGACK_BIT,
> >  };
> >
> > +static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl0 = {
> > +	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN,
> > +	.mask_bit = 2,
> > +	.mask_reset_inv = true,
> > +	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> > +	.rst_stat_bit = EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT,
> > +	.cnt_en_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT,
> > +	.cnt_en_bit = 7,
> > +	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
> > +		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
> > +		  QUIRK_HAS_DBGACK_BIT,
> > +};
> > +
> > +static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 = {
> > +	.mask_reset_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_INT_EN,
> > +	.mask_bit = 2,
> > +	.mask_reset_inv = true,
> > +	.rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> > +	.rst_stat_bit = EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT,
> > +	.cnt_en_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT,
> > +	.cnt_en_bit = 7,
> > +	.quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
> > +		  QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
> > +		  QUIRK_HAS_DBGACK_BIT,
> > +};
> > +
> >  static const struct of_device_id s3c2410_wdt_match[] = {
> >  	{ .compatible = "google,gs101-wdt",
> >  	  .data = &drv_data_gs101_cl0 },
> > @@ -320,6 +350,8 @@ static const struct of_device_id s3c2410_wdt_match[]
> = {
> >  	  .data = &drv_data_exynos850_cl0 },
> >  	{ .compatible = "samsung,exynosautov9-wdt",
> >  	  .data = &drv_data_exynosautov9_cl0 },
> > +	{ .compatible = "samsung,exynosautov920-wdt",
> > +	  .data = &drv_data_exynosautov920_cl0},
> 
> Missing space before }
> 
> >  	{},
> >  };
> 
> 
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> 
> Best regards,
> Krzysztof

RE: [PATCH 2/3] watchdog: s3c2410_wdt: add support for exynosautov920 SoC

[김태완]

Hi,

Thank you for your review.
Yes, cl0 is correct not cl1.
I will apply it to v2 patch.

Best regards,
Taewan Kim.

> -----Original Message-----
> From: Sam Protsenko <semen.protsenko@linaro.org>
> Sent: Tuesday, October 1, 2024 5:15 AM
> To: Taewan Kim <trunixs.kim@samsung.com>
> Cc: Wim Van Sebroeck <wim@linux-watchdog.org>; Guenter Roeck <linux@roeck-
> us.net>; Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Alim Akhtar
> <alim.akhtar@samsung.com>; linux-watchdog@vger.kernel.org;
> devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; linux-arm-
> kernel@lists.infradead.org; linux-samsung-soc@vger.kernel.org; Byoungtae
> Cho <bt.cho@samsung.com>
> Subject: Re: [PATCH 2/3] watchdog: s3c2410_wdt: add support for
> exynosautov920 SoC
> 
> On Fri, Sep 13, 2024 at 3:04 AM Taewan Kim <trunixs.kim@samsung.com> wrote:
> >
> > From: Byoungtae Cho <bt.cho@samsung.com>
> >
> > Adds the compatibles and drvdata for the ExynosAuto V920 SoC. This SoC
> > is almost similar to ExynosAutoV9, but some CPU configurations are
> > quite different, so it should be added. Plus it also support DBGACK
> > like as
> > GS101 SoC.
> >
> > Signed-off-by: Byoungtae Cho <bt.cho@samsung.com>
> > Signed-off-by: Taewan Kim <trunixs.kim@samsung.com>
> > ---
> >  drivers/watchdog/s3c2410_wdt.c | 37
> > +++++++++++++++++++++++++++++++++-
> >  1 file changed, 36 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/watchdog/s3c2410_wdt.c
> > b/drivers/watchdog/s3c2410_wdt.c index 686cf544d0ae..c25133348f0e
> > 100644
> > --- a/drivers/watchdog/s3c2410_wdt.c
> > +++ b/drivers/watchdog/s3c2410_wdt.c
> > @@ -63,6 +63,10 @@
> >  #define EXYNOS850_CLUSTER1_NONCPU_INT_EN       0x1644
> >  #define EXYNOSAUTOV9_CLUSTER1_NONCPU_OUT       0x1520
> >  #define EXYNOSAUTOV9_CLUSTER1_NONCPU_INT_EN    0x1544
> > +#define EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT     0x1420
> > +#define EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN  0x1444
> > +#define EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT     0x1720
> > +#define EXYNOSAUTOV920_CLUSTER1_NONCPU_INT_EN  0x1744
> >
> >  #define EXYNOS850_CLUSTER0_WDTRESET_BIT                24
> >  #define EXYNOS850_CLUSTER1_WDTRESET_BIT                23
> > @@ -303,6 +307,32 @@ static const struct s3c2410_wdt_variant
> drv_data_gs101_cl1 = {
> >                   QUIRK_HAS_DBGACK_BIT,  };
> >
> > +static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl0 = {
> > +       .mask_reset_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_INT_EN,
> > +       .mask_bit = 2,
> > +       .mask_reset_inv = true,
> > +       .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> > +       .rst_stat_bit = EXYNOSAUTOV9_CLUSTER0_WDTRESET_BIT,
> > +       .cnt_en_reg = EXYNOSAUTOV920_CLUSTER0_NONCPU_OUT,
> > +       .cnt_en_bit = 7,
> > +       .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
> > +                 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
> > +                 QUIRK_HAS_DBGACK_BIT, };
> > +
> > +static const struct s3c2410_wdt_variant drv_data_exynosautov920_cl1 = {
> > +       .mask_reset_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_INT_EN,
> > +       .mask_bit = 2,
> > +       .mask_reset_inv = true,
> > +       .rst_stat_reg = EXYNOS5_RST_STAT_REG_OFFSET,
> > +       .rst_stat_bit = EXYNOSAUTOV9_CLUSTER1_WDTRESET_BIT,
> > +       .cnt_en_reg = EXYNOSAUTOV920_CLUSTER1_NONCPU_OUT,
> > +       .cnt_en_bit = 7,
> > +       .quirks = QUIRK_HAS_WTCLRINT_REG | QUIRK_HAS_PMU_MASK_RESET |
> > +                 QUIRK_HAS_PMU_RST_STAT | QUIRK_HAS_PMU_CNT_EN |
> > +                 QUIRK_HAS_DBGACK_BIT, };
> > +
> >  static const struct of_device_id s3c2410_wdt_match[] = {
> >         { .compatible = "google,gs101-wdt",
> >           .data = &drv_data_gs101_cl0 }, @@ -320,6 +350,8 @@ static
> > const struct of_device_id s3c2410_wdt_match[] = {
> >           .data = &drv_data_exynos850_cl0 },
> >         { .compatible = "samsung,exynosautov9-wdt",
> >           .data = &drv_data_exynosautov9_cl0 },
> > +       { .compatible = "samsung,exynosautov920-wdt",
> > +         .data = &drv_data_exynosautov920_cl0},
> >         {},
> >  };
> >  MODULE_DEVICE_TABLE(of, s3c2410_wdt_match); @@ -643,7 +675,8 @@
> > s3c2410_get_wdt_drv_data(struct platform_device *pdev, struct
> s3c2410_wdt *wdt)
> >         /* Choose Exynos850/ExynosAutov9 driver data w.r.t. cluster index
> */
> >         if (variant == &drv_data_exynos850_cl0 ||
> >             variant == &drv_data_exynosautov9_cl0 ||
> > -           variant == &drv_data_gs101_cl0) {
> > +           variant == &drv_data_gs101_cl0 ||
> > +           variant == &drv_data_exynosautov920_cl0) {
> >                 u32 index;
> >                 int err;
> >
> > @@ -662,6 +695,8 @@ s3c2410_get_wdt_drv_data(struct platform_device
> *pdev, struct s3c2410_wdt *wdt)
> >                                 variant = &drv_data_exynosautov9_cl1;
> >                         else if (variant == &drv_data_gs101_cl0)
> >                                 variant = &drv_data_gs101_cl1;
> > +                       else if (variant ==
> > + &drv_data_exynosautov920_cl1)
> 
> Shouldn't it be cl0 here?
> 
> > +                               variant =
> > + &drv_data_exynosautov920_cl1;
> >                         break;
> >                 default:
> >                         return dev_err_probe(dev, -EINVAL, "wrong
> > cluster index: %u\n", index);
> > --
> > 2.46.0
> >
> >

RE: [PATCH 3/3] arm64: dts: exynosautov920: add watchdog DT node

[김태완]

Hi,

I will move it between 'chipid@10000000' and 'interrupt-controller@10400000'.
Thank you for pointing.

Best regards,
Taewan Kim.

> -----Original Message-----
> From: Krzysztof Kozlowski <krzk@kernel.org>
> Sent: Monday, September 30, 2024 8:38 PM
> To: Taewan Kim <trunixs.kim@samsung.com>; Wim Van Sebroeck <wim@linux-
> watchdog.org>; Guenter Roeck <linux@roeck-us.net>; Rob Herring
> <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley
> <conor+dt@kernel.org>; Alim Akhtar <alim.akhtar@samsung.com>
> Cc: linux-watchdog@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> samsung-soc@vger.kernel.org; Byoungtae Cho <bt.cho@samsung.com>
> Subject: Re: [PATCH 3/3] arm64: dts: exynosautov920: add watchdog DT node
> 
> On 13/09/2024 10:03, Taewan Kim wrote:
> > From: Byoungtae Cho <bt.cho@samsung.com>
> >
> > Adds two watchdog devices for ExynosAutoV920 SoC.
> >
> > Signed-off-by: Byoungtae Cho <bt.cho@samsung.com>
> > Signed-off-by: Taewan Kim <trunixs.kim@samsung.com>
> > ---
> >  .../arm64/boot/dts/exynos/exynosautov920.dtsi | 20
> > +++++++++++++++++++
> >  1 file changed, 20 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > index c1c8566d74f5..de210f8e5599 100644
> > --- a/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > +++ b/arch/arm64/boot/dts/exynos/exynosautov920.dtsi
> > @@ -297,6 +297,26 @@ pinctrl_aud: pinctrl@1a460000 {
> >  			compatible = "samsung,exynosautov920-pinctrl";
> >  			reg = <0x1a460000 0x10000>;
> >  		};
> > +
> > +		watchdog_cl0: watchdog@10060000 {
> 
> Does not look like placed in correct location. 1a46 > 1006. Please follow
> DTS coding style in all your works.
> 
> Best regards,
> Krzysztof

RE: [PATCH 2/3] watchdog: s3c2410_wdt: add support for exynosautov920 SoC

[Alim Akhtar]

Hi Taewan

> -----Original Message-----
> From: 김태완 <trunixs.kim@samsung.com>
> Sent: Thursday, October 10, 2024 12:56 PM
> To: 'Sam Protsenko' <semen.protsenko@linaro.org>
> Cc: 'Wim Van Sebroeck' <wim@linux-watchdog.org>; 'Guenter Roeck'
> <linux@roeck-us.net>; 'Rob Herring' <robh@kernel.org>; 'Krzysztof
> Kozlowski' <krzk+dt@kernel.org>; 'Conor Dooley' <conor+dt@kernel.org>;
> 'Alim Akhtar' <alim.akhtar@samsung.com>; linux-
> watchdog@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> samsung-soc@vger.kernel.org; 'Byoungtae Cho' <bt.cho@samsung.com>
> Subject: RE: [PATCH 2/3] watchdog: s3c2410_wdt: add support for
> exynosautov920 SoC
> 
> Hi,
> 
> Thank you for your review.
> Yes, cl0 is correct not cl1.
> I will apply it to v2 patch.
> 
Don’t send a top up reply, context get lost. Configure your email client properly to send a inline reply. 

> Best regards,
> Taewan Kim.
> 

RE: [PATCH 2/3] watchdog: s3c2410_wdt: add support for exynosautov920 SoC

[김태완]

Hi Alim,

> -----Original Message-----
> From: Alim Akhtar <alim.akhtar@samsung.com>
> Sent: Thursday, October 10, 2024 4:45 PM
> To: '김태완' <trunixs.kim@samsung.com>; 'Sam Protsenko'
> <semen.protsenko@linaro.org>
> Cc: 'Wim Van Sebroeck' <wim@linux-watchdog.org>; 'Guenter Roeck'
> <linux@roeck-us.net>; 'Rob Herring' <robh@kernel.org>; 'Krzysztof 
> Kozlowski' <krzk+dt@kernel.org>; 'Conor Dooley' <conor+dt@kernel.org>;
> linux-watchdog@vger.kernel.org; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> samsung-soc@vger.kernel.org; 'Byoungtae Cho' <bt.cho@samsung.com>
> Subject: RE: [PATCH 2/3] watchdog: s3c2410_wdt: add support for
> exynosautov920 SoC
> 
> Hi Taewan
> 
> > -----Original Message-----
> > From: 김태완 <trunixs.kim@samsung.com>
> > Sent: Thursday, October 10, 2024 12:56 PM
> > To: 'Sam Protsenko' <semen.protsenko@linaro.org>
> > Cc: 'Wim Van Sebroeck' <wim@linux-watchdog.org>; 'Guenter Roeck'
> > <linux@roeck-us.net>; 'Rob Herring' <robh@kernel.org>; 'Krzysztof
> > Kozlowski' <krzk+dt@kernel.org>; 'Conor Dooley' <conor+dt@kernel.org>;
> > 'Alim Akhtar' <alim.akhtar@samsung.com>; linux-
> > watchdog@vger.kernel.org; devicetree@vger.kernel.org; linux-
> > kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; linux-
> > samsung-soc@vger.kernel.org; 'Byoungtae Cho' <bt.cho@samsung.com>
> > Subject: RE: [PATCH 2/3] watchdog: s3c2410_wdt: add support for
> > exynosautov920 SoC
> >
> > Hi,
> >
> > Thank you for your review.
> > Yes, cl0 is correct not cl1.
> > I will apply it to v2 patch.
> >
> Don’t send a top up reply, context get lost. Configure your email client
> properly to send a inline reply.

Thanks. I'll bear that in mind.
> 
> > Best regards,
> > Taewan Kim.
> >
>