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Tue, 28 Apr 2026 10:21:59 -0700 (PDT) X-Received: by 2002:a17:90b:3fc5:b0:364:74c1:53b7 with SMTP id 98e67ed59e1d1-364a0adec05mr299334a91.2.1777396919181; Tue, 28 Apr 2026 10:21:59 -0700 (PDT) Received: from [192.168.1.4] ([122.177.243.58]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3649fe8990esm349871a91.0.2026.04.28.10.21.50 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 28 Apr 2026 10:21:58 -0700 (PDT) Message-ID: <008f2f0a-2367-4d8e-b6b7-2421a4de88cb@oss.qualcomm.com> Date: Tue, 28 Apr 2026 22:51:47 +0530 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: Jagadeesh Kona Subject: Re: [PATCH 10/13] clk: qcom: dispcc-sm8750: Add support to control MDP clocks using CESTA To: Dmitry Baryshkov Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Neil Armstrong , Lee Jones , Ajit Pandey , Imran Shaik , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Maulik Shah , Taniya Das References: <20260420-cesta-sm870-dispcc-v1-0-eb27d845df9c@oss.qualcomm.com> <20260420-cesta-sm870-dispcc-v1-10-eb27d845df9c@oss.qualcomm.com> Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNDI4MDE2NyBTYWx0ZWRfX8J5nveGAl0CV zWukRhULo1ajMUwOBoE402Q12nwdXTIT2tQifTAk9IWu9ZWJvlJv0BhSeS5ttwZDtRKuyWXpNSj xP6AHMjGxBDmiDntXzA+s40fAIWVCk3MFfFl2ypkbcHjIB6SsvOEkEm50/ysALjY2Kxeexvy/KM se48RtglyPl7LnSE/Z0Ut42mQS9jpHFP5uv93DiWbIHRFqNgG3k0N6b5uxIVMjbA0I/mT9pGiss 0lpIM74Ih+o88SvPCgMRq4qoGQvgBiFI8s+5W/qBkD8K0weK+6I4vku9Fx8H3z+92X84ZLw1slG BoAT4nSivJ5EwW9eEtehCV1j7ZEmC/YkfMh4CfJNLiWNLpeKiXVMkXWKLURh/MAyCldUQbsA2Ez hIsncJpjP12J+SvpvdEc11Dbe5yWn4X3bcn6rpwJHWMGQdPzU9+MOLEP/mBdFBDM3nC5yWX6CEq MUonmULvSDobOz6q8OA== X-Authority-Analysis: v=2.4 cv=TZKmcxQh c=1 sm=1 tr=0 ts=69f0ecb8 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=EwI1ikYXukqkrg4G3Narhw==:17 a=IkcTkHD0fZMA:10 a=A5OVakUREuEA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=ZpdpYltYx_vBUK5n70dp:22 a=EUspDBNiAAAA:8 a=hyz_MBUfSQ2kkO8oYCUA:9 a=QEXdDO2ut3YA:10 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: C5X1RilIrotl383sDxM9aIrO30lSt9PG X-Proofpoint-ORIG-GUID: C5X1RilIrotl383sDxM9aIrO30lSt9PG X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49 definitions=2026-04-28_05,2026-04-28_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 adultscore=0 phishscore=0 clxscore=1015 suspectscore=0 bulkscore=0 malwarescore=0 impostorscore=0 lowpriorityscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2604280167 On 4/23/2026 12:03 AM, Dmitry Baryshkov wrote: > On Mon, Apr 20, 2026 at 09:59:03PM +0530, Jagadeesh Kona wrote: >> Add support to control the DISPCC MDSS MDP RCG and the associated display >> PLL0 using display CESTA hardware on SM8750 platform. If display CRM is >> enabled, the clock ops of these clocks will be updated by the common code >> before registration to use CRM specific clock ops, allowing these clocks >> to be controlled using display CRM (CESTA Resource Manager) hardware. >> >> Co-developed-by: Taniya Das >> Signed-off-by: Taniya Das >> Signed-off-by: Jagadeesh Kona >> --- >> drivers/clk/qcom/dispcc-sm8750.c | 89 +++++++++++++++++++++++++--------------- >> 1 file changed, 56 insertions(+), 33 deletions(-) >> >> diff --git a/drivers/clk/qcom/dispcc-sm8750.c b/drivers/clk/qcom/dispcc-sm8750.c >> index ca09da111a50e811481fd862b54d454de024d1c9..328e43b52192702dbbfd1ed65737520acdd4a649 100644 >> --- a/drivers/clk/qcom/dispcc-sm8750.c >> +++ b/drivers/clk/qcom/dispcc-sm8750.c >> @@ -71,6 +71,16 @@ enum { >> P_SLEEP_CLK, >> }; >> >> +static struct clk_crm disp_crm = { >> + .max_perf_ol = 10, >> + .regs = { >> + .reg_cfg_rcgr_lut_base = 0xd8, >> + .reg_l_val_lut_base = 0xdc, >> + .vcd_offset = 0x268, >> + .lut_level_offset = 0x28, > > Seeing this configuration makes me even more sure. There is no separate > CRM or disp-crm. The CRM resources should be consumed by dispcc. > The CRM can be used by interconnect drivers also for BW voting via CESTA. Hence it cannot be consumed by dispcc alone. >> + }, >> +}; >> + >> static const struct pll_vco pongo_elu_vco[] = { >> { 38400000, 38400000, 0 }, >> }; >> @@ -89,21 +99,22 @@ static struct alpha_pll_config disp_cc_pll0_config = { >> .user_ctl_hi_val = 0x00000002, >> }; >> >> +static struct clk_init_data disp_cc_pll0_init = { >> + .name = "disp_cc_pll0", >> + .parent_data = &(const struct clk_parent_data) { >> + .index = DT_BI_TCXO, >> + }, >> + .num_parents = 1, >> + .flags = CLK_GET_RATE_NOCACHE, > > Why? It wasn't there beforehand. > The PLL rate can be changed by CESTA outside of the PLL callbacks, when a perf level request is sent via CRM API in RCG's prepare()/set_rate() callbacks. Having this flag ensures that the PLL rate is recalculated from hardware every time when users query the PLL's clk_rate node, providing the correct PLL rate configured by CESTA. Thanks, Jagadeesh