[PATCH 0/4 v2] Adding usb2.0 host-phy support for exynos5250

[PATCH 0/4 v2] Adding usb2.0 host-phy support for exynos5250

[Vivek Gautam]

This patchset is based on the work by Praveen Paneri for
samsung-usbphy driver:
http://comments.gmane.org/gmane.linux.kernel.samsung-soc/12653

Changes from v1:
 - squashed the patch "ARM: S3C64XX: Add phy_type to pmu_isolation" into
   "usb: phy: samsung: Add host phy support to samsung-phy driver".
 - moved similar change of adding phy_type to pmu_isolation for exynos from
   "ARM: Exynos5250: Enabling samsung-usbphy driver" to
   "usb: phy: samsung: Add host phy support to samsung-phy driver".
 - moved s5p_usb_phy_pmu_isolation() declaration from
   "ARM: Exynos5250: Enabling samsung-usbphy driver" to
   "usb: phy: samsung: Add host phy support to samsung-phy driver".
 - moved phy_cfg_sel function pointer declaration from
   "usb: phy: samsung: Add host phy support to samsung-phy driver" to
   "ARM: Exynos5250: Enabling samsung-usbphy driver".
 - Replaced the patch subject "usb: s5p-ehci: Adding phy driver support" and
   "usb: exynos-ohci: Adding phy driver support" with
   "USB: ehci-s5p: Add phy driver support" and
   "USB: ohci-exynos: Add phy driver support" respectively.
 - Corrected the header include order in ehci-s5p and ohci-exynos.
 - Corrected wrong error path for s5p_ehci_phy_disable() and
   exynos_ohci_phy_disable() in ehci-s5p and ohci-exynos respectively.

Tested on smdk5250 target with usb-next branch along with arch patches
for exynos5250:
http://thread.gmane.org/gmane.linux.kernel.samsung-soc/13042
http://thread.gmane.org/gmane.linux.kernel.samsung-soc/13048

Vivek Gautam (4):
  usb: phy: samsung: Add host phy support to samsung-phy driver
  ARM: Exynos5250: Enabling samsung-usbphy driver
  USB: ehci-s5p: Add phy driver support
  USB: ohci-exynos: Add phy driver support

 .../devicetree/bindings/usb/samsung-usbphy.txt     |   12 +-
 arch/arm/boot/dts/exynos5250.dtsi                  |    5 +
 arch/arm/mach-exynos/Kconfig                       |    1 +
 arch/arm/mach-exynos/include/mach/map.h            |    1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c             |   10 +
 arch/arm/mach-exynos/setup-usb-phy.c               |   45 ++-
 arch/arm/mach-s3c64xx/setup-usb-phy.c              |    2 +-
 arch/arm/plat-samsung/include/plat/usb-phy.h       |    3 +-
 drivers/usb/host/ehci-s5p.c                        |   65 +++-
 drivers/usb/host/ohci-exynos.c                     |   65 +++-
 drivers/usb/phy/Kconfig                            |    1 -
 drivers/usb/phy/samsung-usbphy.c                   |  368 ++++++++++++++++++--
 include/linux/platform_data/samsung-usbphy.h       |    9 +-
 13 files changed, 507 insertions(+), 80 deletions(-)

-- 
1.7.6.5

[PATCH 1/4 v2] usb: phy: samsung: Add host phy support to samsung-phy driver

[Vivek Gautam]

This patch adds host phy support to samsung-usbphy.c and
further adds support for samsung's exynos5250 usb-phy.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
---
 arch/arm/mach-exynos/setup-usb-phy.c         |    2 +-
 arch/arm/mach-s3c64xx/setup-usb-phy.c        |    2 +-
 arch/arm/plat-samsung/include/plat/usb-phy.h |    2 +-
 drivers/usb/phy/Kconfig                      |    1 -
 drivers/usb/phy/samsung-usbphy.c             |  368 ++++++++++++++++++++++++--
 include/linux/platform_data/samsung-usbphy.h |    8 +-
 6 files changed, 352 insertions(+), 31 deletions(-)

diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index 1c62d20..be6cd4f 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -222,7 +222,7 @@ int s5p_usb_phy_exit(struct platform_device *pdev, int type)
 	return -EINVAL;
 }
 
-void s5p_usb_phy_pmu_isolation(int on)
+void s5p_usb_phy_pmu_isolation(int on, int type)
 {
 	if (on) {
 		writel(readl(S5P_USBDEVICE_PHY_CONTROL)
diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
index 3aee778..b7d1d95 100644
--- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
+++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
@@ -13,7 +13,7 @@
 #include <mach/map.h>
 #include <mach/regs-sys.h>
 
-void s5p_usb_phy_pmu_isolation(int on)
+void s5p_usb_phy_pmu_isolation(int on, int type)
 {
 	if (on) {
 		writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK,
diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
index 165ffe7..7a4a959 100644
--- a/arch/arm/plat-samsung/include/plat/usb-phy.h
+++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
@@ -18,6 +18,6 @@ enum s5p_usb_phy_type {
 
 extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
 extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
-extern void s5p_usb_phy_pmu_isolation(int on);
+extern void s5p_usb_phy_pmu_isolation(int on, int type);
 
 #endif /* __PLAT_SAMSUNG_USB_PHY_H */
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 313685f..1ce5b32 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -35,7 +35,6 @@ config MV_U3D_PHY
 
 config SAMSUNG_USBPHY
 	bool "Samsung USB PHY controller Driver"
-	depends on USB_S3C_HSOTG
 	select USB_OTG_UTILS
 	help
 	  Enable this to support Samsung USB phy controller for samsung
diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c
index ee2dee0..bd6a5e8 100644
--- a/drivers/usb/phy/samsung-usbphy.c
+++ b/drivers/usb/phy/samsung-usbphy.c
@@ -61,9 +61,120 @@
 #define MHZ (1000*1000)
 #endif
 
+/* EXYNOS5 */
+#define EXYNOS5_PHYHOST				(0x00)
+
+#define EXYNOS5_PHYHOST_PHYSWRSTALL		(0x1 << 31)
+
+#define EXYNOS5_PHYHOST_REFCLKSEL_MASK		(0x3)
+#define EXYNOS5_PHYHOST_REFCLKSEL(_x)		((_x) << 19)
+#define EXYNOS5_PHYHOST_REFCLKSEL_XTAL		\
+		EXYNOS5_PHYHOST_REFCLKSEL(0x0)
+#define EXYNOS5_PHYHOST_REFCLKSEL_EXTL		\
+		EXYNOS5_PHYHOST_REFCLKSEL(0x1)
+#define EXYNOS5_PHYHOST_REFCLKSEL_CLKCORE	\
+		EXYNOS5_PHYHOST_REFCLKSEL(0x2)
+
+#define EXYNOS5_PHYHOST_FSEL_MASK		(0x7 << 16)
+#define EXYNOS5_PHYHOST_FSEL(_x)		((_x) << 16)
+#define EXYNOS5_PHYHOST_FSEL_CLKSEL_50M		(0x7)
+#define EXYNOS5_PHYHOST_FSEL_CLKSEL_24M		(0x5)
+#define EXYNOS5_PHYHOST_FSEL_CLKSEL_20M		(0x4)
+#define EXYNOS5_PHYHOST_FSEL_CLKSEL_19200K	(0x3)
+#define EXYNOS5_PHYHOST_FSEL_CLKSEL_12M		(0x2)
+#define EXYNOS5_PHYHOST_FSEL_CLKSEL_10M		(0x1)
+#define EXYNOS5_PHYHOST_FSEL_CLKSEL_9600K	(0x0)
+
+#define EXYNOS5_PHYHOST_TESTBURNIN		(0x1 << 11)
+#define EXYNOS5_PHYHOST_RETENABLE		(0x1 << 10)
+#define EXYNOS5_PHYHOST_COMMONON_N		(0x1 << 9)
+#define EXYNOS5_PHYHOST_SIDDQ			(0x1 << 6)
+#define EXYNOS5_PHYHOST_FORCESLEEP		(0x1 << 5)
+#define EXYNOS5_PHYHOST_FORCESUSPEND		(0x1 << 4)
+#define EXYNOS5_PHYHOST_WORDINTERFACE		(0x1 << 3)
+#define EXYNOS5_PHYHOST_UTMISWRST		(0x1 << 2)
+#define EXYNOS5_PHYHOST_LINKSWRST		(0x1 << 1)
+#define EXYNOS5_PHYHOST_PHYSWRST		(0x1 << 0)
+
+#define EXYNOS5_PHYHOST_TUNE0			(0x04)
+
+#define EXYNOS5_PHYHSIC1			(0x10)
+
+#define EXYNOS5_PHYHSIC_TUNE1			(0x14)
+
+#define EXYNOS5_PHYHSIC2			(0x20)
+
+#define EXYNOS5_PHYHSIC_TUNE2			(0x24)
+
+#define EXYNOS5_PHYHSIC_REFCLKSEL_MASK		(0x3)
+#define EXYNOS5_PHYHSIC_REFCLKSEL		(0x2 << 23)
+
+#define EXYNOS5_PHYHSIC_REFCLKDIV_MASK		(0x7f)
+#define EXYNOS5_PHYHSIC_REFCLKDIV(_x)		((_x) << 16)
+#define EXYNOS5_PHYHSIC_REFCLKDIV_12		\
+		EXYNOS5_PHYHSIC_REFCLKDIV(0x24)
+#define EXYNOS5_PHYHSIC_REFCLKDIV_15		\
+		EXYNOS5_PHYHSIC_REFCLKDIV(0x1C)
+#define EXYNOS5_PHYHSIC_REFCLKDIV_16		\
+		EXYNOS5_PHYHSIC_REFCLKDIV(0x1A)
+#define EXYNOS5_PHYHSIC_REFCLKDIV_19_2		\
+		EXYNOS5_PHYHSIC_REFCLKDIV(0x15)
+#define EXYNOS5_PHYHSIC_REFCLKDIV_20		\
+		EXYNOS5_PHYHSIC_REFCLKDIV(0x14)
+
+#define EXYNOS5_PHYHSIC_SIDDQ			(0x1 << 6)
+#define EXYNOS5_PHYHSIC_FORCESLEEP		(0x1 << 5)
+#define EXYNOS5_PHYHSIC_FORCESUSPEND		(0x1 << 4)
+#define EXYNOS5_PHYHSIC_WORDINTERFACE		(0x1 << 3)
+#define EXYNOS5_PHYHSIC_UTMISWRST		(0x1 << 2)
+#define EXYNOS5_PHYHSIC_PHYSWRST		(0x1 << 0)
+
+#define EXYNOS5_EHCICTRL			(0x30)
+
+#define EXYNOS5_EHCICTRL_ENAINCRXALIGN		(0x1 << 29)
+#define EXYNOS5_EHCICTRL_ENAINCR4		(0x1 << 28)
+#define EXYNOS5_EHCICTRL_ENAINCR8		(0x1 << 27)
+#define EXYNOS5_EHCICTRL_ENAINCR16		(0x1 << 26)
+
+#define EXYNOS5_OHCICTRL			(0x34)
+
+#define EXYNOS5_OHCICTRL_SUSPLGCY		(0x1 << 3)
+#define EXYNOS5_OHCICTRL_APPSTARTCLK		(0x1 << 2)
+#define EXYNOS5_OHCICTRL_CNTSEL			(0x1 << 1)
+#define EXYNOS5_OHCICTRL_CLKCKTRST		(0x1 << 0)
+
+#define EXYNOS5_PHYOTG				(0x38)
+
+#define EXYNOS5_PHYOTG_PHYLINK_SWRESET		(0x1 << 14)
+#define EXYNOS5_PHYOTG_LINKSWRST_UOTG		(0x1 << 13)
+#define EXYNOS5_PHYOTG_PHY0_SWRST		(0x1 << 12)
+
+#define EXYNOS5_PHYOTG_REFCLKSEL_MASK		(0x3 << 9)
+#define EXYNOS5_PHYOTG_REFCLKSEL(_x)		((_x) << 9)
+#define EXYNOS5_PHYOTG_REFCLKSEL_XTAL		\
+		EXYNOS5_PHYOTG_REFCLKSEL(0x0)
+#define EXYNOS5_PHYOTG_REFCLKSEL_EXTL		\
+		EXYNOS5_PHYOTG_REFCLKSEL(0x1)
+#define EXYNOS5_PHYOTG_REFCLKSEL_CLKCORE	\
+		EXYNOS5_PHYOTG_REFCLKSEL(0x2)
+
+#define EXYNOS5_PHYOTG_IDPULLUP_UOTG		(0x1 << 8)
+#define EXYNOS5_PHYOTG_COMMON_ON		(0x1 << 7)
+
+#define EXYNOS5_PHYOTG_FSEL_MASK		(0x7 << 4)
+#define EXYNOS5_PHYOTG_FSEL(_x)			((_x) << 4)
+
+#define EXYNOS5_PHYOTG_FORCESLEEP		(0x1 << 3)
+#define EXYNOS5_PHYOTG_OTGDISABLE		(0x1 << 2)
+#define EXYNOS5_PHYOTG_SIDDQ_UOTG		(0x1 << 1)
+#define EXYNOS5_PHYOTG_FORCESUSPEND		(0x1 << 0)
+
+#define EXYNOS5_PHYOTG_TUNE			(0x40)
+
 enum samsung_cpu_type {
 	TYPE_S3C64XX,
 	TYPE_EXYNOS4210,
+	TYPE_EXYNOS5250,
 };
 
 /*
@@ -84,6 +195,7 @@ struct samsung_usbphy {
 	void __iomem	*regs;
 	int		ref_clk_freq;
 	int		cpu_type;
+	atomic_t	host_usage;
 };
 
 #define phy_to_sphy(x)		container_of((x), struct samsung_usbphy, phy)
@@ -96,30 +208,175 @@ static int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
 	struct clk *ref_clk;
 	int refclk_freq = 0;
 
-	ref_clk = clk_get(sphy->dev, "xusbxti");
+	if (sphy->cpu_type == TYPE_EXYNOS5250)
+		ref_clk = clk_get(sphy->dev, "ext_xtal");
+	else
+		ref_clk = clk_get(sphy->dev, "xusbxti");
 	if (IS_ERR(ref_clk)) {
 		dev_err(sphy->dev, "Failed to get reference clock\n");
 		return PTR_ERR(ref_clk);
 	}
 
-	switch (clk_get_rate(ref_clk)) {
-	case 12 * MHZ:
-		refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
-		break;
-	case 24 * MHZ:
-		refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
-		break;
-	default:
-	case 48 * MHZ:
-		/* default reference clock */
-		refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
-		break;
+	if (sphy->cpu_type == TYPE_EXYNOS5250) {
+		/* set clock frequency for PLL */
+		switch (clk_get_rate(ref_clk)) {
+		case 96 * 100000:
+			refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_9600K;
+			break;
+		case 10 * MHZ:
+			refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_10M;
+			break;
+		case 12 * MHZ:
+			refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_12M;
+			break;
+		case 192 * 100000:
+			refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_19200K;
+			break;
+		case 20 * MHZ:
+			refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_20M;
+			break;
+		case 50 * MHZ:
+			refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_50M;
+			break;
+		case 24 * MHZ:
+		default:
+			/* default reference clock */
+			refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_24M;
+			break;
+		}
+	} else {
+		switch (clk_get_rate(ref_clk)) {
+		case 12 * MHZ:
+			refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
+			break;
+		case 24 * MHZ:
+			refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
+			break;
+		default:
+		case 48 * MHZ:
+			/* default reference clock */
+			refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
+			break;
+		}
 	}
 	clk_put(ref_clk);
 
 	return refclk_freq;
 }
 
+static int exynos5_phyhost_is_on(void *regs)
+{
+	return (readl(regs + EXYNOS5_PHYHOST) & EXYNOS5_PHYHOST_SIDDQ) ? 0 : 1;
+}
+
+static void samsung_exynos5_usbphy_enable(struct samsung_usbphy *sphy)
+{
+	void __iomem *regs = sphy->regs;
+	u32 phyclk = sphy->ref_clk_freq;
+	u32 phyhost;
+	u32 phyotg;
+	u32 phyhsic;
+	u32 ehcictrl;
+	u32 ohcictrl;
+
+	atomic_inc(&sphy->host_usage);
+
+	if (exynos5_phyhost_is_on(regs)) {
+		dev_info(sphy->dev, "Already power on PHY\n");
+		return;
+	}
+
+	/* Selecting Host/OTG mode; After reset USB2.0PHY_CFG: HOST */
+	if (sphy->plat && sphy->plat->phy_cfg_sel) {
+		if (sphy->plat->type)
+			sphy->plat->phy_cfg_sel(sphy->dev, sphy->plat->type);
+		else
+			sphy->plat->phy_cfg_sel(sphy->dev, TYPE_OTG);
+	}
+
+	/* Host configuration */
+	phyhost = readl(regs + EXYNOS5_PHYHOST);
+
+	/* phy reference clock configuration */
+	phyhost &= ~(EXYNOS5_PHYHOST_FSEL_MASK);
+	phyhost |= EXYNOS5_PHYHOST_FSEL(phyclk);
+
+	/* host phy reset */
+	phyhost &= ~(EXYNOS5_PHYHOST_PHYSWRST |
+			EXYNOS5_PHYHOST_PHYSWRSTALL |
+			EXYNOS5_PHYHOST_SIDDQ |
+			/* Enable normal mode of operation */
+			EXYNOS5_PHYHOST_FORCESUSPEND |
+			EXYNOS5_PHYHOST_FORCESLEEP);
+
+	/* Link reset */
+	phyhost |= (EXYNOS5_PHYHOST_LINKSWRST |
+			EXYNOS5_PHYHOST_UTMISWRST |
+			/* COMMON Block configuration during suspend */
+			EXYNOS5_PHYHOST_COMMONON_N);
+	writel(phyhost, regs + EXYNOS5_PHYHOST);
+	udelay(10);
+	phyhost &= ~(EXYNOS5_PHYHOST_LINKSWRST |
+			EXYNOS5_PHYHOST_UTMISWRST);
+	writel(phyhost, regs + EXYNOS5_PHYHOST);
+
+	/* OTG configuration */
+	phyotg = readl(regs + EXYNOS5_PHYOTG);
+
+	/* phy reference clock configuration */
+	phyotg &= ~(EXYNOS5_PHYOTG_FSEL_MASK);
+	phyotg |= EXYNOS5_PHYOTG_FSEL(phyclk);
+
+	/* Enable normal mode of operation */
+	phyotg &= ~(EXYNOS5_PHYOTG_FORCESUSPEND |
+			EXYNOS5_PHYOTG_SIDDQ_UOTG |
+			EXYNOS5_PHYOTG_FORCESLEEP |
+			EXYNOS5_PHYOTG_REFCLKSEL_MASK |
+			/* COMMON Block configuration during suspend */
+			EXYNOS5_PHYOTG_COMMON_ON);
+
+	/* OTG phy & link reset */
+	phyotg |= (EXYNOS5_PHYOTG_PHY0_SWRST |
+			EXYNOS5_PHYOTG_LINKSWRST_UOTG |
+			EXYNOS5_PHYOTG_PHYLINK_SWRESET |
+			EXYNOS5_PHYOTG_OTGDISABLE |
+			/* Set refclk */
+			EXYNOS5_PHYOTG_REFCLKSEL_CLKCORE);
+
+	writel(phyotg, regs + EXYNOS5_PHYOTG);
+	udelay(10);
+	phyotg &= ~(EXYNOS5_PHYOTG_PHY0_SWRST |
+			EXYNOS5_PHYOTG_LINKSWRST_UOTG	|
+			EXYNOS5_PHYOTG_PHYLINK_SWRESET);
+	writel(phyotg, regs + EXYNOS5_PHYOTG);
+
+	/* HSIC phy configuration */
+	phyhsic = (EXYNOS5_PHYHSIC_REFCLKDIV_12 |
+			EXYNOS5_PHYHSIC_REFCLKSEL |
+			EXYNOS5_PHYHSIC_PHYSWRST);
+	writel(phyhsic, regs + EXYNOS5_PHYHSIC1);
+	writel(phyhsic, regs + EXYNOS5_PHYHSIC2);
+	udelay(10);
+	phyhsic &= ~(EXYNOS5_PHYHSIC_PHYSWRST);
+	writel(phyhsic, regs + EXYNOS5_PHYHSIC1);
+	writel(phyhsic, regs + EXYNOS5_PHYHSIC2);
+
+	udelay(80);
+
+	/* enable EHCI DMA burst */
+	ehcictrl = readl(regs + EXYNOS5_EHCICTRL);
+	ehcictrl |= (EXYNOS5_EHCICTRL_ENAINCRXALIGN |
+				EXYNOS5_EHCICTRL_ENAINCR4 |
+				EXYNOS5_EHCICTRL_ENAINCR8 |
+				EXYNOS5_EHCICTRL_ENAINCR16);
+	writel(ehcictrl, regs + EXYNOS5_EHCICTRL);
+
+	/* set ohci_suspend_on_n */
+	ohcictrl = readl(regs + EXYNOS5_OHCICTRL);
+	ohcictrl |= EXYNOS5_OHCICTRL_SUSPLGCY;
+	writel(ohcictrl, regs + EXYNOS5_OHCICTRL);
+}
+
 static void samsung_usbphy_enable(struct samsung_usbphy *sphy)
 {
 	void __iomem *regs = sphy->regs;
@@ -155,6 +412,41 @@ static void samsung_usbphy_enable(struct samsung_usbphy *sphy)
 	writel(rstcon, regs + S3C_RSTCON);
 }
 
+static void samsung_exynos5_usbphy_disable(struct samsung_usbphy *sphy)
+{
+	void __iomem *regs = sphy->regs;
+	u32 phyhost;
+	u32 phyotg;
+	u32 phyhsic;
+
+	if (atomic_dec_return(&sphy->host_usage) > 0) {
+		dev_info(sphy->dev, "still being used\n");
+		return;
+	}
+
+	phyhsic = (EXYNOS5_PHYHSIC_REFCLKDIV_12 |
+			EXYNOS5_PHYHSIC_REFCLKSEL |
+			EXYNOS5_PHYHSIC_SIDDQ |
+			EXYNOS5_PHYHSIC_FORCESLEEP |
+			EXYNOS5_PHYHSIC_FORCESUSPEND);
+	writel(phyhsic, regs + EXYNOS5_PHYHSIC1);
+	writel(phyhsic, regs + EXYNOS5_PHYHSIC2);
+
+	phyhost = readl(regs + EXYNOS5_PHYHOST);
+	phyhost |= (EXYNOS5_PHYHOST_SIDDQ |
+			EXYNOS5_PHYHOST_FORCESUSPEND |
+			EXYNOS5_PHYHOST_FORCESLEEP |
+			EXYNOS5_PHYHOST_PHYSWRST |
+			EXYNOS5_PHYHOST_PHYSWRSTALL);
+	writel(phyhost, regs + EXYNOS5_PHYHOST);
+
+	phyotg = readl(regs + EXYNOS5_PHYOTG);
+	phyotg |= (EXYNOS5_PHYOTG_FORCESUSPEND |
+			EXYNOS5_PHYOTG_SIDDQ_UOTG |
+			EXYNOS5_PHYOTG_FORCESLEEP);
+	writel(phyotg, regs + EXYNOS5_PHYOTG);
+}
+
 static void samsung_usbphy_disable(struct samsung_usbphy *sphy)
 {
 	void __iomem *regs = sphy->regs;
@@ -194,11 +486,18 @@ static int samsung_usbphy_init(struct usb_phy *phy)
 	}
 
 	/* Disable phy isolation */
-	if (sphy->plat && sphy->plat->pmu_isolation)
-		sphy->plat->pmu_isolation(false);
+	if (sphy->plat && sphy->plat->pmu_isolation) {
+		if (sphy->plat->type)
+			sphy->plat->pmu_isolation(false, sphy->plat->type);
+		else
+			sphy->plat->pmu_isolation(false, TYPE_OTG);
+	}
 
 	/* Initialize usb phy registers */
-	samsung_usbphy_enable(sphy);
+	if (sphy->cpu_type == TYPE_EXYNOS5250)
+		samsung_exynos5_usbphy_enable(sphy);
+	else
+		samsung_usbphy_enable(sphy);
 
 	/* Disable the phy clock */
 	clk_disable_unprepare(sphy->clk);
@@ -220,11 +519,18 @@ static void samsung_usbphy_shutdown(struct usb_phy *phy)
 	}
 
 	/* De-initialize usb phy registers */
-	samsung_usbphy_disable(sphy);
+	if (sphy->cpu_type == TYPE_EXYNOS5250)
+		samsung_exynos5_usbphy_disable(sphy);
+	else
+		samsung_usbphy_disable(sphy);
 
 	/* Enable phy isolation */
-	if (sphy->plat && sphy->plat->pmu_isolation)
-		sphy->plat->pmu_isolation(true);
+	if (sphy->plat && sphy->plat->pmu_isolation) {
+		if (sphy->plat->type)
+			sphy->plat->pmu_isolation(true, sphy->plat->type);
+		else
+			sphy->plat->pmu_isolation(true, TYPE_OTG);
+	}
 
 	clk_disable_unprepare(sphy->clk);
 }
@@ -277,16 +583,9 @@ static int __devinit samsung_usbphy_probe(struct platform_device *pdev)
 	if (!sphy)
 		return -ENOMEM;
 
-	clk = devm_clk_get(dev, "otg");
-	if (IS_ERR(clk)) {
-		dev_err(dev, "Failed to get otg clock\n");
-		return PTR_ERR(clk);
-	}
-
 	sphy->dev		= &pdev->dev;
 	sphy->plat		= pdata;
 	sphy->regs		= phy_base;
-	sphy->clk		= clk;
 	sphy->phy.dev		= sphy->dev;
 	sphy->phy.label		= "samsung-usbphy";
 	sphy->phy.init		= samsung_usbphy_init;
@@ -294,6 +593,17 @@ static int __devinit samsung_usbphy_probe(struct platform_device *pdev)
 	sphy->cpu_type		= samsung_usbphy_get_driver_data(pdev);
 	sphy->ref_clk_freq	= samsung_usbphy_get_refclk_freq(sphy);
 
+	if (sphy->cpu_type == TYPE_EXYNOS5250)
+		clk = devm_clk_get(dev, "usbhost");
+	else
+		clk = devm_clk_get(dev, "otg");
+	if (IS_ERR(clk)) {
+		dev_err(dev, "Failed to get otg clock\n");
+		return PTR_ERR(clk);
+	}
+
+	sphy->clk = clk;
+
 	ret = usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB2);
 	return ret;
 }
@@ -315,6 +625,9 @@ static const struct of_device_id samsung_usbphy_dt_match[] = {
 	}, {
 		.compatible = "samsung,exynos4210-usbphy",
 		.data = (void *)TYPE_EXYNOS4210,
+	}, {
+		.compatible = "samsung,exynos5250-usbphy",
+		.data = (void *)TYPE_EXYNOS5250,
 	},
 	{},
 };
@@ -330,6 +643,9 @@ static struct platform_device_id samsung_usbphy_driver_ids[] = {
 	}, {
 		.name		= "exynos4210-usbphy",
 		.driver_data	= TYPE_EXYNOS4210,
+	}, {
+		.name		= "exynos5250-usbphy",
+		.driver_data	= TYPE_EXYNOS5250,
 	},
 	{},
 };
diff --git a/include/linux/platform_data/samsung-usbphy.h b/include/linux/platform_data/samsung-usbphy.h
index 1bd24cb..364a38a 100644
--- a/include/linux/platform_data/samsung-usbphy.h
+++ b/include/linux/platform_data/samsung-usbphy.h
@@ -18,8 +18,14 @@
  * samsung_usbphy_data - Platform data for USB PHY driver.
  * @pmu_isolation: Function to control usb phy isolation in PMU.
  */
+enum phy_type {
+	TYPE_OTG,
+	TYPE_HOST,
+};
+
 struct samsung_usbphy_data {
-	void (*pmu_isolation)(int on);
+	void (*pmu_isolation)(int on, int phy_type);
+	int type;
 };
 
 extern void samsung_usbphy_set_pdata(struct samsung_usbphy_data *pd);
-- 
1.7.6.5

Re: [PATCH 1/4 v2] usb: phy: samsung: Add host phy support to samsung-phy driver

[Jingoo Han]

On Wednesday, October 10, 2012 7:43 PM Vivek Gautam wrote
> 
> This patch adds host phy support to samsung-usbphy.c and
> further adds support for samsung's exynos5250 usb-phy.
> 
> Signed-off-by: Vivek Gautam <gautam.vivek-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
> ---
>  arch/arm/mach-exynos/setup-usb-phy.c         |    2 +-
>  arch/arm/mach-s3c64xx/setup-usb-phy.c        |    2 +-
>  arch/arm/plat-samsung/include/plat/usb-phy.h |    2 +-
>  drivers/usb/phy/Kconfig                      |    1 -
>  drivers/usb/phy/samsung-usbphy.c             |  368 ++++++++++++++++++++++++--
>  include/linux/platform_data/samsung-usbphy.h |    8 +-
>  6 files changed, 352 insertions(+), 31 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
> index 1c62d20..be6cd4f 100644
> --- a/arch/arm/mach-exynos/setup-usb-phy.c
> +++ b/arch/arm/mach-exynos/setup-usb-phy.c
> @@ -222,7 +222,7 @@ int s5p_usb_phy_exit(struct platform_device *pdev, int type)
>  	return -EINVAL;
>  }
> 
> -void s5p_usb_phy_pmu_isolation(int on)
> +void s5p_usb_phy_pmu_isolation(int on, int type)
>  {
>  	if (on) {
>  		writel(readl(S5P_USBDEVICE_PHY_CONTROL)
> diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
> index 3aee778..b7d1d95 100644
> --- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
> +++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
> @@ -13,7 +13,7 @@
>  #include <mach/map.h>
>  #include <mach/regs-sys.h>
> 
> -void s5p_usb_phy_pmu_isolation(int on)
> +void s5p_usb_phy_pmu_isolation(int on, int type)
>  {
>  	if (on) {
>  		writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK,
> diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
> index 165ffe7..7a4a959 100644
> --- a/arch/arm/plat-samsung/include/plat/usb-phy.h
> +++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
> @@ -18,6 +18,6 @@ enum s5p_usb_phy_type {
> 
>  extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
>  extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
> -extern void s5p_usb_phy_pmu_isolation(int on);
> +extern void s5p_usb_phy_pmu_isolation(int on, int type);
> 
>  #endif /* __PLAT_SAMSUNG_USB_PHY_H */
> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
> index 313685f..1ce5b32 100644
> --- a/drivers/usb/phy/Kconfig
> +++ b/drivers/usb/phy/Kconfig
> @@ -35,7 +35,6 @@ config MV_U3D_PHY
> 
>  config SAMSUNG_USBPHY
>  	bool "Samsung USB PHY controller Driver"
> -	depends on USB_S3C_HSOTG
>  	select USB_OTG_UTILS
>  	help
>  	  Enable this to support Samsung USB phy controller for samsung
> diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c
> index ee2dee0..bd6a5e8 100644
> --- a/drivers/usb/phy/samsung-usbphy.c
> +++ b/drivers/usb/phy/samsung-usbphy.c
> @@ -61,9 +61,120 @@
>  #define MHZ (1000*1000)
>  #endif


How about using exact name for the definition, as possible?
PHY SFRs are defined in Exynos5250 and Exynos5410:
    HOSTPHYCTRL0 0x0000
    HOSTPHYTUNE0 0x0004
    HSICPHYCTRL1 0x0010
    HSICPHYTUNE1 0x0014
    HSICPHYCTRL2 0x0020
    HSICPHYTUNE2 0x0024
    HOSTEHCICTRL 0x0030
    HOSTOHCICTRL 0x0034
    USBOTG_SYS 0x0038
    USBOTG_TUNE 0x0040

It would be better to use 'EXYNOS5_PHY_' as the common prefix.

> 
> +/* EXYNOS5 */
> +#define EXYNOS5_PHYHOST				(0x00)

EXYNOS5_PHY_HOST_CTRL0???


> +
> +#define EXYNOS5_PHYHOST_PHYSWRSTALL		(0x1 << 31)
> +
> +#define EXYNOS5_PHYHOST_REFCLKSEL_MASK		(0x3)
> +#define EXYNOS5_PHYHOST_REFCLKSEL(_x)		((_x) << 19)
> +#define EXYNOS5_PHYHOST_REFCLKSEL_XTAL		\
> +		EXYNOS5_PHYHOST_REFCLKSEL(0x0)
> +#define EXYNOS5_PHYHOST_REFCLKSEL_EXTL		\
> +		EXYNOS5_PHYHOST_REFCLKSEL(0x1)
> +#define EXYNOS5_PHYHOST_REFCLKSEL_CLKCORE	\
> +		EXYNOS5_PHYHOST_REFCLKSEL(0x2)
> +
> +#define EXYNOS5_PHYHOST_FSEL_MASK		(0x7 << 16)
> +#define EXYNOS5_PHYHOST_FSEL(_x)		((_x) << 16)
> +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_50M		(0x7)
> +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_24M		(0x5)
> +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_20M		(0x4)
> +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_19200K	(0x3)
> +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_12M		(0x2)
> +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_10M		(0x1)
> +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_9600K	(0x0)
> +
> +#define EXYNOS5_PHYHOST_TESTBURNIN		(0x1 << 11)
> +#define EXYNOS5_PHYHOST_RETENABLE		(0x1 << 10)
> +#define EXYNOS5_PHYHOST_COMMONON_N		(0x1 << 9)
> +#define EXYNOS5_PHYHOST_SIDDQ			(0x1 << 6)
> +#define EXYNOS5_PHYHOST_FORCESLEEP		(0x1 << 5)
> +#define EXYNOS5_PHYHOST_FORCESUSPEND		(0x1 << 4)
> +#define EXYNOS5_PHYHOST_WORDINTERFACE		(0x1 << 3)
> +#define EXYNOS5_PHYHOST_UTMISWRST		(0x1 << 2)
> +#define EXYNOS5_PHYHOST_LINKSWRST		(0x1 << 1)
> +#define EXYNOS5_PHYHOST_PHYSWRST		(0x1 << 0)
> +
> +#define EXYNOS5_PHYHOST_TUNE0			(0x04)

EXYNOS5_PHY_HOST_TUNE0?

> +
> +#define EXYNOS5_PHYHSIC1			(0x10)

EXYNOS5_PHY_HSIC_CTRL1?

> +
> +#define EXYNOS5_PHYHSIC_TUNE1			(0x14)

EXYNOS5_PHY_HSIC_TUNE1?

> +
> +#define EXYNOS5_PHYHSIC2			(0x20)

EXYNOS5_PHY_HSIC_CTRL2 ?

> +
> +#define EXYNOS5_PHYHSIC_TUNE2			(0x24)

EXYNOS5_PHY_HSIC_TUNE2 ?

> +
> +#define EXYNOS5_PHYHSIC_REFCLKSEL_MASK		(0x3)
> +#define EXYNOS5_PHYHSIC_REFCLKSEL		(0x2 << 23)
> +
> +#define EXYNOS5_PHYHSIC_REFCLKDIV_MASK		(0x7f)
> +#define EXYNOS5_PHYHSIC_REFCLKDIV(_x)		((_x) << 16)
> +#define EXYNOS5_PHYHSIC_REFCLKDIV_12		\
> +		EXYNOS5_PHYHSIC_REFCLKDIV(0x24)
> +#define EXYNOS5_PHYHSIC_REFCLKDIV_15		\
> +		EXYNOS5_PHYHSIC_REFCLKDIV(0x1C)
> +#define EXYNOS5_PHYHSIC_REFCLKDIV_16		\
> +		EXYNOS5_PHYHSIC_REFCLKDIV(0x1A)
> +#define EXYNOS5_PHYHSIC_REFCLKDIV_19_2		\
> +		EXYNOS5_PHYHSIC_REFCLKDIV(0x15)
> +#define EXYNOS5_PHYHSIC_REFCLKDIV_20		\
> +		EXYNOS5_PHYHSIC_REFCLKDIV(0x14)
> +
> +#define EXYNOS5_PHYHSIC_SIDDQ			(0x1 << 6)
> +#define EXYNOS5_PHYHSIC_FORCESLEEP		(0x1 << 5)
> +#define EXYNOS5_PHYHSIC_FORCESUSPEND		(0x1 << 4)
> +#define EXYNOS5_PHYHSIC_WORDINTERFACE		(0x1 << 3)
> +#define EXYNOS5_PHYHSIC_UTMISWRST		(0x1 << 2)
> +#define EXYNOS5_PHYHSIC_PHYSWRST		(0x1 << 0)
> +
> +#define EXYNOS5_EHCICTRL			(0x30)

EXYNOS5_PHY_HOST_EHCICTRL ?

> +
> +#define EXYNOS5_EHCICTRL_ENAINCRXALIGN		(0x1 << 29)
> +#define EXYNOS5_EHCICTRL_ENAINCR4		(0x1 << 28)
> +#define EXYNOS5_EHCICTRL_ENAINCR8		(0x1 << 27)
> +#define EXYNOS5_EHCICTRL_ENAINCR16		(0x1 << 26)
> +
> +#define EXYNOS5_OHCICTRL			(0x34)

EXYNOS5_PHY_HOST_OHCICTRL ?

> +
> +#define EXYNOS5_OHCICTRL_SUSPLGCY		(0x1 << 3)
> +#define EXYNOS5_OHCICTRL_APPSTARTCLK		(0x1 << 2)
> +#define EXYNOS5_OHCICTRL_CNTSEL			(0x1 << 1)
> +#define EXYNOS5_OHCICTRL_CLKCKTRST		(0x1 << 0)
> +
> +#define EXYNOS5_PHYOTG				(0x38)

EXYNOS5_PHY_OTG_TUNE ?

> +
> +#define EXYNOS5_PHYOTG_PHYLINK_SWRESET		(0x1 << 14)
> +#define EXYNOS5_PHYOTG_LINKSWRST_UOTG		(0x1 << 13)
> +#define EXYNOS5_PHYOTG_PHY0_SWRST		(0x1 << 12)
> +
> +#define EXYNOS5_PHYOTG_REFCLKSEL_MASK		(0x3 << 9)
> +#define EXYNOS5_PHYOTG_REFCLKSEL(_x)		((_x) << 9)
> +#define EXYNOS5_PHYOTG_REFCLKSEL_XTAL		\
> +		EXYNOS5_PHYOTG_REFCLKSEL(0x0)
> +#define EXYNOS5_PHYOTG_REFCLKSEL_EXTL		\
> +		EXYNOS5_PHYOTG_REFCLKSEL(0x1)
> +#define EXYNOS5_PHYOTG_REFCLKSEL_CLKCORE	\
> +		EXYNOS5_PHYOTG_REFCLKSEL(0x2)
> +
> +#define EXYNOS5_PHYOTG_IDPULLUP_UOTG		(0x1 << 8)
> +#define EXYNOS5_PHYOTG_COMMON_ON		(0x1 << 7)
> +
> +#define EXYNOS5_PHYOTG_FSEL_MASK		(0x7 << 4)
> +#define EXYNOS5_PHYOTG_FSEL(_x)			((_x) << 4)
> +
> +#define EXYNOS5_PHYOTG_FORCESLEEP		(0x1 << 3)
> +#define EXYNOS5_PHYOTG_OTGDISABLE		(0x1 << 2)
> +#define EXYNOS5_PHYOTG_SIDDQ_UOTG		(0x1 << 1)
> +#define EXYNOS5_PHYOTG_FORCESUSPEND		(0x1 << 0)
> +
> +#define EXYNOS5_PHYOTG_TUNE			(0x40)

EXYNOS5_PHY_OTG_TUNE ?

> +
>  enum samsung_cpu_type {
>  	TYPE_S3C64XX,
>  	TYPE_EXYNOS4210,
> +	TYPE_EXYNOS5250,
>  };
> 
>  /*
> @@ -84,6 +195,7 @@ struct samsung_usbphy {
>  	void __iomem	*regs;
>  	int		ref_clk_freq;
>  	int		cpu_type;
> +	atomic_t	host_usage;
>  };
> 
>  #define phy_to_sphy(x)		container_of((x), struct samsung_usbphy, phy)
> @@ -96,30 +208,175 @@ static int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
>  	struct clk *ref_clk;
>  	int refclk_freq = 0;
> 
> -	ref_clk = clk_get(sphy->dev, "xusbxti");
> +	if (sphy->cpu_type == TYPE_EXYNOS5250)
> +		ref_clk = clk_get(sphy->dev, "ext_xtal");
> +	else
> +		ref_clk = clk_get(sphy->dev, "xusbxti");
>  	if (IS_ERR(ref_clk)) {
>  		dev_err(sphy->dev, "Failed to get reference clock\n");
>  		return PTR_ERR(ref_clk);
>  	}
> 
> -	switch (clk_get_rate(ref_clk)) {
> -	case 12 * MHZ:
> -		refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
> -		break;
> -	case 24 * MHZ:
> -		refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
> -		break;
> -	default:
> -	case 48 * MHZ:
> -		/* default reference clock */
> -		refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
> -		break;
> +	if (sphy->cpu_type == TYPE_EXYNOS5250) {
> +		/* set clock frequency for PLL */
> +		switch (clk_get_rate(ref_clk)) {
> +		case 96 * 100000:
> +			refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_9600K;
> +			break;
> +		case 10 * MHZ:
> +			refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_10M;
> +			break;
> +		case 12 * MHZ:
> +			refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_12M;
> +			break;
> +		case 192 * 100000:
> +			refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_19200K;
> +			break;
> +		case 20 * MHZ:
> +			refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_20M;
> +			break;
> +		case 50 * MHZ:
> +			refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_50M;
> +			break;
> +		case 24 * MHZ:
> +		default:
> +			/* default reference clock */
> +			refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_24M;
> +			break;
> +		}
> +	} else {
> +		switch (clk_get_rate(ref_clk)) {
> +		case 12 * MHZ:
> +			refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
> +			break;
> +		case 24 * MHZ:
> +			refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
> +			break;
> +		default:
> +		case 48 * MHZ:
> +			/* default reference clock */
> +			refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
> +			break;
> +		}
>  	}
>  	clk_put(ref_clk);
> 
>  	return refclk_freq;
>  }
> 
> +static int exynos5_phyhost_is_on(void *regs)
> +{
> +	return (readl(regs + EXYNOS5_PHYHOST) & EXYNOS5_PHYHOST_SIDDQ) ? 0 : 1;
> +}
> +
> +static void samsung_exynos5_usbphy_enable(struct samsung_usbphy *sphy)
> +{
> +	void __iomem *regs = sphy->regs;
> +	u32 phyclk = sphy->ref_clk_freq;
> +	u32 phyhost;
> +	u32 phyotg;
> +	u32 phyhsic;
> +	u32 ehcictrl;
> +	u32 ohcictrl;
> +
> +	atomic_inc(&sphy->host_usage);
> +
> +	if (exynos5_phyhost_is_on(regs)) {
> +		dev_info(sphy->dev, "Already power on PHY\n");
> +		return;
> +	}
> +
> +	/* Selecting Host/OTG mode; After reset USB2.0PHY_CFG: HOST */
> +	if (sphy->plat && sphy->plat->phy_cfg_sel) {
> +		if (sphy->plat->type)
> +			sphy->plat->phy_cfg_sel(sphy->dev, sphy->plat->type);
> +		else
> +			sphy->plat->phy_cfg_sel(sphy->dev, TYPE_OTG);
> +	}
> +
> +	/* Host configuration */
> +	phyhost = readl(regs + EXYNOS5_PHYHOST);
> +
> +	/* phy reference clock configuration */
> +	phyhost &= ~(EXYNOS5_PHYHOST_FSEL_MASK);
> +	phyhost |= EXYNOS5_PHYHOST_FSEL(phyclk);
> +
> +	/* host phy reset */
> +	phyhost &= ~(EXYNOS5_PHYHOST_PHYSWRST |
> +			EXYNOS5_PHYHOST_PHYSWRSTALL |
> +			EXYNOS5_PHYHOST_SIDDQ |
> +			/* Enable normal mode of operation */
> +			EXYNOS5_PHYHOST_FORCESUSPEND |
> +			EXYNOS5_PHYHOST_FORCESLEEP);
> +
> +	/* Link reset */
> +	phyhost |= (EXYNOS5_PHYHOST_LINKSWRST |
> +			EXYNOS5_PHYHOST_UTMISWRST |
> +			/* COMMON Block configuration during suspend */
> +			EXYNOS5_PHYHOST_COMMONON_N);
> +	writel(phyhost, regs + EXYNOS5_PHYHOST);
> +	udelay(10);
> +	phyhost &= ~(EXYNOS5_PHYHOST_LINKSWRST |
> +			EXYNOS5_PHYHOST_UTMISWRST);
> +	writel(phyhost, regs + EXYNOS5_PHYHOST);
> +
> +	/* OTG configuration */
> +	phyotg = readl(regs + EXYNOS5_PHYOTG);
> +
> +	/* phy reference clock configuration */
> +	phyotg &= ~(EXYNOS5_PHYOTG_FSEL_MASK);
> +	phyotg |= EXYNOS5_PHYOTG_FSEL(phyclk);
> +
> +	/* Enable normal mode of operation */
> +	phyotg &= ~(EXYNOS5_PHYOTG_FORCESUSPEND |
> +			EXYNOS5_PHYOTG_SIDDQ_UOTG |
> +			EXYNOS5_PHYOTG_FORCESLEEP |
> +			EXYNOS5_PHYOTG_REFCLKSEL_MASK |
> +			/* COMMON Block configuration during suspend */
> +			EXYNOS5_PHYOTG_COMMON_ON);
> +
> +	/* OTG phy & link reset */
> +	phyotg |= (EXYNOS5_PHYOTG_PHY0_SWRST |
> +			EXYNOS5_PHYOTG_LINKSWRST_UOTG |
> +			EXYNOS5_PHYOTG_PHYLINK_SWRESET |
> +			EXYNOS5_PHYOTG_OTGDISABLE |
> +			/* Set refclk */
> +			EXYNOS5_PHYOTG_REFCLKSEL_CLKCORE);
> +
> +	writel(phyotg, regs + EXYNOS5_PHYOTG);
> +	udelay(10);
> +	phyotg &= ~(EXYNOS5_PHYOTG_PHY0_SWRST |
> +			EXYNOS5_PHYOTG_LINKSWRST_UOTG	|
> +			EXYNOS5_PHYOTG_PHYLINK_SWRESET);
> +	writel(phyotg, regs + EXYNOS5_PHYOTG);
> +
> +	/* HSIC phy configuration */
> +	phyhsic = (EXYNOS5_PHYHSIC_REFCLKDIV_12 |
> +			EXYNOS5_PHYHSIC_REFCLKSEL |
> +			EXYNOS5_PHYHSIC_PHYSWRST);
> +	writel(phyhsic, regs + EXYNOS5_PHYHSIC1);
> +	writel(phyhsic, regs + EXYNOS5_PHYHSIC2);
> +	udelay(10);
> +	phyhsic &= ~(EXYNOS5_PHYHSIC_PHYSWRST);
> +	writel(phyhsic, regs + EXYNOS5_PHYHSIC1);
> +	writel(phyhsic, regs + EXYNOS5_PHYHSIC2);
> +
> +	udelay(80);
> +
> +	/* enable EHCI DMA burst */
> +	ehcictrl = readl(regs + EXYNOS5_EHCICTRL);
> +	ehcictrl |= (EXYNOS5_EHCICTRL_ENAINCRXALIGN |
> +				EXYNOS5_EHCICTRL_ENAINCR4 |
> +				EXYNOS5_EHCICTRL_ENAINCR8 |
> +				EXYNOS5_EHCICTRL_ENAINCR16);
> +	writel(ehcictrl, regs + EXYNOS5_EHCICTRL);
> +
> +	/* set ohci_suspend_on_n */
> +	ohcictrl = readl(regs + EXYNOS5_OHCICTRL);
> +	ohcictrl |= EXYNOS5_OHCICTRL_SUSPLGCY;
> +	writel(ohcictrl, regs + EXYNOS5_OHCICTRL);
> +}
> +
>  static void samsung_usbphy_enable(struct samsung_usbphy *sphy)
>  {
>  	void __iomem *regs = sphy->regs;
> @@ -155,6 +412,41 @@ static void samsung_usbphy_enable(struct samsung_usbphy *sphy)
>  	writel(rstcon, regs + S3C_RSTCON);
>  }
> 
> +static void samsung_exynos5_usbphy_disable(struct samsung_usbphy *sphy)
> +{
> +	void __iomem *regs = sphy->regs;
> +	u32 phyhost;
> +	u32 phyotg;
> +	u32 phyhsic;
> +
> +	if (atomic_dec_return(&sphy->host_usage) > 0) {
> +		dev_info(sphy->dev, "still being used\n");
> +		return;
> +	}
> +
> +	phyhsic = (EXYNOS5_PHYHSIC_REFCLKDIV_12 |
> +			EXYNOS5_PHYHSIC_REFCLKSEL |
> +			EXYNOS5_PHYHSIC_SIDDQ |
> +			EXYNOS5_PHYHSIC_FORCESLEEP |
> +			EXYNOS5_PHYHSIC_FORCESUSPEND);
> +	writel(phyhsic, regs + EXYNOS5_PHYHSIC1);
> +	writel(phyhsic, regs + EXYNOS5_PHYHSIC2);
> +
> +	phyhost = readl(regs + EXYNOS5_PHYHOST);
> +	phyhost |= (EXYNOS5_PHYHOST_SIDDQ |
> +			EXYNOS5_PHYHOST_FORCESUSPEND |
> +			EXYNOS5_PHYHOST_FORCESLEEP |
> +			EXYNOS5_PHYHOST_PHYSWRST |
> +			EXYNOS5_PHYHOST_PHYSWRSTALL);
> +	writel(phyhost, regs + EXYNOS5_PHYHOST);
> +
> +	phyotg = readl(regs + EXYNOS5_PHYOTG);
> +	phyotg |= (EXYNOS5_PHYOTG_FORCESUSPEND |
> +			EXYNOS5_PHYOTG_SIDDQ_UOTG |
> +			EXYNOS5_PHYOTG_FORCESLEEP);
> +	writel(phyotg, regs + EXYNOS5_PHYOTG);
> +}
> +
>  static void samsung_usbphy_disable(struct samsung_usbphy *sphy)
>  {
>  	void __iomem *regs = sphy->regs;
> @@ -194,11 +486,18 @@ static int samsung_usbphy_init(struct usb_phy *phy)
>  	}
> 
>  	/* Disable phy isolation */
> -	if (sphy->plat && sphy->plat->pmu_isolation)
> -		sphy->plat->pmu_isolation(false);
> +	if (sphy->plat && sphy->plat->pmu_isolation) {
> +		if (sphy->plat->type)
> +			sphy->plat->pmu_isolation(false, sphy->plat->type);
> +		else
> +			sphy->plat->pmu_isolation(false, TYPE_OTG);
> +	}
> 
>  	/* Initialize usb phy registers */
> -	samsung_usbphy_enable(sphy);
> +	if (sphy->cpu_type == TYPE_EXYNOS5250)
> +		samsung_exynos5_usbphy_enable(sphy);
> +	else
> +		samsung_usbphy_enable(sphy);
> 
>  	/* Disable the phy clock */
>  	clk_disable_unprepare(sphy->clk);
> @@ -220,11 +519,18 @@ static void samsung_usbphy_shutdown(struct usb_phy *phy)
>  	}
> 
>  	/* De-initialize usb phy registers */
> -	samsung_usbphy_disable(sphy);
> +	if (sphy->cpu_type == TYPE_EXYNOS5250)
> +		samsung_exynos5_usbphy_disable(sphy);
> +	else
> +		samsung_usbphy_disable(sphy);
> 
>  	/* Enable phy isolation */
> -	if (sphy->plat && sphy->plat->pmu_isolation)
> -		sphy->plat->pmu_isolation(true);
> +	if (sphy->plat && sphy->plat->pmu_isolation) {
> +		if (sphy->plat->type)
> +			sphy->plat->pmu_isolation(true, sphy->plat->type);
> +		else
> +			sphy->plat->pmu_isolation(true, TYPE_OTG);
> +	}
> 
>  	clk_disable_unprepare(sphy->clk);
>  }
> @@ -277,16 +583,9 @@ static int __devinit samsung_usbphy_probe(struct platform_device *pdev)
>  	if (!sphy)
>  		return -ENOMEM;
> 
> -	clk = devm_clk_get(dev, "otg");
> -	if (IS_ERR(clk)) {
> -		dev_err(dev, "Failed to get otg clock\n");
> -		return PTR_ERR(clk);
> -	}
> -
>  	sphy->dev		= &pdev->dev;
>  	sphy->plat		= pdata;
>  	sphy->regs		= phy_base;
> -	sphy->clk		= clk;
>  	sphy->phy.dev		= sphy->dev;
>  	sphy->phy.label		= "samsung-usbphy";
>  	sphy->phy.init		= samsung_usbphy_init;
> @@ -294,6 +593,17 @@ static int __devinit samsung_usbphy_probe(struct platform_device *pdev)
>  	sphy->cpu_type		= samsung_usbphy_get_driver_data(pdev);
>  	sphy->ref_clk_freq	= samsung_usbphy_get_refclk_freq(sphy);
> 
> +	if (sphy->cpu_type == TYPE_EXYNOS5250)
> +		clk = devm_clk_get(dev, "usbhost");
> +	else
> +		clk = devm_clk_get(dev, "otg");
> +	if (IS_ERR(clk)) {
> +		dev_err(dev, "Failed to get otg clock\n");
> +		return PTR_ERR(clk);
> +	}
> +
> +	sphy->clk = clk;
> +
>  	ret = usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB2);
>  	return ret;
>  }
> @@ -315,6 +625,9 @@ static const struct of_device_id samsung_usbphy_dt_match[] = {
>  	}, {
>  		.compatible = "samsung,exynos4210-usbphy",
>  		.data = (void *)TYPE_EXYNOS4210,
> +	}, {
> +		.compatible = "samsung,exynos5250-usbphy",
> +		.data = (void *)TYPE_EXYNOS5250,
>  	},
>  	{},
>  };
> @@ -330,6 +643,9 @@ static struct platform_device_id samsung_usbphy_driver_ids[] = {
>  	}, {
>  		.name		= "exynos4210-usbphy",
>  		.driver_data	= TYPE_EXYNOS4210,
> +	}, {
> +		.name		= "exynos5250-usbphy",
> +		.driver_data	= TYPE_EXYNOS5250,
>  	},
>  	{},
>  };
> diff --git a/include/linux/platform_data/samsung-usbphy.h b/include/linux/platform_data/samsung-usbphy.h
> index 1bd24cb..364a38a 100644
> --- a/include/linux/platform_data/samsung-usbphy.h
> +++ b/include/linux/platform_data/samsung-usbphy.h
> @@ -18,8 +18,14 @@
>   * samsung_usbphy_data - Platform data for USB PHY driver.
>   * @pmu_isolation: Function to control usb phy isolation in PMU.
>   */
> +enum phy_type {
> +	TYPE_OTG,
> +	TYPE_HOST,
> +};
> +
>  struct samsung_usbphy_data {
> -	void (*pmu_isolation)(int on);
> +	void (*pmu_isolation)(int on, int phy_type);
> +	int type;
>  };
> 
>  extern void samsung_usbphy_set_pdata(struct samsung_usbphy_data *pd);
> --
> 1.7.6.5

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Re: [PATCH 1/4 v2] usb: phy: samsung: Add host phy support to samsung-phy driver

[Vivek Gautam]

HI,

On Mon, Oct 22, 2012 at 10:27 AM, Jingoo Han <jg1.han@samsung.com> wrote:
> On Wednesday, October 10, 2012 7:43 PM Vivek Gautam wrote
>>
>> This patch adds host phy support to samsung-usbphy.c and
>> further adds support for samsung's exynos5250 usb-phy.
>>
>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>> ---
>>  arch/arm/mach-exynos/setup-usb-phy.c         |    2 +-
>>  arch/arm/mach-s3c64xx/setup-usb-phy.c        |    2 +-
>>  arch/arm/plat-samsung/include/plat/usb-phy.h |    2 +-
>>  drivers/usb/phy/Kconfig                      |    1 -
>>  drivers/usb/phy/samsung-usbphy.c             |  368 ++++++++++++++++++++++++--
>>  include/linux/platform_data/samsung-usbphy.h |    8 +-
>>  6 files changed, 352 insertions(+), 31 deletions(-)
>>
>> diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
>> index 1c62d20..be6cd4f 100644
>> --- a/arch/arm/mach-exynos/setup-usb-phy.c
>> +++ b/arch/arm/mach-exynos/setup-usb-phy.c
>> @@ -222,7 +222,7 @@ int s5p_usb_phy_exit(struct platform_device *pdev, int type)
>>       return -EINVAL;
>>  }
>>
>> -void s5p_usb_phy_pmu_isolation(int on)
>> +void s5p_usb_phy_pmu_isolation(int on, int type)
>>  {
>>       if (on) {
>>               writel(readl(S5P_USBDEVICE_PHY_CONTROL)
>> diff --git a/arch/arm/mach-s3c64xx/setup-usb-phy.c b/arch/arm/mach-s3c64xx/setup-usb-phy.c
>> index 3aee778..b7d1d95 100644
>> --- a/arch/arm/mach-s3c64xx/setup-usb-phy.c
>> +++ b/arch/arm/mach-s3c64xx/setup-usb-phy.c
>> @@ -13,7 +13,7 @@
>>  #include <mach/map.h>
>>  #include <mach/regs-sys.h>
>>
>> -void s5p_usb_phy_pmu_isolation(int on)
>> +void s5p_usb_phy_pmu_isolation(int on, int type)
>>  {
>>       if (on) {
>>               writel(readl(S3C64XX_OTHERS) & ~S3C64XX_OTHERS_USBMASK,
>> diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
>> index 165ffe7..7a4a959 100644
>> --- a/arch/arm/plat-samsung/include/plat/usb-phy.h
>> +++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
>> @@ -18,6 +18,6 @@ enum s5p_usb_phy_type {
>>
>>  extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
>>  extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
>> -extern void s5p_usb_phy_pmu_isolation(int on);
>> +extern void s5p_usb_phy_pmu_isolation(int on, int type);
>>
>>  #endif /* __PLAT_SAMSUNG_USB_PHY_H */
>> diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
>> index 313685f..1ce5b32 100644
>> --- a/drivers/usb/phy/Kconfig
>> +++ b/drivers/usb/phy/Kconfig
>> @@ -35,7 +35,6 @@ config MV_U3D_PHY
>>
>>  config SAMSUNG_USBPHY
>>       bool "Samsung USB PHY controller Driver"
>> -     depends on USB_S3C_HSOTG
>>       select USB_OTG_UTILS
>>       help
>>         Enable this to support Samsung USB phy controller for samsung
>> diff --git a/drivers/usb/phy/samsung-usbphy.c b/drivers/usb/phy/samsung-usbphy.c
>> index ee2dee0..bd6a5e8 100644
>> --- a/drivers/usb/phy/samsung-usbphy.c
>> +++ b/drivers/usb/phy/samsung-usbphy.c
>> @@ -61,9 +61,120 @@
>>  #define MHZ (1000*1000)
>>  #endif
>
>
> How about using exact name for the definition, as possible?
> PHY SFRs are defined in Exynos5250 and Exynos5410:
>     HOSTPHYCTRL0 0x0000
>     HOSTPHYTUNE0 0x0004
>     HSICPHYCTRL1 0x0010
>     HSICPHYTUNE1 0x0014
>     HSICPHYCTRL2 0x0020
>     HSICPHYTUNE2 0x0024
>     HOSTEHCICTRL 0x0030
>     HOSTOHCICTRL 0x0034
>     USBOTG_SYS 0x0038
>     USBOTG_TUNE 0x0040
>
Yes, using above suggested names will be good.

> It would be better to use 'EXYNOS5_PHY_' as the common prefix.
>
shall modify these SFRs' names accordingly and resubmit. Thanks for
pointing out.

>>
>> +/* EXYNOS5 */
>> +#define EXYNOS5_PHYHOST                              (0x00)
>
> EXYNOS5_PHY_HOST_CTRL0???
>
shall change this as suggested.
>
>> +
>> +#define EXYNOS5_PHYHOST_PHYSWRSTALL          (0x1 << 31)
>> +
>> +#define EXYNOS5_PHYHOST_REFCLKSEL_MASK               (0x3)
>> +#define EXYNOS5_PHYHOST_REFCLKSEL(_x)                ((_x) << 19)
>> +#define EXYNOS5_PHYHOST_REFCLKSEL_XTAL               \
>> +             EXYNOS5_PHYHOST_REFCLKSEL(0x0)
>> +#define EXYNOS5_PHYHOST_REFCLKSEL_EXTL               \
>> +             EXYNOS5_PHYHOST_REFCLKSEL(0x1)
>> +#define EXYNOS5_PHYHOST_REFCLKSEL_CLKCORE    \
>> +             EXYNOS5_PHYHOST_REFCLKSEL(0x2)
>> +
>> +#define EXYNOS5_PHYHOST_FSEL_MASK            (0x7 << 16)
>> +#define EXYNOS5_PHYHOST_FSEL(_x)             ((_x) << 16)
>> +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_50M              (0x7)
>> +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_24M              (0x5)
>> +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_20M              (0x4)
>> +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_19200K   (0x3)
>> +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_12M              (0x2)
>> +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_10M              (0x1)
>> +#define EXYNOS5_PHYHOST_FSEL_CLKSEL_9600K    (0x0)
>> +
>> +#define EXYNOS5_PHYHOST_TESTBURNIN           (0x1 << 11)
>> +#define EXYNOS5_PHYHOST_RETENABLE            (0x1 << 10)
>> +#define EXYNOS5_PHYHOST_COMMONON_N           (0x1 << 9)
>> +#define EXYNOS5_PHYHOST_SIDDQ                        (0x1 << 6)
>> +#define EXYNOS5_PHYHOST_FORCESLEEP           (0x1 << 5)
>> +#define EXYNOS5_PHYHOST_FORCESUSPEND         (0x1 << 4)
>> +#define EXYNOS5_PHYHOST_WORDINTERFACE                (0x1 << 3)
>> +#define EXYNOS5_PHYHOST_UTMISWRST            (0x1 << 2)
>> +#define EXYNOS5_PHYHOST_LINKSWRST            (0x1 << 1)
>> +#define EXYNOS5_PHYHOST_PHYSWRST             (0x1 << 0)
>> +
>> +#define EXYNOS5_PHYHOST_TUNE0                        (0x04)
>
> EXYNOS5_PHY_HOST_TUNE0?
>
ditto.

>> +
>> +#define EXYNOS5_PHYHSIC1                     (0x10)
>
> EXYNOS5_PHY_HSIC_CTRL1?
>
ditto.

>> +
>> +#define EXYNOS5_PHYHSIC_TUNE1                        (0x14)
>
> EXYNOS5_PHY_HSIC_TUNE1?
>
ditto.

>> +
>> +#define EXYNOS5_PHYHSIC2                     (0x20)
>
> EXYNOS5_PHY_HSIC_CTRL2 ?
>
ditto.

>> +
>> +#define EXYNOS5_PHYHSIC_TUNE2                        (0x24)
>
> EXYNOS5_PHY_HSIC_TUNE2 ?
>
ditto.

>> +
>> +#define EXYNOS5_PHYHSIC_REFCLKSEL_MASK               (0x3)
>> +#define EXYNOS5_PHYHSIC_REFCLKSEL            (0x2 << 23)
>> +
>> +#define EXYNOS5_PHYHSIC_REFCLKDIV_MASK               (0x7f)
>> +#define EXYNOS5_PHYHSIC_REFCLKDIV(_x)                ((_x) << 16)
>> +#define EXYNOS5_PHYHSIC_REFCLKDIV_12         \
>> +             EXYNOS5_PHYHSIC_REFCLKDIV(0x24)
>> +#define EXYNOS5_PHYHSIC_REFCLKDIV_15         \
>> +             EXYNOS5_PHYHSIC_REFCLKDIV(0x1C)
>> +#define EXYNOS5_PHYHSIC_REFCLKDIV_16         \
>> +             EXYNOS5_PHYHSIC_REFCLKDIV(0x1A)
>> +#define EXYNOS5_PHYHSIC_REFCLKDIV_19_2               \
>> +             EXYNOS5_PHYHSIC_REFCLKDIV(0x15)
>> +#define EXYNOS5_PHYHSIC_REFCLKDIV_20         \
>> +             EXYNOS5_PHYHSIC_REFCLKDIV(0x14)
>> +
>> +#define EXYNOS5_PHYHSIC_SIDDQ                        (0x1 << 6)
>> +#define EXYNOS5_PHYHSIC_FORCESLEEP           (0x1 << 5)
>> +#define EXYNOS5_PHYHSIC_FORCESUSPEND         (0x1 << 4)
>> +#define EXYNOS5_PHYHSIC_WORDINTERFACE                (0x1 << 3)
>> +#define EXYNOS5_PHYHSIC_UTMISWRST            (0x1 << 2)
>> +#define EXYNOS5_PHYHSIC_PHYSWRST             (0x1 << 0)
>> +
>> +#define EXYNOS5_EHCICTRL                     (0x30)
>
> EXYNOS5_PHY_HOST_EHCICTRL ?
>
ditto.

>> +
>> +#define EXYNOS5_EHCICTRL_ENAINCRXALIGN               (0x1 << 29)
>> +#define EXYNOS5_EHCICTRL_ENAINCR4            (0x1 << 28)
>> +#define EXYNOS5_EHCICTRL_ENAINCR8            (0x1 << 27)
>> +#define EXYNOS5_EHCICTRL_ENAINCR16           (0x1 << 26)
>> +
>> +#define EXYNOS5_OHCICTRL                     (0x34)
>
> EXYNOS5_PHY_HOST_OHCICTRL ?
>
ditto.

>> +
>> +#define EXYNOS5_OHCICTRL_SUSPLGCY            (0x1 << 3)
>> +#define EXYNOS5_OHCICTRL_APPSTARTCLK         (0x1 << 2)
>> +#define EXYNOS5_OHCICTRL_CNTSEL                      (0x1 << 1)
>> +#define EXYNOS5_OHCICTRL_CLKCKTRST           (0x1 << 0)
>> +
>> +#define EXYNOS5_PHYOTG                               (0x38)
>
> EXYNOS5_PHY_OTG_TUNE ?
>
ditto.

>> +
>> +#define EXYNOS5_PHYOTG_PHYLINK_SWRESET               (0x1 << 14)
>> +#define EXYNOS5_PHYOTG_LINKSWRST_UOTG                (0x1 << 13)
>> +#define EXYNOS5_PHYOTG_PHY0_SWRST            (0x1 << 12)
>> +
>> +#define EXYNOS5_PHYOTG_REFCLKSEL_MASK                (0x3 << 9)
>> +#define EXYNOS5_PHYOTG_REFCLKSEL(_x)         ((_x) << 9)
>> +#define EXYNOS5_PHYOTG_REFCLKSEL_XTAL                \
>> +             EXYNOS5_PHYOTG_REFCLKSEL(0x0)
>> +#define EXYNOS5_PHYOTG_REFCLKSEL_EXTL                \
>> +             EXYNOS5_PHYOTG_REFCLKSEL(0x1)
>> +#define EXYNOS5_PHYOTG_REFCLKSEL_CLKCORE     \
>> +             EXYNOS5_PHYOTG_REFCLKSEL(0x2)
>> +
>> +#define EXYNOS5_PHYOTG_IDPULLUP_UOTG         (0x1 << 8)
>> +#define EXYNOS5_PHYOTG_COMMON_ON             (0x1 << 7)
>> +
>> +#define EXYNOS5_PHYOTG_FSEL_MASK             (0x7 << 4)
>> +#define EXYNOS5_PHYOTG_FSEL(_x)                      ((_x) << 4)
>> +
>> +#define EXYNOS5_PHYOTG_FORCESLEEP            (0x1 << 3)
>> +#define EXYNOS5_PHYOTG_OTGDISABLE            (0x1 << 2)
>> +#define EXYNOS5_PHYOTG_SIDDQ_UOTG            (0x1 << 1)
>> +#define EXYNOS5_PHYOTG_FORCESUSPEND          (0x1 << 0)
>> +
>> +#define EXYNOS5_PHYOTG_TUNE                  (0x40)
>
> EXYNOS5_PHY_OTG_TUNE ?
>
ditto.

>> +
>>  enum samsung_cpu_type {
>>       TYPE_S3C64XX,
>>       TYPE_EXYNOS4210,
>> +     TYPE_EXYNOS5250,
>>  };
>>
>>  /*
>> @@ -84,6 +195,7 @@ struct samsung_usbphy {
>>       void __iomem    *regs;
>>       int             ref_clk_freq;
>>       int             cpu_type;
>> +     atomic_t        host_usage;
>>  };
>>
>>  #define phy_to_sphy(x)               container_of((x), struct samsung_usbphy, phy)
>> @@ -96,30 +208,175 @@ static int samsung_usbphy_get_refclk_freq(struct samsung_usbphy *sphy)
>>       struct clk *ref_clk;
>>       int refclk_freq = 0;
>>
>> -     ref_clk = clk_get(sphy->dev, "xusbxti");
>> +     if (sphy->cpu_type == TYPE_EXYNOS5250)
>> +             ref_clk = clk_get(sphy->dev, "ext_xtal");
>> +     else
>> +             ref_clk = clk_get(sphy->dev, "xusbxti");
>>       if (IS_ERR(ref_clk)) {
>>               dev_err(sphy->dev, "Failed to get reference clock\n");
>>               return PTR_ERR(ref_clk);
>>       }
>>
>> -     switch (clk_get_rate(ref_clk)) {
>> -     case 12 * MHZ:
>> -             refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
>> -             break;
>> -     case 24 * MHZ:
>> -             refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
>> -             break;
>> -     default:
>> -     case 48 * MHZ:
>> -             /* default reference clock */
>> -             refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
>> -             break;
>> +     if (sphy->cpu_type == TYPE_EXYNOS5250) {
>> +             /* set clock frequency for PLL */
>> +             switch (clk_get_rate(ref_clk)) {
>> +             case 96 * 100000:
>> +                     refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_9600K;
>> +                     break;
>> +             case 10 * MHZ:
>> +                     refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_10M;
>> +                     break;
>> +             case 12 * MHZ:
>> +                     refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_12M;
>> +                     break;
>> +             case 192 * 100000:
>> +                     refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_19200K;
>> +                     break;
>> +             case 20 * MHZ:
>> +                     refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_20M;
>> +                     break;
>> +             case 50 * MHZ:
>> +                     refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_50M;
>> +                     break;
>> +             case 24 * MHZ:
>> +             default:
>> +                     /* default reference clock */
>> +                     refclk_freq |= EXYNOS5_PHYHOST_FSEL_CLKSEL_24M;
>> +                     break;
>> +             }
>> +     } else {
>> +             switch (clk_get_rate(ref_clk)) {
>> +             case 12 * MHZ:
>> +                     refclk_freq |= S3C_PHYCLK_CLKSEL_12M;
>> +                     break;
>> +             case 24 * MHZ:
>> +                     refclk_freq |= S3C_PHYCLK_CLKSEL_24M;
>> +                     break;
>> +             default:
>> +             case 48 * MHZ:
>> +                     /* default reference clock */
>> +                     refclk_freq |= S3C_PHYCLK_CLKSEL_48M;
>> +                     break;
>> +             }
>>       }
>>       clk_put(ref_clk);
>>
>>       return refclk_freq;
>>  }
>>
>> +static int exynos5_phyhost_is_on(void *regs)
>> +{
>> +     return (readl(regs + EXYNOS5_PHYHOST) & EXYNOS5_PHYHOST_SIDDQ) ? 0 : 1;
>> +}
>> +
>> +static void samsung_exynos5_usbphy_enable(struct samsung_usbphy *sphy)
>> +{
>> +     void __iomem *regs = sphy->regs;
>> +     u32 phyclk = sphy->ref_clk_freq;
>> +     u32 phyhost;
>> +     u32 phyotg;
>> +     u32 phyhsic;
>> +     u32 ehcictrl;
>> +     u32 ohcictrl;
>> +
>> +     atomic_inc(&sphy->host_usage);
>> +
>> +     if (exynos5_phyhost_is_on(regs)) {
>> +             dev_info(sphy->dev, "Already power on PHY\n");
>> +             return;
>> +     }
>> +
>> +     /* Selecting Host/OTG mode; After reset USB2.0PHY_CFG: HOST */
>> +     if (sphy->plat && sphy->plat->phy_cfg_sel) {
>> +             if (sphy->plat->type)
>> +                     sphy->plat->phy_cfg_sel(sphy->dev, sphy->plat->type);
>> +             else
>> +                     sphy->plat->phy_cfg_sel(sphy->dev, TYPE_OTG);
>> +     }
>> +
>> +     /* Host configuration */
>> +     phyhost = readl(regs + EXYNOS5_PHYHOST);
>> +
>> +     /* phy reference clock configuration */
>> +     phyhost &= ~(EXYNOS5_PHYHOST_FSEL_MASK);
>> +     phyhost |= EXYNOS5_PHYHOST_FSEL(phyclk);
>> +
>> +     /* host phy reset */
>> +     phyhost &= ~(EXYNOS5_PHYHOST_PHYSWRST |
>> +                     EXYNOS5_PHYHOST_PHYSWRSTALL |
>> +                     EXYNOS5_PHYHOST_SIDDQ |
>> +                     /* Enable normal mode of operation */
>> +                     EXYNOS5_PHYHOST_FORCESUSPEND |
>> +                     EXYNOS5_PHYHOST_FORCESLEEP);
>> +
>> +     /* Link reset */
>> +     phyhost |= (EXYNOS5_PHYHOST_LINKSWRST |
>> +                     EXYNOS5_PHYHOST_UTMISWRST |
>> +                     /* COMMON Block configuration during suspend */
>> +                     EXYNOS5_PHYHOST_COMMONON_N);
>> +     writel(phyhost, regs + EXYNOS5_PHYHOST);
>> +     udelay(10);
>> +     phyhost &= ~(EXYNOS5_PHYHOST_LINKSWRST |
>> +                     EXYNOS5_PHYHOST_UTMISWRST);
>> +     writel(phyhost, regs + EXYNOS5_PHYHOST);
>> +
>> +     /* OTG configuration */
>> +     phyotg = readl(regs + EXYNOS5_PHYOTG);
>> +
>> +     /* phy reference clock configuration */
>> +     phyotg &= ~(EXYNOS5_PHYOTG_FSEL_MASK);
>> +     phyotg |= EXYNOS5_PHYOTG_FSEL(phyclk);
>> +
>> +     /* Enable normal mode of operation */
>> +     phyotg &= ~(EXYNOS5_PHYOTG_FORCESUSPEND |
>> +                     EXYNOS5_PHYOTG_SIDDQ_UOTG |
>> +                     EXYNOS5_PHYOTG_FORCESLEEP |
>> +                     EXYNOS5_PHYOTG_REFCLKSEL_MASK |
>> +                     /* COMMON Block configuration during suspend */
>> +                     EXYNOS5_PHYOTG_COMMON_ON);
>> +
>> +     /* OTG phy & link reset */
>> +     phyotg |= (EXYNOS5_PHYOTG_PHY0_SWRST |
>> +                     EXYNOS5_PHYOTG_LINKSWRST_UOTG |
>> +                     EXYNOS5_PHYOTG_PHYLINK_SWRESET |
>> +                     EXYNOS5_PHYOTG_OTGDISABLE |
>> +                     /* Set refclk */
>> +                     EXYNOS5_PHYOTG_REFCLKSEL_CLKCORE);
>> +
>> +     writel(phyotg, regs + EXYNOS5_PHYOTG);
>> +     udelay(10);
>> +     phyotg &= ~(EXYNOS5_PHYOTG_PHY0_SWRST |
>> +                     EXYNOS5_PHYOTG_LINKSWRST_UOTG   |
>> +                     EXYNOS5_PHYOTG_PHYLINK_SWRESET);
>> +     writel(phyotg, regs + EXYNOS5_PHYOTG);
>> +
>> +     /* HSIC phy configuration */
>> +     phyhsic = (EXYNOS5_PHYHSIC_REFCLKDIV_12 |
>> +                     EXYNOS5_PHYHSIC_REFCLKSEL |
>> +                     EXYNOS5_PHYHSIC_PHYSWRST);
>> +     writel(phyhsic, regs + EXYNOS5_PHYHSIC1);
>> +     writel(phyhsic, regs + EXYNOS5_PHYHSIC2);
>> +     udelay(10);
>> +     phyhsic &= ~(EXYNOS5_PHYHSIC_PHYSWRST);
>> +     writel(phyhsic, regs + EXYNOS5_PHYHSIC1);
>> +     writel(phyhsic, regs + EXYNOS5_PHYHSIC2);
>> +
>> +     udelay(80);
>> +
>> +     /* enable EHCI DMA burst */
>> +     ehcictrl = readl(regs + EXYNOS5_EHCICTRL);
>> +     ehcictrl |= (EXYNOS5_EHCICTRL_ENAINCRXALIGN |
>> +                             EXYNOS5_EHCICTRL_ENAINCR4 |
>> +                             EXYNOS5_EHCICTRL_ENAINCR8 |
>> +                             EXYNOS5_EHCICTRL_ENAINCR16);
>> +     writel(ehcictrl, regs + EXYNOS5_EHCICTRL);
>> +
>> +     /* set ohci_suspend_on_n */
>> +     ohcictrl = readl(regs + EXYNOS5_OHCICTRL);
>> +     ohcictrl |= EXYNOS5_OHCICTRL_SUSPLGCY;
>> +     writel(ohcictrl, regs + EXYNOS5_OHCICTRL);
>> +}
>> +
>>  static void samsung_usbphy_enable(struct samsung_usbphy *sphy)
>>  {
>>       void __iomem *regs = sphy->regs;
>> @@ -155,6 +412,41 @@ static void samsung_usbphy_enable(struct samsung_usbphy *sphy)
>>       writel(rstcon, regs + S3C_RSTCON);
>>  }
>>
>> +static void samsung_exynos5_usbphy_disable(struct samsung_usbphy *sphy)
>> +{
>> +     void __iomem *regs = sphy->regs;
>> +     u32 phyhost;
>> +     u32 phyotg;
>> +     u32 phyhsic;
>> +
>> +     if (atomic_dec_return(&sphy->host_usage) > 0) {
>> +             dev_info(sphy->dev, "still being used\n");
>> +             return;
>> +     }
>> +
>> +     phyhsic = (EXYNOS5_PHYHSIC_REFCLKDIV_12 |
>> +                     EXYNOS5_PHYHSIC_REFCLKSEL |
>> +                     EXYNOS5_PHYHSIC_SIDDQ |
>> +                     EXYNOS5_PHYHSIC_FORCESLEEP |
>> +                     EXYNOS5_PHYHSIC_FORCESUSPEND);
>> +     writel(phyhsic, regs + EXYNOS5_PHYHSIC1);
>> +     writel(phyhsic, regs + EXYNOS5_PHYHSIC2);
>> +
>> +     phyhost = readl(regs + EXYNOS5_PHYHOST);
>> +     phyhost |= (EXYNOS5_PHYHOST_SIDDQ |
>> +                     EXYNOS5_PHYHOST_FORCESUSPEND |
>> +                     EXYNOS5_PHYHOST_FORCESLEEP |
>> +                     EXYNOS5_PHYHOST_PHYSWRST |
>> +                     EXYNOS5_PHYHOST_PHYSWRSTALL);
>> +     writel(phyhost, regs + EXYNOS5_PHYHOST);
>> +
>> +     phyotg = readl(regs + EXYNOS5_PHYOTG);
>> +     phyotg |= (EXYNOS5_PHYOTG_FORCESUSPEND |
>> +                     EXYNOS5_PHYOTG_SIDDQ_UOTG |
>> +                     EXYNOS5_PHYOTG_FORCESLEEP);
>> +     writel(phyotg, regs + EXYNOS5_PHYOTG);
>> +}
>> +
>>  static void samsung_usbphy_disable(struct samsung_usbphy *sphy)
>>  {
>>       void __iomem *regs = sphy->regs;
>> @@ -194,11 +486,18 @@ static int samsung_usbphy_init(struct usb_phy *phy)
>>       }
>>
>>       /* Disable phy isolation */
>> -     if (sphy->plat && sphy->plat->pmu_isolation)
>> -             sphy->plat->pmu_isolation(false);
>> +     if (sphy->plat && sphy->plat->pmu_isolation) {
>> +             if (sphy->plat->type)
>> +                     sphy->plat->pmu_isolation(false, sphy->plat->type);
>> +             else
>> +                     sphy->plat->pmu_isolation(false, TYPE_OTG);
>> +     }
>>
>>       /* Initialize usb phy registers */
>> -     samsung_usbphy_enable(sphy);
>> +     if (sphy->cpu_type == TYPE_EXYNOS5250)
>> +             samsung_exynos5_usbphy_enable(sphy);
>> +     else
>> +             samsung_usbphy_enable(sphy);
>>
>>       /* Disable the phy clock */
>>       clk_disable_unprepare(sphy->clk);
>> @@ -220,11 +519,18 @@ static void samsung_usbphy_shutdown(struct usb_phy *phy)
>>       }
>>
>>       /* De-initialize usb phy registers */
>> -     samsung_usbphy_disableditto.(sphy);
>> +     if (sphy->cpu_type == TYPE_EXYNOS5250)
>> +             samsung_exynos5_usbphy_disable(sphy);
>> +     else
>> +             samsung_usbphy_disable(sphy);
>>
>>       /* Enable phy isolation */
>> -     if (sphy->plat && sphy->plat->pmu_isolation)
>> -             sphy->plat->pmu_isolation(true);
>> +     if (sphy->plat && sphy->plat->pmu_isolation) {
>> +             if (sphy->plat->type)
>> +                     sphy->plat->pmu_isolation(true, sphy->plat->type);
>> +             else
>> +                     sphy->plat->pmu_isolation(true, TYPE_OTG);
>> +     }
>>
>>       clk_disable_unprepare(sphy->clk);
>>  }
>> @@ -277,16 +583,9 @@ static int __devinit samsung_usbphy_probe(struct platform_device *pdev)
>>       if (!sphy)
>>               return -ENOMEM;
>>
>> -     clk = devm_clk_get(dev, "otg");
>> -     if (IS_ERR(clk)) {
>> -             dev_err(dev, "Failed to get otg clock\n");
>> -             return PTR_ERR(clk);
>> -     }
>> -
>>       sphy->dev               = &pdev->dev;
>>       sphy->plat              = pdata;
>>       sphy->regs              = phy_base;
>> -     sphy->clk               = clk;
>>       sphy->phy.dev           = sphy->dev;
>>       sphy->phy.label         = "samsung-usbphy";
>>       sphy->phy.init          = samsung_usbphy_init;
>> @@ -294,6 +593,17 @@ static int __devinit samsung_usbphy_probe(struct platform_device *pdev)
>>       sphy->cpu_type          = samsung_usbphy_get_driver_data(pdev);
>>       sphy->ref_clk_freq      = samsung_usbphy_get_refclk_freq(sphy);
>>
>> +     if (sphy->cpu_type == TYPE_EXYNOS5250)
>> +             clk = devm_clk_get(dev, "usbhost");
>> +     else
>> +             clk = devm_clk_get(dev, "otg");
>> +     if (IS_ERR(clk)) {
>> +             dev_err(dev, "Failed to get otg clock\n");
>> +             return PTR_ERR(clk);
>> +     }
>> +
>> +     sphy->clk = clk;
>> +
>>       ret = usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB2);
>>       return ret;
>>  }
>> @@ -315,6 +625,9 @@ static const struct of_device_id samsung_usbphy_dt_match[] = {
>>       }, {
>>               .compatible = "samsung,exynos4210-usbphy",
>>               .data = (void *)TYPE_EXYNOS4210,
>> +     }, {
>> +             .compatible = "samsung,exynos5250-usbphy",
>> +             .data = (void *)TYPE_EXYNOS5250,
>>       },
>>       {},
>>  };
>> @@ -330,6 +643,9 @@ static struct platform_device_id samsung_usbphy_driver_ids[] = {
>>       }, {
>>               .name           = "exynos4210-usbphy",
>>               .driver_data    = TYPE_EXYNOS4210,
>> +     }, {
>> +             .name           = "exynos5250-usbphy",
>> +             .driver_data    = TYPE_EXYNOS5250,
>>       },
>>       {},
>>  };
>> diff --git a/include/linux/platform_data/samsung-usbphy.h b/include/linux/platform_data/samsung-usbphy.h
>> index 1bd24cb..364a38a 100644
>> --- a/include/linux/platform_data/samsung-usbphy.h
>> +++ b/include/linux/platform_data/samsung-usbphy.h
>> @@ -18,8 +18,14 @@
>>   * samsung_usbphy_data - Platform data for USB PHY driver.
>>   * @pmu_isolation: Function to control usb phy isolation in PMU.
>>   */
>> +enum phy_type {
>> +     TYPE_OTG,
>> +     TYPE_HOST,
>> +};
>> +
>>  struct samsung_usbphy_data {
>> -     void (*pmu_isolation)(int on);
>> +     void (*pmu_isolation)(int on, int phy_type);
>> +     int type;
>>  };
>>
>>  extern void samsung_usbphy_set_pdata(struct samsung_usbphy_data *pd);
>> --
>> 1.7.6.5
>
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[PATCH 2/4 v2] ARM: Exynos5250: Enabling samsung-usbphy driver

[Vivek Gautam]

Adding usbphy node for Exynos5250 along with the platform data.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
---
 .../devicetree/bindings/usb/samsung-usbphy.txt     |   12 +++++-
 arch/arm/boot/dts/exynos5250.dtsi                  |    5 ++
 arch/arm/mach-exynos/Kconfig                       |    1 +
 arch/arm/mach-exynos/include/mach/map.h            |    1 +
 arch/arm/mach-exynos/mach-exynos5-dt.c             |   10 +++++
 arch/arm/mach-exynos/setup-usb-phy.c               |   43 ++++++++++++++++---
 arch/arm/plat-samsung/include/plat/usb-phy.h       |    1 +
 include/linux/platform_data/samsung-usbphy.h       |    1 +
 8 files changed, 65 insertions(+), 9 deletions(-)

diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
index 7d54d59..c644d01 100644
--- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
+++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
@@ -1,11 +1,19 @@
 * Samsung's usb phy transceiver
 
-The Samsung's phy transceiver is used for controlling usb otg phy for
-s3c-hsotg usb device controller.
+The Samsung's phy transceiver is used for controlling usb phy for
+s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers
+across Samsung SOCs.
 TODO: Adding the PHY binding with controller(s) according to the under 
 developement generic PHY driver.
 
+Exynos4210:
 Required properties:
 - compatible : should be "samsung,exynos4210-usbphy"
 - reg : base physical address of the phy registers and length of memory mapped
 	region.
+
+Exynos5250:
+Required properties:
+- compatible : should be "samsung,exynos5250-usbphy"
+- reg : base physical address of the phy registers and length of memory mapped
+	region.
diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
index dddfd6e..82bf042 100644
--- a/arch/arm/boot/dts/exynos5250.dtsi
+++ b/arch/arm/boot/dts/exynos5250.dtsi
@@ -218,6 +218,11 @@
 		#size-cells = <0>;
 	};
 
+	usbphy {
+		compatible = "samsung,exynos5250-usbphy";
+		reg = <0x12130000 0x100>;
+	};
+
 	amba {
 		#address-cells = <1>;
 		#size-cells = <1>;
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 4372075..e8e3d7b 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -422,6 +422,7 @@ config MACH_EXYNOS5_DT
 	select SOC_EXYNOS5250
 	select USE_OF
 	select ARM_AMBA
+	select EXYNOS4_SETUP_USB_PHY
 	help
 	  Machine support for Samsung EXYNOS5 machine with device tree enabled.
 	  Select this if a fdt blob is available for the EXYNOS5 SoC based board.
diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
index 9694424..7f5eb03 100644
--- a/arch/arm/mach-exynos/include/mach/map.h
+++ b/arch/arm/mach-exynos/include/mach/map.h
@@ -195,6 +195,7 @@
 #define EXYNOS4_PA_EHCI			0x12580000
 #define EXYNOS4_PA_OHCI			0x12590000
 #define EXYNOS4_PA_HSPHY		0x125B0000
+#define EXYNOS5_PA_HSPHY		0x12130000
 #define EXYNOS4_PA_MFC			0x13400000
 
 #define EXYNOS4_PA_UART			0x13800000
diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
index db1cd8e..bc041be 100644
--- a/arch/arm/mach-exynos/mach-exynos5-dt.c
+++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
@@ -11,6 +11,7 @@
 
 #include <linux/of_platform.h>
 #include <linux/serial_core.h>
+#include <linux/platform_data/samsung-usbphy.h>
 
 #include <asm/mach/arch.h>
 #include <asm/hardware/gic.h>
@@ -18,9 +19,16 @@
 
 #include <plat/cpu.h>
 #include <plat/regs-serial.h>
+#include <plat/usb-phy.h>
 
 #include "common.h"
 
+static struct samsung_usbphy_data exynos5_usbphy_pdata = {
+	.pmu_isolation = s5p_usb_phy_pmu_isolation,
+	.phy_cfg_sel = s5p_usb_phy_cfg_sel,
+	.type = TYPE_HOST,
+};
+
 /*
  * The following lookup table is used to override device names when devices
  * are registered from device tree. This is temporarily added to enable
@@ -72,6 +80,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
 				"exynos-gsc.2", NULL),
 	OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
 				"exynos-gsc.3", NULL),
+	OF_DEV_AUXDATA("samsung,exynos5250-usbphy", EXYNOS5_PA_HSPHY,
+				"s3c-usbphy", &exynos5_usbphy_pdata),
 	{},
 };
 
diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
index be6cd4f..bebc99b 100644
--- a/arch/arm/mach-exynos/setup-usb-phy.c
+++ b/arch/arm/mach-exynos/setup-usb-phy.c
@@ -14,11 +14,15 @@
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/platform_device.h>
+#include <linux/platform_data/samsung-usbphy.h>
 #include <mach/regs-pmu.h>
 #include <mach/regs-usb-phy.h>
 #include <plat/cpu.h>
+#include <plat/map-base.h>
 #include <plat/usb-phy.h>
 
+#define EXYNOS5_USB_CFG			(S3C_VA_SYS + (0x230))
+
 static atomic_t host_usage;
 
 static int exynos4_usb_host_phy_is_on(void)
@@ -224,13 +228,38 @@ int s5p_usb_phy_exit(struct platform_device *pdev, int type)
 
 void s5p_usb_phy_pmu_isolation(int on, int type)
 {
-	if (on) {
-		writel(readl(S5P_USBDEVICE_PHY_CONTROL)
-			& ~S5P_USBDEVICE_PHY_ENABLE,
-				S5P_USBDEVICE_PHY_CONTROL);
+	if (type == TYPE_HOST) {
+		if (on) {
+			writel(readl(S5P_USBHOST_PHY_CONTROL)
+				& ~S5P_USBHOST_PHY_ENABLE,
+					S5P_USBHOST_PHY_CONTROL);
+		} else {
+			writel(readl(S5P_USBHOST_PHY_CONTROL)
+				| S5P_USBHOST_PHY_ENABLE,
+					S5P_USBHOST_PHY_CONTROL);
+		}
 	} else {
-		writel(readl(S5P_USBDEVICE_PHY_CONTROL)
-			| S5P_USBDEVICE_PHY_ENABLE,
-				S5P_USBDEVICE_PHY_CONTROL);
+		if (on) {
+			writel(readl(S5P_USBDEVICE_PHY_CONTROL)
+				& ~S5P_USBDEVICE_PHY_ENABLE,
+					S5P_USBDEVICE_PHY_CONTROL);
+		} else {
+			writel(readl(S5P_USBDEVICE_PHY_CONTROL)
+				| S5P_USBDEVICE_PHY_ENABLE,
+					S5P_USBDEVICE_PHY_CONTROL);
+		}
 	}
 }
+
+/* Switch between HOST and OTG link from PHY_CFG */
+void s5p_usb_phy_cfg_sel(struct device *dev, int type)
+{
+	u32 is_host;
+
+	is_host = readl(EXYNOS5_USB_CFG);
+	writel(type, EXYNOS5_USB_CFG);
+
+	if (is_host != type)
+		dev_dbg(dev, "Changed USB MUX from %s to %s",
+			is_host ? "Host" : "Device", type ? "Host" : "Device");
+}
diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
index 7a4a959..a57b8bb 100644
--- a/arch/arm/plat-samsung/include/plat/usb-phy.h
+++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
@@ -19,5 +19,6 @@ enum s5p_usb_phy_type {
 extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
 extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
 extern void s5p_usb_phy_pmu_isolation(int on, int type);
+extern void s5p_usb_phy_cfg_sel(struct device *dev, int type);
 
 #endif /* __PLAT_SAMSUNG_USB_PHY_H */
diff --git a/include/linux/platform_data/samsung-usbphy.h b/include/linux/platform_data/samsung-usbphy.h
index 364a38a..2b400e0 100644
--- a/include/linux/platform_data/samsung-usbphy.h
+++ b/include/linux/platform_data/samsung-usbphy.h
@@ -25,6 +25,7 @@ enum phy_type {
 
 struct samsung_usbphy_data {
 	void (*pmu_isolation)(int on, int phy_type);
+	void (*phy_cfg_sel)(struct device *dev, int phy_type);
 	int type;
 };
 
-- 
1.7.6.5

Re: [PATCH 2/4 v2] ARM: Exynos5250: Enabling samsung-usbphy driver

[Jingoo Han]

On Wednesday, October 10, 2012 7:43 PM Vivek Gautam wrote
> 
> Adding usbphy node for Exynos5250 along with the platform data.
> 
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
> ---
>  .../devicetree/bindings/usb/samsung-usbphy.txt     |   12 +++++-
>  arch/arm/boot/dts/exynos5250.dtsi                  |    5 ++
>  arch/arm/mach-exynos/Kconfig                       |    1 +
>  arch/arm/mach-exynos/include/mach/map.h            |    1 +
>  arch/arm/mach-exynos/mach-exynos5-dt.c             |   10 +++++
>  arch/arm/mach-exynos/setup-usb-phy.c               |   43 ++++++++++++++++---
>  arch/arm/plat-samsung/include/plat/usb-phy.h       |    1 +
>  include/linux/platform_data/samsung-usbphy.h       |    1 +
>  8 files changed, 65 insertions(+), 9 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> index 7d54d59..c644d01 100644
> --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
> @@ -1,11 +1,19 @@
>  * Samsung's usb phy transceiver
> 
> -The Samsung's phy transceiver is used for controlling usb otg phy for
> -s3c-hsotg usb device controller.
> +The Samsung's phy transceiver is used for controlling usb phy for
> +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers
> +across Samsung SOCs.
>  TODO: Adding the PHY binding with controller(s) according to the under
>  developement generic PHY driver.
> 
> +Exynos4210:
>  Required properties:
>  - compatible : should be "samsung,exynos4210-usbphy"
>  - reg : base physical address of the phy registers and length of memory mapped
>  	region.
> +
> +Exynos5250:
> +Required properties:
> +- compatible : should be "samsung,exynos5250-usbphy"
> +- reg : base physical address of the phy registers and length of memory mapped
> +	region.
> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
> index dddfd6e..82bf042 100644
> --- a/arch/arm/boot/dts/exynos5250.dtsi
> +++ b/arch/arm/boot/dts/exynos5250.dtsi
> @@ -218,6 +218,11 @@
>  		#size-cells = <0>;
>  	};
> 
> +	usbphy {
> +		compatible = "samsung,exynos5250-usbphy";
> +		reg = <0x12130000 0x100>;
> +	};
> +
>  	amba {
>  		#address-cells = <1>;
>  		#size-cells = <1>;
> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
> index 4372075..e8e3d7b 100644
> --- a/arch/arm/mach-exynos/Kconfig
> +++ b/arch/arm/mach-exynos/Kconfig
> @@ -422,6 +422,7 @@ config MACH_EXYNOS5_DT
>  	select SOC_EXYNOS5250
>  	select USE_OF
>  	select ARM_AMBA
> +	select EXYNOS4_SETUP_USB_PHY
>  	help
>  	  Machine support for Samsung EXYNOS5 machine with device tree enabled.
>  	  Select this if a fdt blob is available for the EXYNOS5 SoC based board.
> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
> index 9694424..7f5eb03 100644
> --- a/arch/arm/mach-exynos/include/mach/map.h
> +++ b/arch/arm/mach-exynos/include/mach/map.h
> @@ -195,6 +195,7 @@
>  #define EXYNOS4_PA_EHCI			0x12580000
>  #define EXYNOS4_PA_OHCI			0x12590000
>  #define EXYNOS4_PA_HSPHY		0x125B0000
> +#define EXYNOS5_PA_HSPHY		0x12130000
>  #define EXYNOS4_PA_MFC			0x13400000
> 
>  #define EXYNOS4_PA_UART			0x13800000
> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
> index db1cd8e..bc041be 100644
> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
> @@ -11,6 +11,7 @@
> 
>  #include <linux/of_platform.h>
>  #include <linux/serial_core.h>
> +#include <linux/platform_data/samsung-usbphy.h>
> 
>  #include <asm/mach/arch.h>
>  #include <asm/hardware/gic.h>
> @@ -18,9 +19,16 @@
> 
>  #include <plat/cpu.h>
>  #include <plat/regs-serial.h>
> +#include <plat/usb-phy.h>
> 
>  #include "common.h"
> 
> +static struct samsung_usbphy_data exynos5_usbphy_pdata = {
> +	.pmu_isolation = s5p_usb_phy_pmu_isolation,
> +	.phy_cfg_sel = s5p_usb_phy_cfg_sel,
> +	.type = TYPE_HOST,
> +};
> +
>  /*
>   * The following lookup table is used to override device names when devices
>   * are registered from device tree. This is temporarily added to enable
> @@ -72,6 +80,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
>  				"exynos-gsc.2", NULL),
>  	OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
>  				"exynos-gsc.3", NULL),
> +	OF_DEV_AUXDATA("samsung,exynos5250-usbphy", EXYNOS5_PA_HSPHY,
> +				"s3c-usbphy", &exynos5_usbphy_pdata),
>  	{},
>  };
> 
> diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
> index be6cd4f..bebc99b 100644
> --- a/arch/arm/mach-exynos/setup-usb-phy.c
> +++ b/arch/arm/mach-exynos/setup-usb-phy.c
> @@ -14,11 +14,15 @@
>  #include <linux/err.h>
>  #include <linux/io.h>
>  #include <linux/platform_device.h>
> +#include <linux/platform_data/samsung-usbphy.h>
>  #include <mach/regs-pmu.h>
>  #include <mach/regs-usb-phy.h>
>  #include <plat/cpu.h>
> +#include <plat/map-base.h>
>  #include <plat/usb-phy.h>
> 
> +#define EXYNOS5_USB_CFG			(S3C_VA_SYS + (0x230))

The parentheses around 0x230 is not necessary.

+#define EXYNOS5_USB_CFG			(S3C_VA_SYS + 0x230)


> +
>  static atomic_t host_usage;
> 
>  static int exynos4_usb_host_phy_is_on(void)
> @@ -224,13 +228,38 @@ int s5p_usb_phy_exit(struct platform_device *pdev, int type)
> 
>  void s5p_usb_phy_pmu_isolation(int on, int type)
>  {
> -	if (on) {
> -		writel(readl(S5P_USBDEVICE_PHY_CONTROL)
> -			& ~S5P_USBDEVICE_PHY_ENABLE,
> -				S5P_USBDEVICE_PHY_CONTROL);
> +	if (type == TYPE_HOST) {
> +		if (on) {
> +			writel(readl(S5P_USBHOST_PHY_CONTROL)
> +				& ~S5P_USBHOST_PHY_ENABLE,
> +					S5P_USBHOST_PHY_CONTROL);
> +		} else {
> +			writel(readl(S5P_USBHOST_PHY_CONTROL)
> +				| S5P_USBHOST_PHY_ENABLE,
> +					S5P_USBHOST_PHY_CONTROL);
> +		}
>  	} else {
> -		writel(readl(S5P_USBDEVICE_PHY_CONTROL)
> -			| S5P_USBDEVICE_PHY_ENABLE,
> -				S5P_USBDEVICE_PHY_CONTROL);
> +		if (on) {
> +			writel(readl(S5P_USBDEVICE_PHY_CONTROL)
> +				& ~S5P_USBDEVICE_PHY_ENABLE,
> +					S5P_USBDEVICE_PHY_CONTROL);
> +		} else {
> +			writel(readl(S5P_USBDEVICE_PHY_CONTROL)
> +				| S5P_USBDEVICE_PHY_ENABLE,
> +					S5P_USBDEVICE_PHY_CONTROL);
> +		}
>  	}
>  }
> +
> +/* Switch between HOST and OTG link from PHY_CFG */
> +void s5p_usb_phy_cfg_sel(struct device *dev, int type)
> +{
> +	u32 is_host;
> +
> +	is_host = readl(EXYNOS5_USB_CFG);
> +	writel(type, EXYNOS5_USB_CFG);
> +
> +	if (is_host != type)
> +		dev_dbg(dev, "Changed USB MUX from %s to %s",
> +			is_host ? "Host" : "Device", type ? "Host" : "Device");
> +}
> diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
> index 7a4a959..a57b8bb 100644
> --- a/arch/arm/plat-samsung/include/plat/usb-phy.h
> +++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
> @@ -19,5 +19,6 @@ enum s5p_usb_phy_type {
>  extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
>  extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
>  extern void s5p_usb_phy_pmu_isolation(int on, int type);
> +extern void s5p_usb_phy_cfg_sel(struct device *dev, int type);
> 
>  #endif /* __PLAT_SAMSUNG_USB_PHY_H */
> diff --git a/include/linux/platform_data/samsung-usbphy.h b/include/linux/platform_data/samsung-usbphy.h
> index 364a38a..2b400e0 100644
> --- a/include/linux/platform_data/samsung-usbphy.h
> +++ b/include/linux/platform_data/samsung-usbphy.h
> @@ -25,6 +25,7 @@ enum phy_type {
> 
>  struct samsung_usbphy_data {
>  	void (*pmu_isolation)(int on, int phy_type);
> +	void (*phy_cfg_sel)(struct device *dev, int phy_type);
>  	int type;
>  };
> 
> --
> 1.7.6.5
> 
> --
> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Re: [PATCH 2/4 v2] ARM: Exynos5250: Enabling samsung-usbphy driver

[Vivek Gautam]

Hi,

On Mon, Oct 22, 2012 at 10:33 AM, Jingoo Han <jg1.han@samsung.com> wrote:
> On Wednesday, October 10, 2012 7:43 PM Vivek Gautam wrote
>>
>> Adding usbphy node for Exynos5250 along with the platform data.
>>
>> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
>> ---
>>  .../devicetree/bindings/usb/samsung-usbphy.txt     |   12 +++++-
>>  arch/arm/boot/dts/exynos5250.dtsi                  |    5 ++
>>  arch/arm/mach-exynos/Kconfig                       |    1 +
>>  arch/arm/mach-exynos/include/mach/map.h            |    1 +
>>  arch/arm/mach-exynos/mach-exynos5-dt.c             |   10 +++++
>>  arch/arm/mach-exynos/setup-usb-phy.c               |   43 ++++++++++++++++---
>>  arch/arm/plat-samsung/include/plat/usb-phy.h       |    1 +
>>  include/linux/platform_data/samsung-usbphy.h       |    1 +
>>  8 files changed, 65 insertions(+), 9 deletions(-)
>>
>> diff --git a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> index 7d54d59..c644d01 100644
>> --- a/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> +++ b/Documentation/devicetree/bindings/usb/samsung-usbphy.txt
>> @@ -1,11 +1,19 @@
>>  * Samsung's usb phy transceiver
>>
>> -The Samsung's phy transceiver is used for controlling usb otg phy for
>> -s3c-hsotg usb device controller.
>> +The Samsung's phy transceiver is used for controlling usb phy for
>> +s3c-hsotg as well as ehci-s5p and ohci-exynos usb controllers
>> +across Samsung SOCs.
>>  TODO: Adding the PHY binding with controller(s) according to the under
>>  developement generic PHY driver.
>>
>> +Exynos4210:
>>  Required properties:
>>  - compatible : should be "samsung,exynos4210-usbphy"
>>  - reg : base physical address of the phy registers and length of memory mapped
>>       region.
>> +
>> +Exynos5250:
>> +Required properties:
>> +- compatible : should be "samsung,exynos5250-usbphy"
>> +- reg : base physical address of the phy registers and length of memory mapped
>> +     region.
>> diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi
>> index dddfd6e..82bf042 100644
>> --- a/arch/arm/boot/dts/exynos5250.dtsi
>> +++ b/arch/arm/boot/dts/exynos5250.dtsi
>> @@ -218,6 +218,11 @@
>>               #size-cells = <0>;
>>       };
>>
>> +     usbphy {
>> +             compatible = "samsung,exynos5250-usbphy";
>> +             reg = <0x12130000 0x100>;
>> +     };
>> +
>>       amba {
>>               #address-cells = <1>;
>>               #size-cells = <1>;
>> diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
>> index 4372075..e8e3d7b 100644
>> --- a/arch/arm/mach-exynos/Kconfig
>> +++ b/arch/arm/mach-exynos/Kconfig
>> @@ -422,6 +422,7 @@ config MACH_EXYNOS5_DT
>>       select SOC_EXYNOS5250
>>       select USE_OF
>>       select ARM_AMBA
>> +     select EXYNOS4_SETUP_USB_PHY
>>       help
>>         Machine support for Samsung EXYNOS5 machine with device tree enabled.
>>         Select this if a fdt blob is available for the EXYNOS5 SoC based board.
>> diff --git a/arch/arm/mach-exynos/include/mach/map.h b/arch/arm/mach-exynos/include/mach/map.h
>> index 9694424..7f5eb03 100644
>> --- a/arch/arm/mach-exynos/include/mach/map.h
>> +++ b/arch/arm/mach-exynos/include/mach/map.h
>> @@ -195,6 +195,7 @@
>>  #define EXYNOS4_PA_EHCI                      0x12580000
>>  #define EXYNOS4_PA_OHCI                      0x12590000
>>  #define EXYNOS4_PA_HSPHY             0x125B0000
>> +#define EXYNOS5_PA_HSPHY             0x12130000
>>  #define EXYNOS4_PA_MFC                       0x13400000
>>
>>  #define EXYNOS4_PA_UART                      0x13800000
>> diff --git a/arch/arm/mach-exynos/mach-exynos5-dt.c b/arch/arm/mach-exynos/mach-exynos5-dt.c
>> index db1cd8e..bc041be 100644
>> --- a/arch/arm/mach-exynos/mach-exynos5-dt.c
>> +++ b/arch/arm/mach-exynos/mach-exynos5-dt.c
>> @@ -11,6 +11,7 @@
>>
>>  #include <linux/of_platform.h>
>>  #include <linux/serial_core.h>
>> +#include <linux/platform_data/samsung-usbphy.h>
>>
>>  #include <asm/mach/arch.h>
>>  #include <asm/hardware/gic.h>
>> @@ -18,9 +19,16 @@
>>
>>  #include <plat/cpu.h>
>>  #include <plat/regs-serial.h>
>> +#include <plat/usb-phy.h>
>>
>>  #include "common.h"
>>
>> +static struct samsung_usbphy_data exynos5_usbphy_pdata = {
>> +     .pmu_isolation = s5p_usb_phy_pmu_isolation,
>> +     .phy_cfg_sel = s5p_usb_phy_cfg_sel,
>> +     .type = TYPE_HOST,
>> +};
>> +
>>  /*
>>   * The following lookup table is used to override device names when devices
>>   * are registered from device tree. This is temporarily added to enable
>> @@ -72,6 +80,8 @@ static const struct of_dev_auxdata exynos5250_auxdata_lookup[] __initconst = {
>>                               "exynos-gsc.2", NULL),
>>       OF_DEV_AUXDATA("samsung,exynos5-gsc", EXYNOS5_PA_GSC3,
>>                               "exynos-gsc.3", NULL),
>> +     OF_DEV_AUXDATA("samsung,exynos5250-usbphy", EXYNOS5_PA_HSPHY,
>> +                             "s3c-usbphy", &exynos5_usbphy_pdata),
>>       {},
>>  };
>>
>> diff --git a/arch/arm/mach-exynos/setup-usb-phy.c b/arch/arm/mach-exynos/setup-usb-phy.c
>> index be6cd4f..bebc99b 100644
>> --- a/arch/arm/mach-exynos/setup-usb-phy.c
>> +++ b/arch/arm/mach-exynos/setup-usb-phy.c
>> @@ -14,11 +14,15 @@
>>  #include <linux/err.h>
>>  #include <linux/io.h>
>>  #include <linux/platform_device.h>
>> +#include <linux/platform_data/samsung-usbphy.h>
>>  #include <mach/regs-pmu.h>
>>  #include <mach/regs-usb-phy.h>
>>  #include <plat/cpu.h>
>> +#include <plat/map-base.h>
>>  #include <plat/usb-phy.h>
>>
>> +#define EXYNOS5_USB_CFG                      (S3C_VA_SYS + (0x230))
>
> The parentheses around 0x230 is not necessary.
>
> +#define EXYNOS5_USB_CFG                        (S3C_VA_SYS + 0x230)
>
Ok, will remove them.

>
>> +
>>  static atomic_t host_usage;
>>
>>  static int exynos4_usb_host_phy_is_on(void)
>> @@ -224,13 +228,38 @@ int s5p_usb_phy_exit(struct platform_device *pdev, int type)
>>
>>  void s5p_usb_phy_pmu_isolation(int on, int type)
>>  {
>> -     if (on) {
>> -             writel(readl(S5P_USBDEVICE_PHY_CONTROL)
>> -                     & ~S5P_USBDEVICE_PHY_ENABLE,
>> -                             S5P_USBDEVICE_PHY_CONTROL);
>> +     if (type == TYPE_HOST) {
>> +             if (on) {
>> +                     writel(readl(S5P_USBHOST_PHY_CONTROL)
>> +                             & ~S5P_USBHOST_PHY_ENABLE,
>> +                                     S5P_USBHOST_PHY_CONTROL);
>> +             } else {
>> +                     writel(readl(S5P_USBHOST_PHY_CONTROL)
>> +                             | S5P_USBHOST_PHY_ENABLE,
>> +                                     S5P_USBHOST_PHY_CONTROL);
>> +             }
>>       } else {
>> -             writel(readl(S5P_USBDEVICE_PHY_CONTROL)
>> -                     | S5P_USBDEVICE_PHY_ENABLE,
>> -                             S5P_USBDEVICE_PHY_CONTROL);
>> +             if (on) {
>> +                     writel(readl(S5P_USBDEVICE_PHY_CONTROL)
>> +                             & ~S5P_USBDEVICE_PHY_ENABLE,
>> +                                     S5P_USBDEVICE_PHY_CONTROL);
>> +             } else {
>> +                     writel(readl(S5P_USBDEVICE_PHY_CONTROL)
>> +                             | S5P_USBDEVICE_PHY_ENABLE,
>> +                                     S5P_USBDEVICE_PHY_CONTROL);
>> +             }
>>       }
>>  }
>> +
>> +/* Switch between HOST and OTG link from PHY_CFG */
>> +void s5p_usb_phy_cfg_sel(struct device *dev, int type)
>> +{
>> +     u32 is_host;
>> +
>> +     is_host = readl(EXYNOS5_USB_CFG);
>> +     writel(type, EXYNOS5_USB_CFG);
>> +
>> +     if (is_host != type)
>> +             dev_dbg(dev, "Changed USB MUX from %s to %s",
>> +                     is_host ? "Host" : "Device", type ? "Host" : "Device");
>> +}
>> diff --git a/arch/arm/plat-samsung/include/plat/usb-phy.h b/arch/arm/plat-samsung/include/plat/usb-phy.h
>> index 7a4a959..a57b8bb 100644
>> --- a/arch/arm/plat-samsung/include/plat/usb-phy.h
>> +++ b/arch/arm/plat-samsung/include/plat/usb-phy.h
>> @@ -19,5 +19,6 @@ enum s5p_usb_phy_type {
>>  extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
>>  extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
>>  extern void s5p_usb_phy_pmu_isolation(int on, int type);
>> +extern void s5p_usb_phy_cfg_sel(struct device *dev, int type);
>>
>>  #endif /* __PLAT_SAMSUNG_USB_PHY_H */
>> diff --git a/include/linux/platform_data/samsung-usbphy.h b/include/linux/platform_data/samsung-usbphy.h
>> index 364a38a..2b400e0 100644
>> --- a/include/linux/platform_data/samsung-usbphy.h
>> +++ b/include/linux/platform_data/samsung-usbphy.h
>> @@ -25,6 +25,7 @@ enum phy_type {
>>
>>  struct samsung_usbphy_data {
>>       void (*pmu_isolation)(int on, int phy_type);
>> +     void (*phy_cfg_sel)(struct device *dev, int phy_type);
>>       int type;
>>  };
>>
>> --
>> 1.7.6.5
>>
>> --
>> To unsubscribe from this list: send the line "unsubscribe linux-usb" in
>> the body of a message to majordomo@vger.kernel.org
>> More majordomo info at  http://vger.kernel.org/majordomo-info.html
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at  http://vger.kernel.org/majordomo-info.html

Thanks & Regards
Vivek

[PATCH 3/4 v2] USB: ehci-s5p: Add phy driver support

[Vivek Gautam]

Adding the transceiver to ehci driver. Keeping the platform data
for continuing the smooth operation for boards which still uses it

Signed-off-by: Vivek Gautam <gautam.vivek-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 drivers/usb/host/ehci-s5p.c |   65 +++++++++++++++++++++++++++++-------------
 1 files changed, 45 insertions(+), 20 deletions(-)

diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
index 85b74be..6dac38f 100644
--- a/drivers/usb/host/ehci-s5p.c
+++ b/drivers/usb/host/ehci-s5p.c
@@ -17,6 +17,7 @@
 #include <linux/platform_device.h>
 #include <linux/of_gpio.h>
 #include <linux/platform_data/usb-ehci-s5p.h>
+#include <linux/usb/phy.h>
 #include <plat/usb-phy.h>
 
 #define EHCI_INSNREG00(base)			(base + 0x90)
@@ -32,6 +33,8 @@ struct s5p_ehci_hcd {
 	struct device *dev;
 	struct usb_hcd *hcd;
 	struct clk *clk;
+	struct usb_phy *phy;
+	struct s5p_ehci_platdata *pdata;
 };
 
 static const struct hc_driver s5p_ehci_hc_driver = {
@@ -65,6 +68,26 @@ static const struct hc_driver s5p_ehci_hc_driver = {
 	.clear_tt_buffer_complete	= ehci_clear_tt_buffer_complete,
 };
 
+static void s5p_ehci_phy_enable(struct s5p_ehci_hcd *s5p_ehci)
+{
+	struct platform_device *pdev = to_platform_device(s5p_ehci->dev);
+
+	if (s5p_ehci->phy)
+		usb_phy_init(s5p_ehci->phy);
+	else if (s5p_ehci->pdata->phy_init)
+		s5p_ehci->pdata->phy_init(pdev, S5P_USB_PHY_HOST);
+}
+
+static void s5p_ehci_phy_disable(struct s5p_ehci_hcd *s5p_ehci)
+{
+	struct platform_device *pdev = to_platform_device(s5p_ehci->dev);
+
+	if (s5p_ehci->phy)
+		usb_phy_shutdown(s5p_ehci->phy);
+	else if (s5p_ehci->pdata->phy_exit)
+		s5p_ehci->pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
+}
+
 static void s5p_setup_vbus_gpio(struct platform_device *pdev)
 {
 	int err;
@@ -92,15 +115,10 @@ static int __devinit s5p_ehci_probe(struct platform_device *pdev)
 	struct usb_hcd *hcd;
 	struct ehci_hcd *ehci;
 	struct resource *res;
+	struct usb_phy *phy;
 	int irq;
 	int err;
 
-	pdata = pdev->dev.platform_data;
-	if (!pdata) {
-		dev_err(&pdev->dev, "No platform data defined\n");
-		return -EINVAL;
-	}
-
 	/*
 	 * Right now device-tree probed devices don't get dma_mask set.
 	 * Since shared usb code relies on it, set it here for now.
@@ -118,6 +136,20 @@ static int __devinit s5p_ehci_probe(struct platform_device *pdev)
 	if (!s5p_ehci)
 		return -ENOMEM;
 
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		/* Fallback to Phy transceiver */
+		phy = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
+		if (IS_ERR_OR_NULL(phy)) {
+			dev_err(&pdev->dev, "no platform data or transceiver defined\n");
+			return -EPROBE_DEFER;
+		} else {
+			s5p_ehci->phy = phy;
+		}
+	} else {
+		s5p_ehci->pdata = pdata;
+	}
+
 	s5p_ehci->dev = &pdev->dev;
 
 	hcd = usb_create_hcd(&s5p_ehci_hc_driver, &pdev->dev,
@@ -163,8 +195,7 @@ static int __devinit s5p_ehci_probe(struct platform_device *pdev)
 		goto fail_io;
 	}
 
-	if (pdata->phy_init)
-		pdata->phy_init(pdev, S5P_USB_PHY_HOST);
+	s5p_ehci_phy_enable(s5p_ehci);
 
 	ehci = hcd_to_ehci(hcd);
 	ehci->caps = hcd->regs;
@@ -175,13 +206,15 @@ static int __devinit s5p_ehci_probe(struct platform_device *pdev)
 	err = usb_add_hcd(hcd, irq, IRQF_SHARED);
 	if (err) {
 		dev_err(&pdev->dev, "Failed to add USB HCD\n");
-		goto fail_io;
+		goto fail_add_hcd;
 	}
 
 	platform_set_drvdata(pdev, s5p_ehci);
 
 	return 0;
 
+fail_add_hcd:
+	s5p_ehci_phy_disable(s5p_ehci);
 fail_io:
 	clk_disable(s5p_ehci->clk);
 fail_clk:
@@ -191,14 +224,12 @@ fail_clk:
 
 static int __devexit s5p_ehci_remove(struct platform_device *pdev)
 {
-	struct s5p_ehci_platdata *pdata = pdev->dev.platform_data;
 	struct s5p_ehci_hcd *s5p_ehci = platform_get_drvdata(pdev);
 	struct usb_hcd *hcd = s5p_ehci->hcd;
 
 	usb_remove_hcd(hcd);
 
-	if (pdata && pdata->phy_exit)
-		pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
+	s5p_ehci_phy_disable(s5p_ehci);
 
 	clk_disable(s5p_ehci->clk);
 
@@ -222,14 +253,11 @@ static int s5p_ehci_suspend(struct device *dev)
 	struct s5p_ehci_hcd *s5p_ehci = dev_get_drvdata(dev);
 	struct usb_hcd *hcd = s5p_ehci->hcd;
 	bool do_wakeup = device_may_wakeup(dev);
-	struct platform_device *pdev = to_platform_device(dev);
-	struct s5p_ehci_platdata *pdata = pdev->dev.platform_data;
 	int rc;
 
 	rc = ehci_suspend(hcd, do_wakeup);
 
-	if (pdata && pdata->phy_exit)
-		pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
+	s5p_ehci_phy_disable(s5p_ehci);
 
 	clk_disable(s5p_ehci->clk);
 
@@ -240,13 +268,10 @@ static int s5p_ehci_resume(struct device *dev)
 {
 	struct s5p_ehci_hcd *s5p_ehci = dev_get_drvdata(dev);
 	struct usb_hcd *hcd = s5p_ehci->hcd;
-	struct platform_device *pdev = to_platform_device(dev);
-	struct s5p_ehci_platdata *pdata = pdev->dev.platform_data;
 
 	clk_enable(s5p_ehci->clk);
 
-	if (pdata && pdata->phy_init)
-		pdata->phy_init(pdev, S5P_USB_PHY_HOST);
+	s5p_ehci_phy_enable(s5p_ehci);
 
 	/* DMA burst Enable */
 	writel(EHCI_INSNREG00_ENABLE_DMA_BURST, EHCI_INSNREG00(hcd->regs));
-- 
1.7.6.5

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Re: [PATCH 3/4 v2] USB: ehci-s5p: Add phy driver support

[Jingoo Han]

On Wednesday, October 10, 2012 7:43 PM Vivek Gautam wrote

> 
> Adding the transceiver to ehci driver. Keeping the platform data
> for continuing the smooth operation for boards which still uses it
> 
> Signed-off-by: Vivek Gautam <gautam.vivek-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>


It looks good. I have tested this patch with Exynos5250.

Acked-by: Jingoo Han <jg1.han-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>


Best regards,
Jingoo Han


> ---
>  drivers/usb/host/ehci-s5p.c |   65 +++++++++++++++++++++++++++++-------------
>  1 files changed, 45 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
> index 85b74be..6dac38f 100644
> --- a/drivers/usb/host/ehci-s5p.c
> +++ b/drivers/usb/host/ehci-s5p.c
> @@ -17,6 +17,7 @@
>  #include <linux/platform_device.h>
>  #include <linux/of_gpio.h>
>  #include <linux/platform_data/usb-ehci-s5p.h>
> +#include <linux/usb/phy.h>
>  #include <plat/usb-phy.h>
> 
>  #define EHCI_INSNREG00(base)			(base + 0x90)
> @@ -32,6 +33,8 @@ struct s5p_ehci_hcd {
>  	struct device *dev;
>  	struct usb_hcd *hcd;
>  	struct clk *clk;
> +	struct usb_phy *phy;
> +	struct s5p_ehci_platdata *pdata;
>  };
> 
>  static const struct hc_driver s5p_ehci_hc_driver = {
> @@ -65,6 +68,26 @@ static const struct hc_driver s5p_ehci_hc_driver = {
>  	.clear_tt_buffer_complete	= ehci_clear_tt_buffer_complete,
>  };
> 
> +static void s5p_ehci_phy_enable(struct s5p_ehci_hcd *s5p_ehci)
> +{
> +	struct platform_device *pdev = to_platform_device(s5p_ehci->dev);
> +
> +	if (s5p_ehci->phy)
> +		usb_phy_init(s5p_ehci->phy);
> +	else if (s5p_ehci->pdata->phy_init)
> +		s5p_ehci->pdata->phy_init(pdev, S5P_USB_PHY_HOST);
> +}
> +
> +static void s5p_ehci_phy_disable(struct s5p_ehci_hcd *s5p_ehci)
> +{
> +	struct platform_device *pdev = to_platform_device(s5p_ehci->dev);
> +
> +	if (s5p_ehci->phy)
> +		usb_phy_shutdown(s5p_ehci->phy);
> +	else if (s5p_ehci->pdata->phy_exit)
> +		s5p_ehci->pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
> +}
> +
>  static void s5p_setup_vbus_gpio(struct platform_device *pdev)
>  {
>  	int err;
> @@ -92,15 +115,10 @@ static int __devinit s5p_ehci_probe(struct platform_device *pdev)
>  	struct usb_hcd *hcd;
>  	struct ehci_hcd *ehci;
>  	struct resource *res;
> +	struct usb_phy *phy;
>  	int irq;
>  	int err;
> 
> -	pdata = pdev->dev.platform_data;
> -	if (!pdata) {
> -		dev_err(&pdev->dev, "No platform data defined\n");
> -		return -EINVAL;
> -	}
> -
>  	/*
>  	 * Right now device-tree probed devices don't get dma_mask set.
>  	 * Since shared usb code relies on it, set it here for now.
> @@ -118,6 +136,20 @@ static int __devinit s5p_ehci_probe(struct platform_device *pdev)
>  	if (!s5p_ehci)
>  		return -ENOMEM;
> 
> +	pdata = pdev->dev.platform_data;
> +	if (!pdata) {
> +		/* Fallback to Phy transceiver */
> +		phy = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
> +		if (IS_ERR_OR_NULL(phy)) {
> +			dev_err(&pdev->dev, "no platform data or transceiver defined\n");
> +			return -EPROBE_DEFER;
> +		} else {
> +			s5p_ehci->phy = phy;
> +		}
> +	} else {
> +		s5p_ehci->pdata = pdata;
> +	}
> +
>  	s5p_ehci->dev = &pdev->dev;
> 
>  	hcd = usb_create_hcd(&s5p_ehci_hc_driver, &pdev->dev,
> @@ -163,8 +195,7 @@ static int __devinit s5p_ehci_probe(struct platform_device *pdev)
>  		goto fail_io;
>  	}
> 
> -	if (pdata->phy_init)
> -		pdata->phy_init(pdev, S5P_USB_PHY_HOST);
> +	s5p_ehci_phy_enable(s5p_ehci);
> 
>  	ehci = hcd_to_ehci(hcd);
>  	ehci->caps = hcd->regs;
> @@ -175,13 +206,15 @@ static int __devinit s5p_ehci_probe(struct platform_device *pdev)
>  	err = usb_add_hcd(hcd, irq, IRQF_SHARED);
>  	if (err) {
>  		dev_err(&pdev->dev, "Failed to add USB HCD\n");
> -		goto fail_io;
> +		goto fail_add_hcd;
>  	}
> 
>  	platform_set_drvdata(pdev, s5p_ehci);
> 
>  	return 0;
> 
> +fail_add_hcd:
> +	s5p_ehci_phy_disable(s5p_ehci);
>  fail_io:
>  	clk_disable(s5p_ehci->clk);
>  fail_clk:
> @@ -191,14 +224,12 @@ fail_clk:
> 
>  static int __devexit s5p_ehci_remove(struct platform_device *pdev)
>  {
> -	struct s5p_ehci_platdata *pdata = pdev->dev.platform_data;
>  	struct s5p_ehci_hcd *s5p_ehci = platform_get_drvdata(pdev);
>  	struct usb_hcd *hcd = s5p_ehci->hcd;
> 
>  	usb_remove_hcd(hcd);
> 
> -	if (pdata && pdata->phy_exit)
> -		pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
> +	s5p_ehci_phy_disable(s5p_ehci);
> 
>  	clk_disable(s5p_ehci->clk);
> 
> @@ -222,14 +253,11 @@ static int s5p_ehci_suspend(struct device *dev)
>  	struct s5p_ehci_hcd *s5p_ehci = dev_get_drvdata(dev);
>  	struct usb_hcd *hcd = s5p_ehci->hcd;
>  	bool do_wakeup = device_may_wakeup(dev);
> -	struct platform_device *pdev = to_platform_device(dev);
> -	struct s5p_ehci_platdata *pdata = pdev->dev.platform_data;
>  	int rc;
> 
>  	rc = ehci_suspend(hcd, do_wakeup);
> 
> -	if (pdata && pdata->phy_exit)
> -		pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
> +	s5p_ehci_phy_disable(s5p_ehci);
> 
>  	clk_disable(s5p_ehci->clk);
> 
> @@ -240,13 +268,10 @@ static int s5p_ehci_resume(struct device *dev)
>  {
>  	struct s5p_ehci_hcd *s5p_ehci = dev_get_drvdata(dev);
>  	struct usb_hcd *hcd = s5p_ehci->hcd;
> -	struct platform_device *pdev = to_platform_device(dev);
> -	struct s5p_ehci_platdata *pdata = pdev->dev.platform_data;
> 
>  	clk_enable(s5p_ehci->clk);
> 
> -	if (pdata && pdata->phy_init)
> -		pdata->phy_init(pdev, S5P_USB_PHY_HOST);
> +	s5p_ehci_phy_enable(s5p_ehci);
> 
>  	/* DMA burst Enable */
>  	writel(EHCI_INSNREG00_ENABLE_DMA_BURST, EHCI_INSNREG00(hcd->regs));
> --
> 1.7.6.5

[PATCH 4/4 v2] USB: ohci-exynos: Add phy driver support

[Vivek Gautam]

Adding the transceiver to ohci driver. Keeping the platform data
for continuing the smooth operation for boards which still uses it

Signed-off-by: Vivek Gautam <gautam.vivek-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org>
---
 drivers/usb/host/ohci-exynos.c |   65 +++++++++++++++++++++++++++------------
 1 files changed, 45 insertions(+), 20 deletions(-)

diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index 20a5008..a1c4eb3 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -15,14 +15,37 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/platform_data/usb-exynos.h>
+#include <linux/usb/phy.h>
 #include <plat/usb-phy.h>
 
 struct exynos_ohci_hcd {
 	struct device *dev;
 	struct usb_hcd *hcd;
 	struct clk *clk;
+	struct usb_phy *phy;
+	struct exynos4_ohci_platdata *pdata;
 };
 
+static void exynos_ohci_phy_enable(struct exynos_ohci_hcd *exynos_ohci)
+{
+	struct platform_device *pdev = to_platform_device(exynos_ohci->dev);
+
+	if (exynos_ohci->phy)
+		usb_phy_init(exynos_ohci->phy);
+	else if (exynos_ohci->pdata->phy_init)
+		exynos_ohci->pdata->phy_init(pdev, S5P_USB_PHY_HOST);
+}
+
+static void exynos_ohci_phy_disable(struct exynos_ohci_hcd *exynos_ohci)
+{
+	struct platform_device *pdev = to_platform_device(exynos_ohci->dev);
+
+	if (exynos_ohci->phy)
+		usb_phy_shutdown(exynos_ohci->phy);
+	else if (exynos_ohci->pdata->phy_exit)
+		exynos_ohci->pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
+}
+
 static int ohci_exynos_start(struct usb_hcd *hcd)
 {
 	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
@@ -81,15 +104,10 @@ static int __devinit exynos_ohci_probe(struct platform_device *pdev)
 	struct usb_hcd *hcd;
 	struct ohci_hcd *ohci;
 	struct resource *res;
+	struct usb_phy *phy;
 	int irq;
 	int err;
 
-	pdata = pdev->dev.platform_data;
-	if (!pdata) {
-		dev_err(&pdev->dev, "No platform data defined\n");
-		return -EINVAL;
-	}
-
 	/*
 	 * Right now device-tree probed devices don't get dma_mask set.
 	 * Since shared usb code relies on it, set it here for now.
@@ -105,6 +123,20 @@ static int __devinit exynos_ohci_probe(struct platform_device *pdev)
 	if (!exynos_ohci)
 		return -ENOMEM;
 
+	pdata = pdev->dev.platform_data;
+	if (!pdata) {
+		/* Fallback to Phy transceiver */
+		phy = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
+		if (IS_ERR_OR_NULL(phy)) {
+			dev_err(&pdev->dev, "no platform data or transceiver defined\n");
+			return -EPROBE_DEFER;
+		} else {
+			exynos_ohci->phy = phy;
+		}
+	} else {
+		exynos_ohci->pdata = pdata;
+	}
+
 	exynos_ohci->dev = &pdev->dev;
 
 	hcd = usb_create_hcd(&exynos_ohci_hc_driver, &pdev->dev,
@@ -150,8 +182,7 @@ static int __devinit exynos_ohci_probe(struct platform_device *pdev)
 		goto fail_io;
 	}
 
-	if (pdata->phy_init)
-		pdata->phy_init(pdev, S5P_USB_PHY_HOST);
+	exynos_ohci_phy_enable(exynos_ohci);
 
 	ohci = hcd_to_ohci(hcd);
 	ohci_hcd_init(ohci);
@@ -159,13 +190,15 @@ static int __devinit exynos_ohci_probe(struct platform_device *pdev)
 	err = usb_add_hcd(hcd, irq, IRQF_SHARED);
 	if (err) {
 		dev_err(&pdev->dev, "Failed to add USB HCD\n");
-		goto fail_io;
+		goto fail_add_hcd;
 	}
 
 	platform_set_drvdata(pdev, exynos_ohci);
 
 	return 0;
 
+fail_add_hcd:
+	exynos_ohci_phy_disable(exynos_ohci);
 fail_io:
 	clk_disable(exynos_ohci->clk);
 fail_clken:
@@ -177,14 +210,12 @@ fail_clk:
 
 static int __devexit exynos_ohci_remove(struct platform_device *pdev)
 {
-	struct exynos4_ohci_platdata *pdata = pdev->dev.platform_data;
 	struct exynos_ohci_hcd *exynos_ohci = platform_get_drvdata(pdev);
 	struct usb_hcd *hcd = exynos_ohci->hcd;
 
 	usb_remove_hcd(hcd);
 
-	if (pdata && pdata->phy_exit)
-		pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
+	exynos_ohci_phy_disable(exynos_ohci);
 
 	clk_disable(exynos_ohci->clk);
 	clk_put(exynos_ohci->clk);
@@ -209,8 +240,6 @@ static int exynos_ohci_suspend(struct device *dev)
 	struct exynos_ohci_hcd *exynos_ohci = dev_get_drvdata(dev);
 	struct usb_hcd *hcd = exynos_ohci->hcd;
 	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
-	struct platform_device *pdev = to_platform_device(dev);
-	struct exynos4_ohci_platdata *pdata = pdev->dev.platform_data;
 	unsigned long flags;
 	int rc = 0;
 
@@ -229,8 +258,7 @@ static int exynos_ohci_suspend(struct device *dev)
 
 	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
 
-	if (pdata && pdata->phy_exit)
-		pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
+	exynos_ohci_phy_disable(exynos_ohci);
 
 	clk_disable(exynos_ohci->clk);
 
@@ -244,13 +272,10 @@ static int exynos_ohci_resume(struct device *dev)
 {
 	struct exynos_ohci_hcd *exynos_ohci = dev_get_drvdata(dev);
 	struct usb_hcd *hcd = exynos_ohci->hcd;
-	struct platform_device *pdev = to_platform_device(dev);
-	struct exynos4_ohci_platdata *pdata = pdev->dev.platform_data;
 
 	clk_enable(exynos_ohci->clk);
 
-	if (pdata && pdata->phy_init)
-		pdata->phy_init(pdev, S5P_USB_PHY_HOST);
+	exynos_ohci_phy_enable(exynos_ohci);
 
 	/* Mark hardware accessible again as we are out of D3 state by now */
 	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
-- 
1.7.6.5

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RE: [PATCH 4/4 v2] USB: ohci-exynos: Add phy driver support

[Jingoo Han]

On Wednesday, October 10, 2012 7:43 PM Vivek Gautam wrote
> 
> Adding the transceiver to ohci driver. Keeping the platform data
> for continuing the smooth operation for boards which still uses it
> 
> Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>


It looks good. I have tested this patch with Exynos5250.

Acked-by: Jingoo Han <jg1.han@samsung.com>


Best regards,
Jingoo Han


> ---
>  drivers/usb/host/ohci-exynos.c |   65 +++++++++++++++++++++++++++------------
>  1 files changed, 45 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
> index 20a5008..a1c4eb3 100644
> --- a/drivers/usb/host/ohci-exynos.c
> +++ b/drivers/usb/host/ohci-exynos.c
> @@ -15,14 +15,37 @@
>  #include <linux/of.h>
>  #include <linux/platform_device.h>
>  #include <linux/platform_data/usb-exynos.h>
> +#include <linux/usb/phy.h>
>  #include <plat/usb-phy.h>
> 
>  struct exynos_ohci_hcd {
>  	struct device *dev;
>  	struct usb_hcd *hcd;
>  	struct clk *clk;
> +	struct usb_phy *phy;
> +	struct exynos4_ohci_platdata *pdata;
>  };
> 
> +static void exynos_ohci_phy_enable(struct exynos_ohci_hcd *exynos_ohci)
> +{
> +	struct platform_device *pdev = to_platform_device(exynos_ohci->dev);
> +
> +	if (exynos_ohci->phy)
> +		usb_phy_init(exynos_ohci->phy);
> +	else if (exynos_ohci->pdata->phy_init)
> +		exynos_ohci->pdata->phy_init(pdev, S5P_USB_PHY_HOST);
> +}
> +
> +static void exynos_ohci_phy_disable(struct exynos_ohci_hcd *exynos_ohci)
> +{
> +	struct platform_device *pdev = to_platform_device(exynos_ohci->dev);
> +
> +	if (exynos_ohci->phy)
> +		usb_phy_shutdown(exynos_ohci->phy);
> +	else if (exynos_ohci->pdata->phy_exit)
> +		exynos_ohci->pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
> +}
> +
>  static int ohci_exynos_start(struct usb_hcd *hcd)
>  {
>  	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
> @@ -81,15 +104,10 @@ static int __devinit exynos_ohci_probe(struct platform_device *pdev)
>  	struct usb_hcd *hcd;
>  	struct ohci_hcd *ohci;
>  	struct resource *res;
> +	struct usb_phy *phy;
>  	int irq;
>  	int err;
> 
> -	pdata = pdev->dev.platform_data;
> -	if (!pdata) {
> -		dev_err(&pdev->dev, "No platform data defined\n");
> -		return -EINVAL;
> -	}
> -
>  	/*
>  	 * Right now device-tree probed devices don't get dma_mask set.
>  	 * Since shared usb code relies on it, set it here for now.
> @@ -105,6 +123,20 @@ static int __devinit exynos_ohci_probe(struct platform_device *pdev)
>  	if (!exynos_ohci)
>  		return -ENOMEM;
> 
> +	pdata = pdev->dev.platform_data;
> +	if (!pdata) {
> +		/* Fallback to Phy transceiver */
> +		phy = devm_usb_get_phy(&pdev->dev, USB_PHY_TYPE_USB2);
> +		if (IS_ERR_OR_NULL(phy)) {
> +			dev_err(&pdev->dev, "no platform data or transceiver defined\n");
> +			return -EPROBE_DEFER;
> +		} else {
> +			exynos_ohci->phy = phy;
> +		}
> +	} else {
> +		exynos_ohci->pdata = pdata;
> +	}
> +
>  	exynos_ohci->dev = &pdev->dev;
> 
>  	hcd = usb_create_hcd(&exynos_ohci_hc_driver, &pdev->dev,
> @@ -150,8 +182,7 @@ static int __devinit exynos_ohci_probe(struct platform_device *pdev)
>  		goto fail_io;
>  	}
> 
> -	if (pdata->phy_init)
> -		pdata->phy_init(pdev, S5P_USB_PHY_HOST);
> +	exynos_ohci_phy_enable(exynos_ohci);
> 
>  	ohci = hcd_to_ohci(hcd);
>  	ohci_hcd_init(ohci);
> @@ -159,13 +190,15 @@ static int __devinit exynos_ohci_probe(struct platform_device *pdev)
>  	err = usb_add_hcd(hcd, irq, IRQF_SHARED);
>  	if (err) {
>  		dev_err(&pdev->dev, "Failed to add USB HCD\n");
> -		goto fail_io;
> +		goto fail_add_hcd;
>  	}
> 
>  	platform_set_drvdata(pdev, exynos_ohci);
> 
>  	return 0;
> 
> +fail_add_hcd:
> +	exynos_ohci_phy_disable(exynos_ohci);
>  fail_io:
>  	clk_disable(exynos_ohci->clk);
>  fail_clken:
> @@ -177,14 +210,12 @@ fail_clk:
> 
>  static int __devexit exynos_ohci_remove(struct platform_device *pdev)
>  {
> -	struct exynos4_ohci_platdata *pdata = pdev->dev.platform_data;
>  	struct exynos_ohci_hcd *exynos_ohci = platform_get_drvdata(pdev);
>  	struct usb_hcd *hcd = exynos_ohci->hcd;
> 
>  	usb_remove_hcd(hcd);
> 
> -	if (pdata && pdata->phy_exit)
> -		pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
> +	exynos_ohci_phy_disable(exynos_ohci);
> 
>  	clk_disable(exynos_ohci->clk);
>  	clk_put(exynos_ohci->clk);
> @@ -209,8 +240,6 @@ static int exynos_ohci_suspend(struct device *dev)
>  	struct exynos_ohci_hcd *exynos_ohci = dev_get_drvdata(dev);
>  	struct usb_hcd *hcd = exynos_ohci->hcd;
>  	struct ohci_hcd *ohci = hcd_to_ohci(hcd);
> -	struct platform_device *pdev = to_platform_device(dev);
> -	struct exynos4_ohci_platdata *pdata = pdev->dev.platform_data;
>  	unsigned long flags;
>  	int rc = 0;
> 
> @@ -229,8 +258,7 @@ static int exynos_ohci_suspend(struct device *dev)
> 
>  	clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
> 
> -	if (pdata && pdata->phy_exit)
> -		pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
> +	exynos_ohci_phy_disable(exynos_ohci);
> 
>  	clk_disable(exynos_ohci->clk);
> 
> @@ -244,13 +272,10 @@ static int exynos_ohci_resume(struct device *dev)
>  {
>  	struct exynos_ohci_hcd *exynos_ohci = dev_get_drvdata(dev);
>  	struct usb_hcd *hcd = exynos_ohci->hcd;
> -	struct platform_device *pdev = to_platform_device(dev);
> -	struct exynos4_ohci_platdata *pdata = pdev->dev.platform_data;
> 
>  	clk_enable(exynos_ohci->clk);
> 
> -	if (pdata && pdata->phy_init)
> -		pdata->phy_init(pdev, S5P_USB_PHY_HOST);
> +	exynos_ohci_phy_enable(exynos_ohci);
> 
>  	/* Mark hardware accessible again as we are out of D3 state by now */
>  	set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
> --
> 1.7.6.5