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Thu, 13 Nov 2025 23:07:09 -0800 (PST) Message-ID: <0109a90fc464e3cc63dd6c11e699db0143906256.camel@icenowy.me> Subject: Re: [PATCH RFC 01/13] dt-bindings: soc: starfive: Add vout-subsystem IP block From: Icenowy Zheng To: Conor Dooley Cc: Michal Wilczynski , Rob Herring , Krzysztof Kozlowski , Emil Renner Berthing , Hal Feng , Michael Turquette , Stephen Boyd , Conor Dooley , Xingyu Wu , Vinod Koul , Kishon Vijay Abraham I , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Lee Jones , Philipp Zabel , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , Maud Spierings , Andy Yan , Heiko Stuebner , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-phy@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-riscv@lists.infradead.org Date: Fri, 14 Nov 2025 15:06:55 +0800 In-Reply-To: <20251113-irritable-unfold-da619d52026c@spud> References: <20251108-jh7110-clean-send-v1-0-06bf43bb76b1@samsung.com> <20251108-jh7110-clean-send-v1-1-06bf43bb76b1@samsung.com> <20251111-massager-twistable-1e88f03d82f8@spud> <20251111-unsaid-rockslide-67b88b2e34bd@spud> <0d8e3a626b037dd348378e5ebca8005c1e715871.camel@icenowy.me> <20251112-skating-robust-81be8dee0a8b@spud> <1d54524d7ef939232b4512ca59c78794484103ca.camel@icenowy.me> <20251113-irritable-unfold-da619d52026c@spud> Organization: Anthon Open-Source Community Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.44.4 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ZohoMailClient: External =E5=9C=A8 2025-11-13=E6=98=9F=E6=9C=9F=E5=9B=9B=E7=9A=84 19:44 +0000=EF=BC= =8CConor Dooley=E5=86=99=E9=81=93=EF=BC=9A > On Thu, Nov 13, 2025 at 08:48:33AM +0800, Icenowy Zheng wrote: > > =E5=9C=A8 2025-11-12=E6=98=9F=E6=9C=9F=E4=B8=89=E7=9A=84 18:36 +0000=EF= =BC=8CConor Dooley=E5=86=99=E9=81=93=EF=BC=9A > > > On Wed, Nov 12, 2025 at 02:34:39PM +0800, Icenowy Zheng wrote: > > > > =E5=9C=A8 2025-11-11=E6=98=9F=E6=9C=9F=E4=BA=8C=E7=9A=84 18:36 +000= 0=EF=BC=8CConor Dooley=E5=86=99=E9=81=93=EF=BC=9A > > > > > On Tue, Nov 11, 2025 at 06:18:16PM +0000, Conor Dooley wrote: > > > > > > On Sat, Nov 08, 2025 at 02:04:35AM +0100, Michal Wilczynski > > > > > > wrote: > > > > > > > Add the dt-binding documentation for the StarFive JH7110 > > > > > > > Video > > >=20 > > > > > > > +patternProperties: > > > > > > > +=C2=A0 "^display@[0-9a-f]+$": > > > > > >=20 > > > > > > Personally I'd like to see these being regular properties, > > > > > > since > > > > > > there's > > > > > > exactly one possible setup for this. > > > > > >=20 > > > > > > > +=C2=A0=C2=A0=C2=A0 type: object > > > > > > > +=C2=A0=C2=A0=C2=A0 description: Verisilicon DC8200 Display C= ontroller > > > > > > > node. > > > > > >=20 > > > > > > Can you add the relevant references here instead of > > > > > > allowing > > > > > > any > > > > > > object? > > > > >=20 > > > > > I don't think that if you did, this would pass the binding > > > > > checks, > > > > > because there's no "verisilicon,dc" binding. I think I saw > > > > > one in > > > > > progress, but without the soc-specific compatible that I am > > > > > going > > > > > to > > > > > require here - if for no reason other than making sure that > > > > > the > > > > > clocks > > > > > etc are provided correctly for this device. > > > >=20 > > > > Well I didn't specify any soc-specific compatible because that > > > > IP > > > > has > > > > its own identification registers. > > >=20 > > > I still require one because I want to make sure that clocks etc > > > are > > > handled correctly. You can ignore it in the driver if you wish, > > > but > > > when > > > the next user comes along with one more or less clock, I want the > > > jh7110 one to be forced to use the correct configuration. > >=20 > > I don't think for those generic IPs requiring a SoC-specific > > compatible > > is a good idea. >=20 > I disagree. If things are complex enough to end up with different > numbers of clocks or power-domains etc on different platforms (which > I > believe GPUs are) then I want one for validation purposes on > platforms I > care about. What you do in the driver is up to you. Well I think Vivante GPUs do have such case -- a "shader" clock that is only present when 3D support is here. But that binding still contains only "vivante,gc" and the maintainer of etnaviv rejects extra compatible strings. In addition, as the addition of SoC-specific compatible string and the real DT are usually written by the same person at the same time, I don't think this introduces any more validation (because when the author gets things wrong they will just make it wrong at the two places).