From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D18EC433F5 for ; Tue, 1 Mar 2022 16:17:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229848AbiCAQS2 (ORCPT ); Tue, 1 Mar 2022 11:18:28 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49002 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231856AbiCAQS1 (ORCPT ); Tue, 1 Mar 2022 11:18:27 -0500 Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BFDEF50E00; Tue, 1 Mar 2022 08:17:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646151466; x=1677687466; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=Ic2cVNr/QuZ8LZWxFs/I0VO4RNQe/bRpOebdDp7iddI=; b=PyL8bOWFA7TbskcVwh74luGZn/mFymLikmVju3vDgJjWIUXwqN/VUaK6 kU/KjifKtX41mbfvfvH8MM9rHMXUztBhC0qfHrlBR4VYxLQDzQFcQboq6 asGTBs8lkCwaCpQhHl0B8Ok26vH/tf+2T4O4SgLTniuXZ0MJ5y4DbEVFd TXq+EcMYwpp8oyExPu0jeUM+jgAW0PCs17oEFUTKJKQz2p3XWxAhPUdQh FnmfRT9u+mV8s4wfHtnveNOPg/QdZsRx8XaT8FS16YXfLvkIC5IU/EygJ zCceDtRA51OdzIEdriloKRZAEJE50NQs/3TasNF9eL7hPYrLwunoHae61 Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10272"; a="339600528" X-IronPort-AV: E=Sophos;i="5.90,146,1643702400"; d="scan'208";a="339600528" Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2022 08:17:46 -0800 X-IronPort-AV: E=Sophos;i="5.90,146,1643702400"; d="scan'208";a="545146467" Received: from rbrosius-mobl.amr.corp.intel.com (HELO [10.209.131.146]) ([10.209.131.146]) by fmsmga007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 01 Mar 2022 08:17:45 -0800 Message-ID: <01184946-ebdc-52f1-65d9-e2905be0474e@linux.intel.com> Date: Tue, 1 Mar 2022 07:51:22 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Firefox/91.0 Thunderbird/91.5.0 Subject: Re: [PATCH v3 3/3] soundwire: qcom: add in-band wake up interrupt support Content-Language: en-US To: Srinivas Kandagatla , robh+dt@kernel.org, vkoul@kernel.org, yung-chuan.liao@linux.intel.com Cc: devicetree@vger.kernel.org, alsa-devel@alsa-project.org, linux-kernel@vger.kernel.org, quic_srivasam@quicinc.com References: <20220228172528.3489-1-srinivas.kandagatla@linaro.org> <20220228172528.3489-4-srinivas.kandagatla@linaro.org> <28a7aa9b-8322-54df-1cfa-275805e2b044@linux.intel.com> From: Pierre-Louis Bossart In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 3/1/22 05:13, Srinivas Kandagatla wrote: > > > On 28/02/2022 18:01, Pierre-Louis Bossart wrote: >> >>> @@ -1424,6 +1464,11 @@ static int swrm_runtime_resume(struct device >>> *dev) >>>       struct qcom_swrm_ctrl *ctrl = dev_get_drvdata(dev); >>>       int ret; >>>   +    if (ctrl->wake_irq > 0) { >>> +        if (!irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) >>> +            disable_irq_nosync(ctrl->wake_irq); >>> +    } >>> + >>>       clk_prepare_enable(ctrl->hclk); >> >> This one is quite interesting. If you disable the IRQ mechanism but >> haven't yet resumed the clock, that leaves a time window where the >> peripheral could attempt to drive the line high. what happens in that >> case? > > > We did call pm_runtime_get_sync() from Wake IRQ handler, which means > that resume should be finished as part of Wake IRQ handler. Any new > Interrupt conditions/status generated by slave in the meantime will be > cleared while handling SLAVE PEND interrupt. > >> >>>         if (ctrl->clock_stop_not_supported) { >>> @@ -1491,6 +1536,11 @@ static int __maybe_unused >>> swrm_runtime_suspend(struct device *dev) >>>         usleep_range(300, 305); >>>   +    if (ctrl->wake_irq > 0) { >>> +        if (irqd_irq_disabled(irq_get_irq_data(ctrl->wake_irq))) >>> +            enable_irq(ctrl->wake_irq); >>> +    } >>> + >> >> and this one is similar, you could have a case where the peripheral >> signals a wake immediately after the ClockStopNow frame, but you may not >> yet have enabled the wake detection interrupt. >> >> Would that imply that the wake is missed? > Its Possible it might be missed at that instance, however as the Slave > interrupt source condition/status (Ex: button Press) is still not > cleared it should generate a Wake interrupt as soon as its enabled. ok, thanks for the answers - both make sense.