From: "Pankaj Dubey" <pankaj.dubey@samsung.com>
To: "'Krzysztof Kozlowski'" <krzk@kernel.org>,
"'SeonGu Kang'" <ksk4725@coasia.com>,
"'Jesper Nilsson'" <jesper.nilsson@axis.com>,
"'Michael Turquette'" <mturquette@baylibre.com>,
"'Stephen Boyd'" <sboyd@kernel.org>,
"'Rob Herring'" <robh@kernel.org>,
"'Krzysztof Kozlowski'" <krzk+dt@kernel.org>,
"'Conor Dooley'" <conor+dt@kernel.org>,
"'Sylwester Nawrocki'" <s.nawrocki@samsung.com>,
"'Chanwoo Choi'" <cw00.choi@samsung.com>,
"'Alim Akhtar'" <alim.akhtar@samsung.com>,
"'Linus Walleij'" <linus.walleij@linaro.org>,
"'Tomasz Figa'" <tomasz.figa@gmail.com>,
"'Catalin Marinas'" <catalin.marinas@arm.com>,
"'Will Deacon'" <will@kernel.org>,
"'Arnd Bergmann'" <arnd@arndb.de>
Cc: "'kenkim'" <kenkim@coasia.com>,
"'Jongshin Park'" <pjsin865@coasia.com>,
"'GunWoo Kim'" <gwk1013@coasia.com>,
"'HaGyeong Kim'" <hgkim05@coasia.com>,
"'GyoungBo Min'" <mingyoungbo@coasia.com>,
"'SungMin Park'" <smn1196@coasia.com>,
"'Shradha Todi'" <shradha.t@samsung.com>,
"'Ravi Patel'" <ravi.patel@samsung.com>,
"'Inbaraj E'" <inbaraj.e@samsung.com>,
"'Swathi K S'" <swathi.ks@samsung.com>,
"'Hrishikesh'" <hrishikesh.d@samsung.com>,
"'Dongjin Yang'" <dj76.yang@samsung.com>,
"'Sang Min Kim'" <hypmean.kim@samsung.com>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-samsung-soc@vger.kernel.org>, <linux-arm-kernel@axis.com>,
<linux-clk@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-gpio@vger.kernel.org>, <soc@lists.linux.dev>
Subject: RE: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC
Date: Thu, 7 Aug 2025 12:26:27 +0530 [thread overview]
Message-ID: <013301dc0768$6f58dc40$4e0a94c0$@samsung.com> (raw)
In-Reply-To: <ef3b8e12-0677-4e49-bf2c-b8136c9a6908@kernel.org>
> Subject: Re: [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC
>
> On 06/08/2025 11:05, Pankaj Dubey wrote:
> >
> >> Also SAME strict DT compliance profile will be applied. (see more on
> >> that below)
> >>
> >>>
> >>> Given that ARTPEC-8 is a distinct SoC with its own set of IPs, we believe
> it's
> >> reasonable
> >>> to create a separate directory for it, similar to FSD.
> >>
> >> No. It was a mistake for FSD to keep it separate why? Because there is
> >> no single non-Samsung stuff there. I am afraid exactly the same will
> >> happen there.
> >>
> >
> > I am not sure, why you are saying this as a mistake, in case next version of
> FSD
>
>
> My mistake that I agreed on that, based on promise that "there will be
> non Samsung stuff" and that "non Samsung stuff" never happened.
>
I am not authorized to comment on FSD's non Samsung stuff at this moment.
But I got your point.
> > or ARTPEC is manufactured (ODM) by another vendor in that case, won't it
> > create problems?
>
>
> No problems here. Non-Samsung Artpec/Axis soc will not go there. It will
> go the top-level axis directory, just like artpec-6
>
Okay, understood. I assume Axis team will be fine with this approach.
Let me align with them internally and address all the review comments in v2.
>
> >
> > For example ARTPEC-6/7 (ARM based) have their own directories as
> "arch/arm/boot/dts/axis/"
> > These were not Samsung (ODM) manufactures SoCs.
> >
> > But ARTPEC-8/9 (ARM64) based SoCs are samsung manufactured. What if
> the next version say
> > ARTPEC-10 is not samsung manufactured, so different version of products
> (SoCs) from
> > same vendor (OEM), in this case Axis, will have code in separate directories
> and with different maintainers?
>
> It will be the same with Google Pixel for whatever they decide in the
> future. dts/exynos/google/ + dts/google/.
>
> I know that this is not ideal, but for me grouping samsung stuff
> together is far more important, because there is much, much more to
> share between two SoCs designed by Samsung, than Axis-9 and future
> non-Samsung Axis-10. And I have `git grep` as argument:
> git grep compatible -- arch/arm64/boot/dts/tesla/
>
> and point me to any Tesla IP. Zero results.
>
>
> >
> >> Based on above list of blocks this should be done like Google is done,
> >> so it goes as subdirectory of samsung (exynos). Can be called axis or
> >> artpec-8.
> >
> > I will suggest to keep axis, knowing the fact that sooner after artpec-8
> patches gets approved and merged
> > we have plan to upstream artpec-9 (ARM64, Samsung manufactured) as
> well.
> >
> >>
> >> To clarify: Only this SoC, not others which are not Samsung.
> >>
> >>>
> >>> We will remove Samsung and Coasia teams from the maintainers list in
> v2
> >> and only
> >>> Axis team will be maintainer.
> >>
> >> A bit unexpected or rather: just use names of people who WILL be
> >> maintaining it. If this is Jesper and Lars, great. Just don't add
> >> entries just because they are managers.
> >
> > AFAIK, Jesper will be taking care.
> >
> >>
> >>>
> >>> Maintainer list for previous generation of Axis chips (ARM based) is
> already
> >> present,
> >>> so this will be merged into that.
> >>
> >> Existing Artpec entry does not have tree mentioned, so if you choose
> >> above, you must not add the tree, since the tree is provided by Samsung
> SoC.
> >>
> >
> > OK
> >
> >> OTOH, how are you going to add there strict DT compliance? Existing axis
> >> is not following this, but artpec-8, as a Samsung derivative, MUST
> >> FOLLOW strict DT compliance. And this should be clearly marked in
> >> maintainer entry, just like everywhere else.
> >>
> >
> > As I said this is tricky situation, though artpec-8 is derivative of samsung, we
> can't confirm
> > if future versions (> 9) will be samsung derivative.
> >
> > But this would be case for all such custom ASIC manufactured by samsung,
> so I would like to
> > understand how this will be handled?
>
>
> I suggest to do the same as Google and when I say Google in this email,
> I mean Pixel/GS101. Google was easier because there was no prior entry
> and Axis has, so you will have two Axis entries. But I don't see how we
> can add clean-dts profiles to the existing Axis entry, if you decide to
> include Artpec-8 in that one.
>
Okay we will have separate dts profile aligned with Exynos DT compliance for
ARM64 based Axis SoCs which are manufactured by Samsung at this moment.
>
> Best regards,
> Krzysztof
next prev parent reply other threads:[~2025-08-07 6:56 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-10 0:20 [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC ksk4725
2025-07-10 0:20 ` [PATCH 01/16] dt-bindings: clock: Add CMU bindings definitions for ARTPEC-8 platform ksk4725
2025-07-10 7:07 ` Krzysztof Kozlowski
2025-07-21 4:31 ` Hakyeong Kim
2025-07-10 0:20 ` [PATCH 02/16] dt-bindings: clock: Add ARTPEC-8 CMU bindings ksk4725
2025-07-10 7:10 ` Krzysztof Kozlowski
2025-07-21 4:31 ` Hakyeong Kim
2025-07-10 0:20 ` [PATCH 03/16] clk: samsung: Add clock PLL support for ARTPEC-8 SoC ksk4725
2025-07-10 0:20 ` [PATCH 04/16] clk: samsung: artpec-8: Add initial clock support ksk4725
2025-07-10 7:12 ` Krzysztof Kozlowski
2025-07-21 4:32 ` Hakyeong Kim
2025-07-10 0:20 ` [PATCH 05/16] clk: samsung: artpec-8: Add clock support for CMU_CMU block ksk4725
2025-07-10 0:20 ` [PATCH 06/16] clk: samsung: artpec-8: Add clock support for CMU_BUS block ksk4725
2025-07-10 0:20 ` [PATCH 07/16] clk: samsung: artpec-8: Add clock support for CMU_CORE block ksk4725
2025-07-10 0:20 ` [PATCH 08/16] clk: samsung: artpec-8: Add clock support for CMU_CPUCL block ksk4725
2025-07-10 0:20 ` [PATCH 09/16] clk: samsung: artpec-8: Add clock support for CMU_FSYS block ksk4725
2025-07-10 0:20 ` [PATCH 10/16] clk: samsung: artpec-8: Add clock support for CMU_PERI block ksk4725
2025-07-10 7:13 ` Krzysztof Kozlowski
2025-07-21 4:32 ` Hakyeong Kim
2025-07-10 0:20 ` [PATCH 11/16] dt-bindings: pinctrl: samsung: Add compatible for ARTPEC-8 SoC ksk4725
2025-07-10 0:20 ` [PATCH 12/16] pinctrl: samsung: Add ARTPEC-8 SoC specific configuration ksk4725
2025-07-10 0:20 ` [PATCH 13/16] dt-bindings: arm: Add Axis ARTPEC SoC platform ksk4725
2025-07-10 7:15 ` Krzysztof Kozlowski
2025-07-21 6:36 ` sungmin
2025-07-10 0:20 ` [PATCH 14/16] arm64: dts: axis: Add initial device tree support ksk4725
2025-07-10 7:02 ` Krzysztof Kozlowski
2025-07-21 7:08 ` sungmin park
2025-07-21 7:17 ` Krzysztof Kozlowski
2025-07-10 7:48 ` Arnd Bergmann
2025-07-10 10:14 ` Krzysztof Kozlowski
2025-07-10 0:20 ` [PATCH 15/16] arm64: dts: axis: Add initial pinctrl support ksk4725
2025-07-10 7:04 ` Krzysztof Kozlowski
2025-07-21 4:48 ` SeonGu Kang
2025-07-10 0:20 ` [PATCH 16/16] arm64: defconfig: Enable Axis ARTPEC SoC ksk4725
2025-07-10 7:07 ` [PATCH 00/16] Add support for the Axis ARTPEC-8 SoC Krzysztof Kozlowski
2025-07-21 4:50 ` SeonGu Kang
2025-07-21 6:39 ` Krzysztof Kozlowski
2025-08-06 8:22 ` Pankaj Dubey
2025-08-06 8:36 ` Krzysztof Kozlowski
2025-08-06 9:05 ` Pankaj Dubey
2025-08-06 9:23 ` Krzysztof Kozlowski
2025-08-06 15:42 ` Arnd Bergmann
2025-08-07 6:56 ` Pankaj Dubey [this message]
2025-08-08 13:18 ` 'Jesper Nilsson'
2025-07-12 19:26 ` Linus Walleij
2025-07-21 4:32 ` Hakyeong Kim
[not found] ` <CGME20250821124014epcas5p12bacab10aac378f8d011fe7d2e04c8fa@epcas5p1.samsung.com>
2025-08-21 12:32 ` [PATCH v2 00/10] " Ravi Patel
[not found] ` <CGME20250821124019epcas5p42ac6e6abe1d3c8c9d69331596e51ad48@epcas5p4.samsung.com>
2025-08-21 12:32 ` [PATCH v2 01/10] dt-bindings: clock: Add ARTPEC-8 clock controller Ravi Patel
2025-08-22 19:39 ` Rob Herring (Arm)
[not found] ` <CGME20250821124024epcas5p349dda3c9e0523cc07acf2889476beeb1@epcas5p3.samsung.com>
2025-08-21 12:32 ` [PATCH v2 02/10] clk: samsung: Add clock PLL support for ARTPEC-8 SoC Ravi Patel
2025-08-22 6:32 ` Krzysztof Kozlowski
2025-08-22 12:08 ` Ravi Patel
[not found] ` <CGME20250821124029epcas5p1f04c643c243a7d388492b46341fb3c74@epcas5p1.samsung.com>
2025-08-21 12:32 ` [PATCH v2 03/10] clk: samsung: artpec-8: Add initial clock " Ravi Patel
[not found] ` <CGME20250821124034epcas5p350aeb42b9065fcbc3d9f713df1649574@epcas5p3.samsung.com>
2025-08-21 12:32 ` [PATCH v2 04/10] dt-bindings: pinctrl: samsung: Add compatible " Ravi Patel
2025-08-22 19:40 ` Rob Herring (Arm)
[not found] ` <CGME20250821124039epcas5p34b77813c9936b8b70c801e0e1b67891a@epcas5p3.samsung.com>
2025-08-21 12:32 ` [PATCH v2 05/10] pinctrl: samsung: Add ARTPEC-8 SoC specific configuration Ravi Patel
2025-08-21 16:50 ` Linus Walleij
[not found] ` <CGME20250821124045epcas5p37f0a50fb18e6f468a7c57ab406795419@epcas5p3.samsung.com>
2025-08-21 12:32 ` [PATCH v2 06/10] dt-bindings: arm: Convert Axis board/soc bindings to json-schema Ravi Patel
2025-08-22 19:41 ` Rob Herring (Arm)
[not found] ` <CGME20250821124050epcas5p22b08f66c69633f10986b7c19b3cd8cb4@epcas5p2.samsung.com>
2025-08-21 12:32 ` [PATCH v2 07/10] dt-bindings: arm: axis: Add ARTPEC-8 grizzly board Ravi Patel
2025-08-22 19:41 ` Rob Herring (Arm)
[not found] ` <CGME20250821124055epcas5p4d1072e9b4ef29587e0fd8606bc1abc4f@epcas5p4.samsung.com>
2025-08-21 12:32 ` [PATCH v2 08/10] arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support Ravi Patel
2025-08-22 6:38 ` Krzysztof Kozlowski
2025-08-22 11:48 ` Ravi Patel
[not found] ` <CGME20250821124100epcas5p42f719e140529823d9408b7325c646bbf@epcas5p4.samsung.com>
2025-08-21 12:32 ` [PATCH v2 09/10] arm64: dts: axis: Add ARTPEC-8 Grizzly dts support Ravi Patel
[not found] ` <CGME20250821124105epcas5p402a0f6ec6a893d0e5e305547976e4c80@epcas5p4.samsung.com>
2025-08-21 12:32 ` [PATCH v2 10/10] arm64: defconfig: Enable Axis ARTPEC SoC Ravi Patel
2025-08-22 6:26 ` [PATCH v2 00/10] Add support for the Axis ARTPEC-8 SoC Krzysztof Kozlowski
2025-08-22 11:50 ` Ravi Patel
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