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From: Alexandre TORGUE <alexandre.torgue@foss.st.com>
To: Patrick Delaunay <patrick.delaunay@foss.st.com>,
	Srinivas Kandagatla <srinivas.kandagatla@linaro.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Maxime Coquelin <mcoquelin.stm32@gmail.com>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>,
	Fabrice Gasnier <fabrice.gasnier@foss.st.com>
Cc: "Arnd Bergmann" <arnd@arndb.de>,
	"Bjorn Andersson" <quic_bjorande@quicinc.com>,
	"Dmitry Baryshkov" <dmitry.baryshkov@linaro.org>,
	"Geert Uytterhoeven" <geert+renesas@glider.be>,
	"Konrad Dybcio" <konrad.dybcio@linaro.org>,
	"Krzysztof Kozlowski" <krzysztof.kozlowski@linaro.org>,
	"Marek Szyprowski" <m.szyprowski@samsung.com>,
	"Neil Armstrong" <neil.armstrong@linaro.org>,
	"Nícolas F. R. A. Prado" <nfraprado@collabora.com>,
	"Peng Fan" <peng.fan@nxp.com>, "Udit Kumar" <u-kumar1@ti.com>,
	devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	linux-stm32@st-md-mailman.stormreply.com
Subject: Re: [PATCH 0/4] stm32: add support for STM32MP25 BSEC to control OTP data
Date: Thu, 14 Dec 2023 17:28:40 +0100	[thread overview]
Message-ID: <0145e75a-0d4c-4e34-a247-7852796f0552@foss.st.com> (raw)
In-Reply-To: <20231117143338.1173475-1-patrick.delaunay@foss.st.com>

Hi

On 11/17/23 15:33, Patrick Delaunay wrote:
> 
> Non volatile memory area is available on STM32MP25 with OTP in BSEC.
> 
> The 12 Kbits of OTP (effective) for STM32MP25x SoC Family
> are organized into the following regions:
> - lower OTP (OTP0 to OTP127) = 4096 lower OTP bits,
>    bitwise (1-bit) programmable
> - mid OTP (OTP128 to OTP255) = 4096 middle OTP bits,
>    bulk (32-bit) programmable
> - upper OTP (OTP256 to OTP383) = 4096 upper OTP bits,
>    bulk (32-bit) programmable,
>    only accessible when BSEC is in closed state.
> 
> BSEC is only accessible by secure world, so the OTP access is done
> by driver with OP-TEE TA, as on STM32MP13x family.
> 
> 
> 
> Patrick Delaunay (4):
>    dt-bindings: nvmem: add new stm32mp25 compatible for stm32-romem
>    nvmem: stm32: add support for STM32MP25 BSEC to control OTP data
>    arm64: defconfig: enable NVMEM STM32 ROMEM for stm32mp25
>    nvmem: add bsec support to stm32mp25
> 
>   .../bindings/nvmem/st,stm32-romem.yaml           |  1 +
>   arch/arm64/boot/dts/st/stm32mp251.dtsi           | 16 ++++++++++++++++
>   arch/arm64/configs/defconfig                     |  1 +
>   drivers/nvmem/stm32-romem.c                      | 16 ++++++++++++++++
>   4 files changed, 34 insertions(+)
> 


patch[4] (DT) applied on stm32-next.

thanks
Alex

      parent reply	other threads:[~2023-12-14 16:29 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-17 14:33 [PATCH 0/4] stm32: add support for STM32MP25 BSEC to control OTP data Patrick Delaunay
2023-11-17 14:33 ` [PATCH 1/4] dt-bindings: nvmem: add new stm32mp25 compatible for stm32-romem Patrick Delaunay
2023-11-19 13:42   ` Conor Dooley
2023-11-17 14:33 ` [PATCH 4/4] nvmem: add bsec support to stm32mp25 Patrick Delaunay
2023-11-20 14:15   ` Alexandre TORGUE
2023-12-08 11:03 ` (subset) [PATCH 0/4] stm32: add support for STM32MP25 BSEC to control OTP data Srinivas Kandagatla
2023-12-14 16:28 ` Alexandre TORGUE [this message]

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