From: William Qiu <william.qiu@starfivetech.com>
To: <devicetree@vger.kernel.org>, <linux-spi@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
"Emil Renner Berthing" <kernel@esmil.dk>,
Ziv Xu <ziv.xu@starfivetech.com>
Subject: Re: [PATCH v4 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC
Date: Tue, 18 Jul 2023 14:12:40 +0800 [thread overview]
Message-ID: <018b8bd3-ede0-d6ad-d50e-b4c959ac1660@starfivetech.com> (raw)
In-Reply-To: <ZLV2vqycWIA5TanD@aurel32.net>
On 2023/7/18 1:13, Aurelien Jarno wrote:
> Hi,
>
> On 2023-07-04 17:04, William Qiu wrote:
>> Add the quad spi controller node for the StarFive JH7110 SoC.
>>
>> Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com>
>> Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com>
>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
>> ---
>> .../jh7110-starfive-visionfive-2.dtsi | 32 +++++++++++++++++++
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 18 +++++++++++
>> 2 files changed, 50 insertions(+)
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> index 2a6d81609284..983b683e2f27 100644
>> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
>> @@ -126,6 +126,38 @@ &i2c6 {
>> status = "okay";
>> };
>>
>> +&qspi {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + nor_flash: flash@0 {
>> + compatible = "jedec,spi-nor";
>> + reg = <0>;
>> + cdns,read-delay = <5>;
>> + spi-max-frequency = <12000000>;
>> + cdns,tshsl-ns = <1>;
>> + cdns,tsd2d-ns = <1>;
>> + cdns,tchsh-ns = <1>;
>> + cdns,tslch-ns = <1>;
>> +
>> + partitions {
>> + compatible = "fixed-partitions";
>> + #address-cells = <1>;
>> + #size-cells = <1>;
>> +
>> + spl@0 {
>> + reg = <0x0 0x20000>;
>> + };
>> + uboot@100000 {
>> + reg = <0x100000 0x300000>;
>> + };
>> + data@f00000 {
>> + reg = <0xf00000 0x100000>;
>> + };
>
> It appears that this uses the old layout for the SPI flash. The new
> layout is described there:
>
> https://doc-en.rvspace.org/VisionFive2/Boot_UG/JH7110_SDK/boot_address_allocation.html
>
> Regards
> Aurelien
>
I'll take a look, and use it then.
Thanks for your comments.
Best regards,
William
next prev parent reply other threads:[~2023-07-18 6:14 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 9:04 [PATCH v4 0/3] Add initialization of clock for StarFive JH7110 SoC William Qiu
2023-07-04 9:04 ` [PATCH v4 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks " William Qiu
2023-07-04 9:04 ` [PATCH v4 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI William Qiu
2023-07-04 16:36 ` Conor Dooley
2023-07-04 16:41 ` Mark Brown
2023-07-05 7:02 ` William Qiu
2023-07-05 6:21 ` Krzysztof Kozlowski
2023-07-05 7:04 ` William Qiu
2023-07-05 7:23 ` Krzysztof Kozlowski
2023-07-05 8:31 ` William Qiu
2023-07-04 9:04 ` [PATCH v4 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC William Qiu
2023-07-04 9:43 ` Krzysztof Kozlowski
2023-07-05 7:05 ` William Qiu
2023-07-17 17:13 ` Aurelien Jarno
2023-07-18 6:12 ` William Qiu [this message]
2023-08-04 19:04 ` (subset) [PATCH v4 0/3] Add initialization of clock " Mark Brown
-- strict thread matches above, loose matches on Subject: below --
2023-07-04 9:19 [PATCH v1 0/2] Add SPI module " William Qiu
2023-07-04 9:19 ` [PATCH v4 3/3] riscv: dts: starfive: Add QSPI controller node " William Qiu
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