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Thu, 12 Jun 2025 03:22:33 -0700 (PDT) Received: from smtpclient.apple ([89.66.237.154]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-6086a551a2esm939584a12.1.2025.06.12.03.22.30 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Thu, 12 Jun 2025 03:22:32 -0700 (PDT) Content-Type: text/plain; charset=utf-8 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3826.600.51.1.1\)) Subject: Re: [PATCH 3/3] arm64: dts: rockchip: Add HDMI PHY PLL clock source to VOP2 on rk3576 From: Piotr Oniszczuk In-Reply-To: <20250612-rk3576-hdmitx-fix-v1-3-4b11007d8675@collabora.com> Date: Thu, 12 Jun 2025 12:22:19 +0200 Cc: Sandy Huang , =?utf-8?Q?Heiko_St=C3=BCbner?= , Andy Yan , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , kernel@collabora.com, Andy Yan , Krzysztof Kozlowski , dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org Content-Transfer-Encoding: quoted-printable Message-Id: <01D5D2D8-392B-4926-884E-1A4FB87C03CF@gmail.com> References: <20250612-rk3576-hdmitx-fix-v1-0-4b11007d8675@collabora.com> <20250612-rk3576-hdmitx-fix-v1-3-4b11007d8675@collabora.com> To: Cristian Ciocaltea X-Mailer: Apple Mail (2.3826.600.51.1.1) > Wiadomo=C5=9B=C4=87 napisana przez Cristian Ciocaltea = w dniu 11 cze 2025, o godz. 23:47: >=20 > Since commit c871a311edf0 ("phy: rockchip: samsung-hdptx: Setup TMDS > char rate via phy_configure_opts_hdmi"), the workaround of passing the > rate from DW HDMI QP bridge driver via phy_set_bus_width() became > partially broken, as it cannot reliably handle mode switches anymore. >=20 > Attempting to fix this up at PHY level would not only introduce > additional hacks, but it would also fail to adequately resolve the > display issues that are a consequence of the system CRU limitations. >=20 > Instead, proceed with the solution already implemented for RK3588: = make > use of the HDMI PHY PLL as a better suited DCLK source for VOP2. This > will not only address the aforementioned problem, but it should also > facilitate the proper operation of display modes up to 4K@60Hz. >=20 > It's worth noting that anything above 4K@30Hz still requires high TMDS > clock ratio and scrambling support, which hasn't been mainlined yet. >=20 > Fixes: d74b842cab08 ("arm64: dts: rockchip: Add vop for rk3576") > Cc: stable@vger.kernel.org > Signed-off-by: Cristian Ciocaltea > --- > arch/arm64/boot/dts/rockchip/rk3576.dtsi | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) >=20 > diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi = b/arch/arm64/boot/dts/rockchip/rk3576.dtsi > index = 6a13fe0c3513fb2ff7cd535aa70e3386c37696e4..b1ac23035dd789f0478bf10c78c74ef1= 67d94904 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi > @@ -1155,12 +1155,14 @@ vop: vop@27d00000 { > <&cru HCLK_VOP>, > <&cru DCLK_VP0>, > <&cru DCLK_VP1>, > - <&cru DCLK_VP2>; > + <&cru DCLK_VP2>, > + <&hdptxphy>; > clock-names =3D "aclk", > "hclk", > "dclk_vp0", > "dclk_vp1", > - "dclk_vp2"; > + "dclk_vp2", > + "pll_hdmiphy0"; > iommus =3D <&vop_mmu>; > power-domains =3D <&power RK3576_PD_VOP>; > rockchip,grf =3D <&sys_grf>; >=20 > --=20 > 2.49.0 >=20 >=20 > _______________________________________________ > Linux-rockchip mailing list > Linux-rockchip@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-rockchip Cristian, It fixes fractional hd modes for me on rk3576. Thx for this fix! =20