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([2a01:e0a:982:cbb0:c7ce:7756:462d:a8bd]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-35dd064aa6csm13842822f8f.93.2024.06.05.02.28.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 05 Jun 2024 02:28:42 -0700 (PDT) Message-ID: <01bde68a-88a7-46eb-860c-1375aa730bec@linaro.org> Date: Wed, 5 Jun 2024 11:28:41 +0200 Precedence: bulk X-Mailing-List: devicetree@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird From: neil.armstrong@linaro.org Reply-To: neil.armstrong@linaro.org Subject: Re: [PATCH 00/14] Add initial support for the Rockchip RK3588 HDMI TX Controller To: Andy Yan , Cristian Ciocaltea Cc: Heiko Stuebner , Andrzej Hajda , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Daniel Vetter , Sandy Huang , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Mark Yao , Andy Yan , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, kernel@collabora.com, Alexandre ARNOUD , Luis de Arquer , Algea Cao References: <20240601-b4-rk3588-bridge-upstream-v1-0-f6203753232b@collabora.com> <11359776.NyiUUSuA9g@phil> <4456bc5a.9b2d.18fe7b76790.Coremail.andyshrk@163.com> Content-Language: en-US, fr Autocrypt: addr=neil.armstrong@linaro.org; keydata= xsBNBE1ZBs8BCAD78xVLsXPwV/2qQx2FaO/7mhWL0Qodw8UcQJnkrWmgTFRobtTWxuRx8WWP GTjuhvbleoQ5Cxjr+v+1ARGCH46MxFP5DwauzPekwJUD5QKZlaw/bURTLmS2id5wWi3lqVH4 BVF2WzvGyyeV1o4RTCYDnZ9VLLylJ9bneEaIs/7cjCEbipGGFlfIML3sfqnIvMAxIMZrvcl9 qPV2k+KQ7q+aXavU5W+yLNn7QtXUB530Zlk/d2ETgzQ5FLYYnUDAaRl+8JUTjc0CNOTpCeik 80TZcE6f8M76Xa6yU8VcNko94Ck7iB4vj70q76P/J7kt98hklrr85/3NU3oti3nrIHmHABEB AAHNKk5laWwgQXJtc3Ryb25nIDxuZWlsLmFybXN0cm9uZ0BsaW5hcm8ub3JnPsLAkQQTAQoA OwIbIwULCQgHAwUVCgkICwUWAgMBAAIeAQIXgBYhBInsPQWERiF0UPIoSBaat7Gkz/iuBQJk Q5wSAhkBAAoJEBaat7Gkz/iuyhMIANiD94qDtUTJRfEW6GwXmtKWwl/mvqQtaTtZID2dos04 YqBbshiJbejgVJjy+HODcNUIKBB3PSLaln4ltdsV73SBcwUNdzebfKspAQunCM22Mn6FBIxQ GizsMLcP/0FX4en9NaKGfK6ZdKK6kN1GR9YffMJd2P08EO8mHowmSRe/ExAODhAs9W7XXExw UNCY4pVJyRPpEhv373vvff60bHxc1k/FF9WaPscMt7hlkbFLUs85kHtQAmr8pV5Hy9ezsSRa GzJmiVclkPc2BY592IGBXRDQ38urXeM4nfhhvqA50b/nAEXc6FzqgXqDkEIwR66/Gbp0t3+r yQzpKRyQif3OwE0ETVkGzwEIALyKDN/OGURaHBVzwjgYq+ZtifvekdrSNl8TIDH8g1xicBYp QTbPn6bbSZbdvfeQPNCcD4/EhXZuhQXMcoJsQQQnO4vwVULmPGgtGf8PVc7dxKOeta+qUh6+ SRh3vIcAUFHDT3f/Zdspz+e2E0hPV2hiSvICLk11qO6cyJE13zeNFoeY3ggrKY+IzbFomIZY 4yG6xI99NIPEVE9lNBXBKIlewIyVlkOaYvJWSV+p5gdJXOvScNN1epm5YHmf9aE2ZjnqZGoM Mtsyw18YoX9BqMFInxqYQQ3j/HpVgTSvmo5ea5qQDDUaCsaTf8UeDcwYOtgI8iL4oHcsGtUX oUk33HEAEQEAAcLAXwQYAQIACQUCTVkGzwIbDAAKCRAWmrexpM/4rrXiB/sGbkQ6itMrAIfn M7IbRuiSZS1unlySUVYu3SD6YBYnNi3G5EpbwfBNuT3H8//rVvtOFK4OD8cRYkxXRQmTvqa3 3eDIHu/zr1HMKErm+2SD6PO9umRef8V82o2oaCLvf4WeIssFjwB0b6a12opuRP7yo3E3gTCS KmbUuLv1CtxKQF+fUV1cVaTPMyT25Od+RC1K+iOR0F54oUJvJeq7fUzbn/KdlhA8XPGzwGRy 4zcsPWvwnXgfe5tk680fEKZVwOZKIEuJC3v+/yZpQzDvGYJvbyix0lHnrCzq43WefRHI5XTT QbM0WUIBIcGmq38+OgUsMYu4NzLu7uZFAcmp6h8g Organization: Linaro In-Reply-To: <4456bc5a.9b2d.18fe7b76790.Coremail.andyshrk@163.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Hi, On 05/06/2024 11:25, Andy Yan wrote: > > Hi, > > At 2024-06-05 04:33:57, "Cristian Ciocaltea" wrote: >> On 6/3/24 4:08 PM, neil.armstrong@linaro.org wrote: >>> Hi, >>> >>> On 03/06/2024 15:03, Heiko Stuebner wrote: >>>> Am Montag, 3. Juni 2024, 14:14:17 CEST schrieb Andy Yan: >>>>> Hi Neil: >>>>> >>>>> On 6/3/24 16:55, Neil Armstrong wrote: >>>>>> Hi Christian, >>>>>> >>>>>> On 01/06/2024 15:12, Cristian Ciocaltea wrote: >>>>>>> The RK3588 SoC family integrates a Quad-Pixel (QP) variant of the >>>>>>> Synopsys DesignWare HDMI TX controller used in the previous SoCs. >>>>>>> >>>>>>> It is HDMI 2.1 compliant and supports the following features, among >>>>>>> others: >>>>>>> >>>>>> . >>>>>> >>>>>> .. >>>>>> >>>>>>> * SCDC I2C DDC access >>>>>>> * TMDS Scrambler enabling 2160p@60Hz with RGB/YCbCr4:4:4 >>>>>>> * YCbCr4:2:0 enabling 2160p@60Hz at lower HDMI link speeds >>>>>>> * Multi-stream audio >>>>>>> * Enhanced Audio Return Channel (EARC) >>>>>> -> Those features were already supported by the HDMI 2.0a compliant >>>>>> HW, just >>>>>> list the _new_ features for HDMI 2.1 >>>>>> >>>>>> I did a quick review of your patchset and I don't understand why you >>>>>> need >>>>>> to add a separate dw-hdmi-qp.c since you only need simple variants >>>>>> of the I2C >>>>>> bus, infoframe and bridge setup. >>>>>> >>>>>> Can you elaborate further ? isn't this Quad-Pixel (QP) TX controller >>>>>> version >>>>>> detectable at runtime ? >>>>>> >>>>>> I would prefer to keep a single dw-hdmi driver if possible. >>>>> >>>>> >>>>> >>>>> The QP HDMI controller is a completely different variant with totally >>>>> different >>>>> registers layout, see PATCH 13/14. >>>>> I think make it a separate driver will be easier for development and >>>>> maintenance. >>>> >>>> I'm with Andy here. Trying to navigate a driver for two IP blocks really >>>> sounds taxing especially when both are so different. >> >> Thank you all for the valuable feedback! >> >>> I agree, I just wanted more details than "variant of the >>> Synopsys DesignWare HDMI TX controller", if the register mapping is 100% >>> different, and does not match at all with the old IP, then it's indeed time >>> to make a brand new driver, but instead of doing a mix up, it's time to >>> extract >>> the dw-hdmi code that could be common helpers into a dw-hdmi-common module >>> and use them. >> >> Sounds good, will handle this in v2. >> >>> As I see, no "driver" code can be shared, only DRM plumbings, so perhaps >>> those >>> plumbing code should go into the DRM core ? >>> >>> In any case, please add more details on the cover letter, including the >>> detailed >>> HW differrence and the design you chose so support this new IP. >> >> Andy, could you please help with a summary of the HW changes? >> The information I could provide is rather limited, since I don't have >> access to any DW IP datasheets and I'm also not familiar enough with the >> old variant. >> > Accurately, we should refer to it as an entirely new IP，it has nothing in common with > the current mainline dw-hdmi。 The only commonality is that they both come from > Synopsys DesignWare： > （1）It has a 100% different register mapping > （2）It supports FRL and DSC > （3）different configuration flow in many places。 > > So I have the same feeling with Heiko and Maxime： > The DW_HDMI_QP should have a separate driver and with it's own CONFIG such as DRM_DW_HDMI_QP in Kconfig. > and the rockchip part should also be split from dw_hdmi-rockchip.c. > I am sorry we mixed them in dw_hdmi-rockchip.c when we develop the bsp driver，but we really regretted this decision > when we repeatedly broke compatibility with dw-hdmi on other socs。 Yes please, and as I say, if there's code common with the old dw-hdmi, please add a common module if this code can't be moved in core bridge helpers. Neil > > > >>> Neil >>> >>>> >>>> Synopsis also created a new dsi controller for the DSI2 standard, with >>>> a vastly different registers layout. >>>> >>>> I guess at some point there is time to say this really is a new IP ;-) . >>>> >>>> >>>> Though while on that thought, I don't fully understand why both a >>>> compiled >>>> under the dw_hdmi kconfig symbol. People going for a minimal kernel might >>>> want one or the other, but not both for their specific board. >> >> Indeed, it makes sense to have a dedicated Kconfig option. This is >> mostly a leftover from downstream implementation, will fix in v2. >> >> Thanks again, >> Cristian >> >> _______________________________________________ >> linux-arm-kernel mailing list >> linux-arm-kernel@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-arm-kernel