[PATCH 00/10] Add SM8475 clock controller drivers

[PATCH 00/10] Add SM8475 clock controller drivers

[Danila Tikhonov]

This series adds support for SM8475 to SM8450 clock controller drivers.
Was tested on Nothing Phone (2) aka nothing-pong.

Based on this downstream commit:
https://git.codelinaro.org/clo/la/kernel/msm-5.10/-/commit/b051ec6bdc4b4884905002b2e75753e6f1238d20

To: Bjorn Andersson <andersson@kernel.org>
To: Michael Turquette <mturquette@baylibre.com>
To: Stephen Boyd <sboyd@kernel.org>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Philipp Zabel <p.zabel@pengutronix.de>
To: Vinod Koul <vkoul@kernel.org>
To: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
To: Jagadeesh Kona <quic_jkona@quicinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Konrad Dybcio <konradybcio@kernel.org>
To: Taniya Das <quic_tdas@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux@mainlining.org

Danila Tikhonov (10):
  dt-bindings: clock: qcom,gcc-sm8450: Add SM8475 GCC bindings
  clk: qcom: gcc-sm8450: Add SM8475 support
  dt-bindings: clock: qcom,sm8450-dispcc: Add SM8475 DISPCC bindings
  clk: qcom: dispcc-sm8450: Add SM8475 support
  dt-bindings: clock: qcom,sm8450-gpucc: Add SM8475 GPUCC bindings
  clk: qcom: gpucc-sm8450: Add SM8475 support
  dt-bindings: clock: qcom,sm8450-videocc: Add SM8475 VIDEOCC bindings
  clk: qcom: videocc-sm8450: Add SM8475 support
  dt-bindings: clock: qcom,sm8450-camcc: Add SM8475 CAMCC bindings
  clk: qcom: camcc-sm8450: Add SM8475 support

 .../bindings/clock/qcom,gcc-sm8450.yaml       |   8 +-
 .../bindings/clock/qcom,sm8450-camcc.yaml     |   2 +
 .../bindings/clock/qcom,sm8450-dispcc.yaml    |   5 +-
 .../bindings/clock/qcom,sm8450-gpucc.yaml     |   3 +
 .../bindings/clock/qcom,sm8450-videocc.yaml   |   2 +
 drivers/clk/qcom/Kconfig                      |  12 +-
 drivers/clk/qcom/camcc-sm8450.c               | 231 +++++++++++++++++-
 drivers/clk/qcom/dispcc-sm8450.c              |  49 +++-
 drivers/clk/qcom/gcc-sm8450.c                 | 182 +++++++++++++-
 drivers/clk/qcom/gpucc-sm8450.c               |  25 +-
 drivers/clk/qcom/videocc-sm8450.c             |  31 ++-
 include/dt-bindings/clock/qcom,gcc-sm8450.h   |   2 +
 include/dt-bindings/clock/qcom,sm8475-camcc.h |   1 +
 .../dt-bindings/clock/qcom,sm8475-dispcc.h    |   1 +
 include/dt-bindings/clock/qcom,sm8475-gcc.h   |   1 +
 include/dt-bindings/clock/qcom,sm8475-gpucc.h |   1 +
 .../dt-bindings/clock/qcom,sm8475-videocc.h   |   1 +
 include/dt-bindings/reset/qcom,sm8475-gpucc.h |   1 +
 18 files changed, 532 insertions(+), 26 deletions(-)
 create mode 120000 include/dt-bindings/clock/qcom,sm8475-camcc.h
 create mode 120000 include/dt-bindings/clock/qcom,sm8475-dispcc.h
 create mode 120000 include/dt-bindings/clock/qcom,sm8475-gcc.h
 create mode 120000 include/dt-bindings/clock/qcom,sm8475-gpucc.h
 create mode 120000 include/dt-bindings/clock/qcom,sm8475-videocc.h
 create mode 120000 include/dt-bindings/reset/qcom,sm8475-gpucc.h

-- 
2.45.2

[PATCH 01/10] dt-bindings: clock: qcom,gcc-sm8450: Add SM8475 GCC bindings

[Danila Tikhonov]

Add SM8475 GCC bindings, which are simply a symlink to the SM8450
bindings. Update the documentation with the new compatible.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
 .../devicetree/bindings/clock/qcom,gcc-sm8450.yaml        | 8 ++++++--
 include/dt-bindings/clock/qcom,gcc-sm8450.h               | 2 ++
 include/dt-bindings/clock/qcom,sm8475-gcc.h               | 1 +
 3 files changed, 9 insertions(+), 2 deletions(-)
 create mode 120000 include/dt-bindings/clock/qcom,sm8475-gcc.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
index d848361beeb3..c7d75ee2a23b 100644
--- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
@@ -13,11 +13,15 @@ description: |
   Qualcomm global clock control module provides the clocks, resets and power
   domains on SM8450
 
-  See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h
+  See also::
+    include/dt-bindings/clock/qcom,gcc-sm8450.h
+    include/dt-bindings/clock/qcom,sm8475-gcc.h
 
 properties:
   compatible:
-    const: qcom,gcc-sm8450
+    enum:
+      - qcom,gcc-sm8450
+      - qcom,sm8475-gcc
 
   clocks:
     items:
diff --git a/include/dt-bindings/clock/qcom,gcc-sm8450.h b/include/dt-bindings/clock/qcom,gcc-sm8450.h
index 9679410843a0..5f1f9ab71a22 100644
--- a/include/dt-bindings/clock/qcom,gcc-sm8450.h
+++ b/include/dt-bindings/clock/qcom,gcc-sm8450.h
@@ -194,6 +194,8 @@
 #define GCC_VIDEO_AXI0_CLK					182
 #define GCC_VIDEO_AXI1_CLK					183
 #define GCC_VIDEO_XO_CLK					184
+#define GCC_GPLL2						185
+#define GCC_GPLL3						186
 
 /* GCC resets */
 #define GCC_CAMERA_BCR						0
diff --git a/include/dt-bindings/clock/qcom,sm8475-gcc.h b/include/dt-bindings/clock/qcom,sm8475-gcc.h
new file mode 120000
index 000000000000..daafdd881892
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8475-gcc.h
@@ -0,0 +1 @@
+qcom,gcc-sm8450.h
\ No newline at end of file
-- 
2.45.2

[PATCH 02/10] clk: qcom: gcc-sm8450: Add SM8475 support

[Danila Tikhonov]

Add support to the SM8475 global clock controller by extending the
SM8450 global clock controller, which is almost identical but has some
minor differences.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
 drivers/clk/qcom/Kconfig      |   3 +-
 drivers/clk/qcom/gcc-sm8450.c | 182 +++++++++++++++++++++++++++++++++-
 2 files changed, 183 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 11ae28430dad..decb41c4a58e 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -1032,7 +1032,8 @@ config SM_GCC_8450
 	depends on ARM64 || COMPILE_TEST
 	select QCOM_GDSC
 	help
-	  Support for the global clock controller on SM8450 devices.
+	  Support for the global clock controller on SM8450 or SM8475
+	  devices.
 	  Say Y if you want to use peripheral devices such as UART,
 	  SPI, I2C, USB, SD/UFS, PCIe etc.
 
diff --git a/drivers/clk/qcom/gcc-sm8450.c b/drivers/clk/qcom/gcc-sm8450.c
index c445c271678a..83e8f1a5d51b 100644
--- a/drivers/clk/qcom/gcc-sm8450.c
+++ b/drivers/clk/qcom/gcc-sm8450.c
@@ -26,6 +26,8 @@ enum {
 	P_BI_TCXO,
 	P_GCC_GPLL0_OUT_EVEN,
 	P_GCC_GPLL0_OUT_MAIN,
+	P_GCC_GPLL2_OUT_EVEN,
+	P_GCC_GPLL3_OUT_EVEN,
 	P_GCC_GPLL4_OUT_MAIN,
 	P_GCC_GPLL9_OUT_MAIN,
 	P_PCIE_1_PHY_AUX_CLK,
@@ -36,6 +38,15 @@ enum {
 	P_USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK,
 };
 
+static struct clk_init_data gcc_gpll0_sm8475_init = {
+	.name = "gcc_gpll0",
+	.parent_data = &(const struct clk_parent_data){
+		.fw_name = "bi_tcxo",
+	},
+	.num_parents = 1,
+	.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
+};
+
 static struct clk_alpha_pll gcc_gpll0 = {
 	.offset = 0x0,
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
@@ -53,6 +64,15 @@ static struct clk_alpha_pll gcc_gpll0 = {
 	},
 };
 
+static struct clk_init_data gcc_gpll0_out_even_sm8475_init = {
+	.name = "gcc_gpll0_out_even",
+	.parent_hws = (const struct clk_hw*[]) {
+		&gcc_gpll0.clkr.hw,
+	},
+	.num_parents = 1,
+	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+};
+
 static const struct clk_div_table post_div_table_gcc_gpll0_out_even[] = {
 	{ 0x1, 2 },
 	{ }
@@ -75,6 +95,49 @@ static struct clk_alpha_pll_postdiv gcc_gpll0_out_even = {
 	},
 };
 
+static struct clk_alpha_pll gcc_gpll2 = {
+	.offset = 0x2000,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+	.clkr = {
+		.enable_reg = 0x62018,
+		.enable_mask = BIT(2),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_gpll2",
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "bi_tcxo",
+			},
+			.num_parents = 1,
+			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
+		},
+	},
+};
+
+static struct clk_alpha_pll gcc_gpll3 = {
+	.offset = 0x3000,
+	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE],
+	.clkr = {
+		.enable_reg = 0x62018,
+		.enable_mask = BIT(3),
+		.hw.init = &(struct clk_init_data){
+			.name = "gcc_gpll3",
+			.parent_data = &(const struct clk_parent_data){
+				.fw_name = "bi_tcxo",
+			},
+			.num_parents = 1,
+			.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
+		},
+	},
+};
+
+static struct clk_init_data gcc_gpll4_sm8475_init = {
+	.name = "gcc_gpll4",
+	.parent_data = &(const struct clk_parent_data){
+		.fw_name = "bi_tcxo",
+	},
+	.num_parents = 1,
+	.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
+};
+
 static struct clk_alpha_pll gcc_gpll4 = {
 	.offset = 0x4000,
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
@@ -92,6 +155,15 @@ static struct clk_alpha_pll gcc_gpll4 = {
 	},
 };
 
+static struct clk_init_data gcc_gpll9_sm8475_init = {
+	.name = "gcc_gpll9",
+	.parent_data = &(const struct clk_parent_data){
+		.fw_name = "bi_tcxo",
+	},
+	.num_parents = 1,
+	.ops = &clk_alpha_pll_fixed_lucid_ole_ops,
+};
+
 static struct clk_alpha_pll gcc_gpll9 = {
 	.offset = 0x9000,
 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO],
@@ -153,6 +225,22 @@ static const struct clk_parent_data gcc_parent_data_3[] = {
 	{ .fw_name = "bi_tcxo" },
 };
 
+static const struct parent_map gcc_parent_map_sm8475_3[] = {
+	{ P_BI_TCXO, 0 },
+	{ P_GCC_GPLL0_OUT_MAIN, 1 },
+	{ P_GCC_GPLL2_OUT_EVEN, 2 },
+	{ P_GCC_GPLL3_OUT_EVEN, 3 },
+	{ P_GCC_GPLL0_OUT_EVEN, 6 },
+};
+
+static const struct clk_parent_data gcc_parent_data_sm8475_3[] = {
+	{ .fw_name = "bi_tcxo" },
+	{ .hw = &gcc_gpll0.clkr.hw },
+	{ .hw = &gcc_gpll2.clkr.hw },
+	{ .hw = &gcc_gpll3.clkr.hw },
+	{ .hw = &gcc_gpll0_out_even.clkr.hw },
+};
+
 static const struct parent_map gcc_parent_map_5[] = {
 	{ P_PCIE_1_PHY_AUX_CLK, 0 },
 	{ P_BI_TCXO, 2 },
@@ -915,6 +1003,16 @@ static struct clk_rcg2 gcc_qupv3_wrap2_s6_clk_src = {
 	.clkr.hw.init = &gcc_qupv3_wrap2_s6_clk_src_init,
 };
 
+static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src_sm8475[] = {
+	F(400000, P_BI_TCXO, 12, 1, 4),
+	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
+	F(37000000, P_GCC_GPLL9_OUT_MAIN, 16, 0, 0),
+	F(50000000, P_GCC_GPLL0_OUT_EVEN, 6, 0, 0),
+	F(100000000, P_GCC_GPLL0_OUT_EVEN, 3, 0, 0),
+	F(148000000, P_GCC_GPLL9_OUT_MAIN, 4, 0, 0),
+	{ }
+};
+
 static const struct freq_tbl ftbl_gcc_sdcc2_apps_clk_src[] = {
 	F(400000, P_BI_TCXO, 12, 1, 4),
 	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
@@ -963,6 +1061,25 @@ static struct clk_rcg2 gcc_sdcc4_apps_clk_src = {
 	},
 };
 
+static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src_sm8475[] = {
+	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
+	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
+	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
+	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
+	F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
+	F(806400000, P_GCC_GPLL2_OUT_EVEN, 1, 0, 0),
+	F(850000000, P_GCC_GPLL2_OUT_EVEN, 1, 0, 0),
+	{ }
+};
+
+static struct clk_init_data gcc_ufs_phy_axi_clk_src_sm8475_init = {
+	.name = "gcc_ufs_phy_axi_clk_src",
+	.parent_data = gcc_parent_data_sm8475_3,
+	.num_parents = ARRAY_SIZE(gcc_parent_map_sm8475_3),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
+};
+
 static const struct freq_tbl ftbl_gcc_ufs_phy_axi_clk_src[] = {
 	F(25000000, P_GCC_GPLL0_OUT_EVEN, 12, 0, 0),
 	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
@@ -987,6 +1104,24 @@ static struct clk_rcg2 gcc_ufs_phy_axi_clk_src = {
 	},
 };
 
+static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src_sm8475[] = {
+	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
+	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
+	F(300000000, P_GCC_GPLL0_OUT_MAIN, 2, 0, 0),
+	F(600000000, P_GCC_GPLL0_OUT_MAIN, 1, 0, 0),
+	F(806400000, P_GCC_GPLL2_OUT_EVEN, 1, 0, 0),
+	F(850000000, P_GCC_GPLL2_OUT_EVEN, 1, 0, 0),
+	{ }
+};
+
+static struct clk_init_data gcc_ufs_phy_ice_core_clk_src_sm8475_init = {
+	.name = "gcc_ufs_phy_ice_core_clk_src",
+	.parent_data = gcc_parent_data_sm8475_3,
+	.num_parents = ARRAY_SIZE(gcc_parent_map_sm8475_3),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
+};
+
 static const struct freq_tbl ftbl_gcc_ufs_phy_ice_core_clk_src[] = {
 	F(75000000, P_GCC_GPLL0_OUT_EVEN, 4, 0, 0),
 	F(150000000, P_GCC_GPLL0_OUT_MAIN, 4, 0, 0),
@@ -1032,6 +1167,14 @@ static struct clk_rcg2 gcc_ufs_phy_phy_aux_clk_src = {
 	},
 };
 
+static struct clk_init_data gcc_ufs_phy_unipro_core_clk_src_sm8475_init = {
+	.name = "gcc_ufs_phy_unipro_core_clk_src",
+	.parent_data = gcc_parent_data_sm8475_3,
+	.num_parents = ARRAY_SIZE(gcc_parent_map_sm8475_3),
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_rcg2_ops,
+};
+
 static struct clk_rcg2 gcc_ufs_phy_unipro_core_clk_src = {
 	.cmd_rcgr = 0x8708c,
 	.mnd_width = 0,
@@ -3166,6 +3309,8 @@ static struct clk_regmap *gcc_sm8450_clocks[] = {
 	[GCC_USB3_PRIM_PHY_PIPE_CLK_SRC] = &gcc_usb3_prim_phy_pipe_clk_src.clkr,
 	[GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr,
 	[GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
+	[GCC_GPLL2] = &gcc_gpll2.clkr,
+	[GCC_GPLL3] = &gcc_gpll3.clkr,
 };
 
 static const struct qcom_reset_map gcc_sm8450_resets[] = {
@@ -3259,6 +3404,7 @@ static const struct qcom_cc_desc gcc_sm8450_desc = {
 
 static const struct of_device_id gcc_sm8450_match_table[] = {
 	{ .compatible = "qcom,gcc-sm8450" },
+	{ .compatible = "qcom,sm8475-gcc" },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, gcc_sm8450_match_table);
@@ -3277,6 +3423,40 @@ static int gcc_sm8450_probe(struct platform_device *pdev)
 	if (ret)
 		return ret;
 
+	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-gcc")) {
+		/* Update GCC PLL0 Config */
+		gcc_gpll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+		gcc_gpll0.clkr.hw.init = &gcc_gpll0_sm8475_init;
+
+		gcc_gpll0_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+		gcc_gpll0_out_even.clkr.hw.init = &gcc_gpll0_out_even_sm8475_init;
+
+		/* Update GCC PLL4 Config */
+		gcc_gpll4.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+		gcc_gpll4.clkr.hw.init = &gcc_gpll4_sm8475_init;
+
+		/* Update GCC PLL9 Config */
+		gcc_gpll9.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+		gcc_gpll9.clkr.hw.init = &gcc_gpll9_sm8475_init;
+
+		gcc_sdcc2_apps_clk_src.freq_tbl = ftbl_gcc_sdcc2_apps_clk_src_sm8475;
+
+		gcc_ufs_phy_axi_clk_src.parent_map = gcc_parent_map_sm8475_3;
+		gcc_ufs_phy_axi_clk_src.freq_tbl = ftbl_gcc_ufs_phy_axi_clk_src_sm8475;
+		gcc_ufs_phy_axi_clk_src.clkr.hw.init = &gcc_ufs_phy_axi_clk_src_sm8475_init;
+
+		gcc_ufs_phy_ice_core_clk_src.parent_map = gcc_parent_map_sm8475_3;
+		gcc_ufs_phy_ice_core_clk_src.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src_sm8475;
+		gcc_ufs_phy_ice_core_clk_src.clkr.hw.init = &gcc_ufs_phy_ice_core_clk_src_sm8475_init;
+
+		gcc_ufs_phy_unipro_core_clk_src.parent_map = gcc_parent_map_sm8475_3;
+		gcc_ufs_phy_unipro_core_clk_src.freq_tbl = ftbl_gcc_ufs_phy_ice_core_clk_src_sm8475;
+		gcc_ufs_phy_unipro_core_clk_src.clkr.hw.init = &gcc_ufs_phy_unipro_core_clk_src_sm8475_init;
+	} else {
+		gcc_sm8450_desc.clks[GCC_GPLL2] = NULL;
+		gcc_sm8450_desc.clks[GCC_GPLL3] = NULL;
+	}
+
 	/* FORCE_MEM_CORE_ON for ufs phy ice core clocks */
 	regmap_update_bits(regmap, gcc_ufs_phy_ice_core_clk.halt_reg, BIT(14), BIT(14));
 
@@ -3312,5 +3492,5 @@ static void __exit gcc_sm8450_exit(void)
 }
 module_exit(gcc_sm8450_exit);
 
-MODULE_DESCRIPTION("QTI GCC SM8450 Driver");
+MODULE_DESCRIPTION("QTI GCC SM8450 / SM8475 Driver");
 MODULE_LICENSE("GPL v2");
-- 
2.45.2

[PATCH 03/10] dt-bindings: clock: qcom,sm8450-dispcc: Add SM8475 DISPCC bindings

[Danila Tikhonov]

Add SM8475 DISPCC bindings, which are simply a symlink to the SM8450
bindings. Update the documentation with the new compatible.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
 .../devicetree/bindings/clock/qcom,sm8450-dispcc.yaml        | 5 ++++-
 include/dt-bindings/clock/qcom,sm8475-dispcc.h               | 1 +
 2 files changed, 5 insertions(+), 1 deletion(-)
 create mode 120000 include/dt-bindings/clock/qcom,sm8475-dispcc.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml
index 4794c53793a8..76f5a8cc42cc 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml
@@ -13,12 +13,15 @@ description: |
   Qualcomm display clock control module provides the clocks, resets and power
   domains on SM8450.
 
-  See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h
+  See also::
+    include/dt-bindings/clock/qcom,sm8450-dispcc.h
+    include/dt-bindings/clock/qcom,sm8475-dispcc.h
 
 properties:
   compatible:
     enum:
       - qcom,sm8450-dispcc
+      - qcom,sm8475-dispcc
 
   clocks:
     minItems: 3
diff --git a/include/dt-bindings/clock/qcom,sm8475-dispcc.h b/include/dt-bindings/clock/qcom,sm8475-dispcc.h
new file mode 120000
index 000000000000..21a9db2d0f09
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8475-dispcc.h
@@ -0,0 +1 @@
+qcom,sm8450-dispcc.h
\ No newline at end of file
-- 
2.45.2

[PATCH 04/10] clk: qcom: dispcc-sm8450: Add SM8475 support

[Danila Tikhonov]

Add support to the SM8475 display clock controller by extending the
SM8450 display clock controller, which is almost identical but has
some minor differences.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
 drivers/clk/qcom/Kconfig         |  2 +-
 drivers/clk/qcom/dispcc-sm8450.c | 49 ++++++++++++++++++++++++++++++--
 2 files changed, 47 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index decb41c4a58e..702de741cedd 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -924,7 +924,7 @@ config SM_DISPCC_8450
 	depends on SM_GCC_8450
 	help
 	  Support for the display clock controller on Qualcomm Technologies, Inc
-	  SM8450 devices.
+	  SM8450 or SM8475 devices.
 	  Say Y if you want to support display devices and functionality such as
 	  splash screen.
 
diff --git a/drivers/clk/qcom/dispcc-sm8450.c b/drivers/clk/qcom/dispcc-sm8450.c
index d1d3f60789ee..cef38cdd7318 100644
--- a/drivers/clk/qcom/dispcc-sm8450.c
+++ b/drivers/clk/qcom/dispcc-sm8450.c
@@ -75,7 +75,7 @@ static const struct pll_vco lucid_evo_vco[] = {
 	{ 249600000, 2000000000, 0 },
 };
 
-static const struct alpha_pll_config disp_cc_pll0_config = {
+static struct alpha_pll_config disp_cc_pll0_config = {
 	.l = 0xD,
 	.alpha = 0x6492,
 	.config_ctl_val = 0x20485699,
@@ -85,6 +85,15 @@ static const struct alpha_pll_config disp_cc_pll0_config = {
 	.user_ctl_hi_val = 0x00000805,
 };
 
+static struct clk_init_data disp_cc_pll0_sm8475_init = {
+	.name = "disp_cc_pll0",
+	.parent_data = &(const struct clk_parent_data) {
+		.index = DT_BI_TCXO,
+	},
+	.num_parents = 1,
+	.ops = &clk_alpha_pll_reset_lucid_ole_ops,
+};
+
 static struct clk_alpha_pll disp_cc_pll0 = {
 	.offset = 0x0,
 	.vco_table = lucid_evo_vco,
@@ -102,7 +111,7 @@ static struct clk_alpha_pll disp_cc_pll0 = {
 	},
 };
 
-static const struct alpha_pll_config disp_cc_pll1_config = {
+static struct alpha_pll_config disp_cc_pll1_config = {
 	.l = 0x1F,
 	.alpha = 0x4000,
 	.config_ctl_val = 0x20485699,
@@ -112,6 +121,15 @@ static const struct alpha_pll_config disp_cc_pll1_config = {
 	.user_ctl_hi_val = 0x00000805,
 };
 
+static struct clk_init_data disp_cc_pll1_sm8475_init = {
+	.name = "disp_cc_pll1",
+	.parent_data = &(const struct clk_parent_data) {
+		.index = DT_BI_TCXO,
+	},
+	.num_parents = 1,
+	.ops = &clk_alpha_pll_reset_lucid_ole_ops,
+};
+
 static struct clk_alpha_pll disp_cc_pll1 = {
 	.offset = 0x1000,
 	.vco_table = lucid_evo_vco,
@@ -1746,6 +1764,7 @@ static struct qcom_cc_desc disp_cc_sm8450_desc = {
 
 static const struct of_device_id disp_cc_sm8450_match_table[] = {
 	{ .compatible = "qcom,sm8450-dispcc" },
+	{ .compatible = "qcom,sm8475-dispcc" },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, disp_cc_sm8450_match_table);
@@ -1769,6 +1788,30 @@ static int disp_cc_sm8450_probe(struct platform_device *pdev)
 		goto err_put_rpm;
 	}
 
+	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-dispcc")) {
+		/* Update DISPCC PLL0 Config */
+		disp_cc_pll0_config.config_ctl_hi1_val = 0x82aa299c;
+		disp_cc_pll0_config.test_ctl_val = 0x00000000;
+		disp_cc_pll0_config.test_ctl_hi_val = 0x00000003;
+		disp_cc_pll0_config.test_ctl_hi1_val = 0x00009000;
+		disp_cc_pll0_config.test_ctl_hi2_val = 0x00000034;
+		disp_cc_pll0_config.user_ctl_hi_val = 0x00000005;
+
+		disp_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+		disp_cc_pll0.clkr.hw.init = &disp_cc_pll0_sm8475_init;
+
+		/* Update DISPCC PLL1 Config */
+		disp_cc_pll1_config.config_ctl_hi1_val = 0x82aa299c;
+		disp_cc_pll1_config.test_ctl_val = 0x00000000;
+		disp_cc_pll1_config.test_ctl_hi_val = 0x00000003;
+		disp_cc_pll1_config.test_ctl_hi1_val = 0x00009000;
+		disp_cc_pll1_config.test_ctl_hi2_val = 0x00000034;
+		disp_cc_pll1_config.user_ctl_hi_val = 0x00000005;
+
+		disp_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+		disp_cc_pll1.clkr.hw.init = &disp_cc_pll1_sm8475_init;
+	}
+
 	clk_lucid_evo_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);
 	clk_lucid_evo_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);
 
@@ -1802,5 +1845,5 @@ static struct platform_driver disp_cc_sm8450_driver = {
 
 module_platform_driver(disp_cc_sm8450_driver);
 
-MODULE_DESCRIPTION("QTI DISPCC SM8450 Driver");
+MODULE_DESCRIPTION("QTI DISPCC SM8450 / SM8475 Driver");
 MODULE_LICENSE("GPL");
-- 
2.45.2

[PATCH 05/10] dt-bindings: clock: qcom,sm8450-gpucc: Add SM8475 GPUCC bindings

[Danila Tikhonov]

Add SM8475 GPUCC bindings, which are simply a symlink to the SM8450
bindings. Update the documentation with the new compatible.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
 Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml | 3 +++
 include/dt-bindings/clock/qcom,sm8475-gpucc.h                  | 1 +
 include/dt-bindings/reset/qcom,sm8475-gpucc.h                  | 1 +
 3 files changed, 5 insertions(+)
 create mode 120000 include/dt-bindings/clock/qcom,sm8475-gpucc.h
 create mode 120000 include/dt-bindings/reset/qcom,sm8475-gpucc.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
index d10bb002906e..608fe63fb43a 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
@@ -15,8 +15,10 @@ description: |
 
   See also::
     include/dt-bindings/clock/qcom,sm8450-gpucc.h
+    include/dt-bindings/clock/qcom,sm8475-gpucc.h
     include/dt-bindings/clock/qcom,sm8550-gpucc.h
     include/dt-bindings/reset/qcom,sm8450-gpucc.h
+    include/dt-bindings/reset/qcom,sm8475-gpucc.h
     include/dt-bindings/reset/qcom,sm8650-gpucc.h
     include/dt-bindings/reset/qcom,x1e80100-gpucc.h
 
@@ -24,6 +26,7 @@ properties:
   compatible:
     enum:
       - qcom,sm8450-gpucc
+      - qcom,sm8475-gpucc
       - qcom,sm8550-gpucc
       - qcom,sm8650-gpucc
       - qcom,x1e80100-gpucc
diff --git a/include/dt-bindings/clock/qcom,sm8475-gpucc.h b/include/dt-bindings/clock/qcom,sm8475-gpucc.h
new file mode 120000
index 000000000000..2ba622290833
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8475-gpucc.h
@@ -0,0 +1 @@
+qcom,sm8450-gpucc.h
\ No newline at end of file
diff --git a/include/dt-bindings/reset/qcom,sm8475-gpucc.h b/include/dt-bindings/reset/qcom,sm8475-gpucc.h
new file mode 120000
index 000000000000..2ba622290833
--- /dev/null
+++ b/include/dt-bindings/reset/qcom,sm8475-gpucc.h
@@ -0,0 +1 @@
+qcom,sm8450-gpucc.h
\ No newline at end of file
-- 
2.45.2

[PATCH 06/10] clk: qcom: gpucc-sm8450: Add SM8475 support

[Danila Tikhonov]

Add support to the SM8475 graphics clock controller by extending the
SM8450 graphics clock controller, which is almost identical but has
some minor differences.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
 drivers/clk/qcom/Kconfig        |  3 ++-
 drivers/clk/qcom/gpucc-sm8450.c | 25 ++++++++++++++++++++++++-
 2 files changed, 26 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 702de741cedd..eb2c8db95daf 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -1123,7 +1123,8 @@ config SM_GPUCC_8450
 	depends on ARM64 || COMPILE_TEST
 	select SM_GCC_8450
 	help
-	  Support for the graphics clock controller on SM8450 devices.
+	  Support for the graphics clock controller on SM8450 or SM8475
+	  devices.
 	  Say Y if you want to support graphics controller devices and
 	  functionality such as 3D graphics.
 
diff --git a/drivers/clk/qcom/gpucc-sm8450.c b/drivers/clk/qcom/gpucc-sm8450.c
index b3c5d6923cd2..35ebf93fdb66 100644
--- a/drivers/clk/qcom/gpucc-sm8450.c
+++ b/drivers/clk/qcom/gpucc-sm8450.c
@@ -736,6 +736,7 @@ static const struct qcom_cc_desc gpu_cc_sm8450_desc = {
 
 static const struct of_device_id gpu_cc_sm8450_match_table[] = {
 	{ .compatible = "qcom,sm8450-gpucc" },
+	{ .compatible = "qcom,sm8475-gpucc" },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, gpu_cc_sm8450_match_table);
@@ -748,6 +749,28 @@ static int gpu_cc_sm8450_probe(struct platform_device *pdev)
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
+	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-gpucc")) {
+		/* Update GPUCC PLL0 Config */
+		gpu_cc_pll0_config.config_ctl_hi1_val = 0x82aa299c;
+		gpu_cc_pll0_config.test_ctl_val = 0x00000000;
+		gpu_cc_pll0_config.test_ctl_hi_val = 0x00000003;
+		gpu_cc_pll0_config.test_ctl_hi1_val = 0x00009000;
+		gpu_cc_pll0_config.test_ctl_hi2_val = 0x00000034;
+		gpu_cc_pll0_config.user_ctl_hi_val = 0x00000005;
+
+		gpu_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+
+		/* Update GPUCC PLL1 Config */
+		gpu_cc_pll1_config.config_ctl_hi1_val = 0x82aa299c;
+		gpu_cc_pll1_config.test_ctl_val = 0x00000000;
+		gpu_cc_pll1_config.test_ctl_hi_val = 0x00000003;
+		gpu_cc_pll1_config.test_ctl_hi1_val = 0x00009000;
+		gpu_cc_pll1_config.test_ctl_hi2_val = 0x00000034;
+		gpu_cc_pll1_config.user_ctl_hi_val = 0x00000005;
+
+		gpu_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+	}
+
 	clk_lucid_evo_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
 	clk_lucid_evo_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
 
@@ -763,5 +786,5 @@ static struct platform_driver gpu_cc_sm8450_driver = {
 };
 module_platform_driver(gpu_cc_sm8450_driver);
 
-MODULE_DESCRIPTION("QTI GPU_CC SM8450 Driver");
+MODULE_DESCRIPTION("QTI GPU_CC SM8450 / SM8475 Driver");
 MODULE_LICENSE("GPL");
-- 
2.45.2

[PATCH 07/10] dt-bindings: clock: qcom,sm8450-videocc: Add SM8475 VIDEOCC bindings

[Danila Tikhonov]

Add SM8475 VIDEOCC bindings, which are simply a symlink to the SM8450
bindings. Update the documentation with the new compatible.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
 .../devicetree/bindings/clock/qcom,sm8450-videocc.yaml          | 2 ++
 include/dt-bindings/clock/qcom,sm8475-videocc.h                 | 1 +
 2 files changed, 3 insertions(+)
 create mode 120000 include/dt-bindings/clock/qcom,sm8475-videocc.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
index b2792b4bb554..9186d2ee87f8 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
@@ -16,12 +16,14 @@ description: |
 
   See also:
     include/dt-bindings/clock/qcom,sm8450-videocc.h
+    include/dt-bindings/clock/qcom,sm8475-videocc.h
     include/dt-bindings/clock/qcom,sm8650-videocc.h
 
 properties:
   compatible:
     enum:
       - qcom,sm8450-videocc
+      - qcom,sm8475-videocc
       - qcom,sm8550-videocc
       - qcom,sm8650-videocc
 
diff --git a/include/dt-bindings/clock/qcom,sm8475-videocc.h b/include/dt-bindings/clock/qcom,sm8475-videocc.h
new file mode 120000
index 000000000000..231cd153052c
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8475-videocc.h
@@ -0,0 +1 @@
+qcom,sm8450-videocc.h
\ No newline at end of file
-- 
2.45.2

[PATCH 08/10] clk: qcom: videocc-sm8450: Add SM8475 support

[Danila Tikhonov]

Add support to the SM8475 video clock controller by extending the
SM8450 video clock controller, which is almost identical but has some
minor differences.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
 drivers/clk/qcom/Kconfig          |  2 +-
 drivers/clk/qcom/videocc-sm8450.c | 31 ++++++++++++++++++++++++++++---
 2 files changed, 29 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index eb2c8db95daf..60e70bf69cb9 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -1258,7 +1258,7 @@ config SM_VIDEOCC_8450
 	select QCOM_GDSC
 	help
 	  Support for the video clock controller on Qualcomm Technologies, Inc.
-	  SM8450 devices.
+	  SM8450 or SM8475 devices.
 	  Say Y if you want to support video devices and functionality such as
 	  video encode/decode.
 endif
diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-sm8450.c
index ed9163d64244..14d18e73332e 100644
--- a/drivers/clk/qcom/videocc-sm8450.c
+++ b/drivers/clk/qcom/videocc-sm8450.c
@@ -35,7 +35,7 @@ static const struct pll_vco lucid_evo_vco[] = {
 	{ 249600000, 2020000000, 0 },
 };
 
-static const struct alpha_pll_config video_cc_pll0_config = {
+static struct alpha_pll_config video_cc_pll0_config = {
 	/* .l includes CAL_L_VAL, L_VAL fields */
 	.l = 0x0044001e,
 	.alpha = 0x0,
@@ -63,7 +63,7 @@ static struct clk_alpha_pll video_cc_pll0 = {
 	},
 };
 
-static const struct alpha_pll_config video_cc_pll1_config = {
+static struct alpha_pll_config video_cc_pll1_config = {
 	/* .l includes CAL_L_VAL, L_VAL fields */
 	.l = 0x0044002b,
 	.alpha = 0xc000,
@@ -397,6 +397,7 @@ static struct qcom_cc_desc video_cc_sm8450_desc = {
 
 static const struct of_device_id video_cc_sm8450_match_table[] = {
 	{ .compatible = "qcom,sm8450-videocc" },
+	{ .compatible = "qcom,sm8475-videocc" },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, video_cc_sm8450_match_table);
@@ -420,6 +421,30 @@ static int video_cc_sm8450_probe(struct platform_device *pdev)
 		return PTR_ERR(regmap);
 	}
 
+	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-videocc")) {
+		/* Update VideoCC PLL0 Config */
+		video_cc_pll0_config.l = 0x1e;
+		video_cc_pll0_config.config_ctl_hi1_val = 0x82aa299c;
+		video_cc_pll0_config.test_ctl_val = 0x00000000;
+		video_cc_pll0_config.test_ctl_hi_val = 0x00000003;
+		video_cc_pll0_config.test_ctl_hi1_val = 0x00009000;
+		video_cc_pll0_config.test_ctl_hi2_val = 0x00000034;
+		video_cc_pll0_config.user_ctl_hi_val = 0x00000005;
+
+		video_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+
+		/* Update VideoCC PLL1 Config */
+		video_cc_pll1_config.l = 0x2b;
+		video_cc_pll1_config.config_ctl_hi1_val = 0x82aa299c;
+		video_cc_pll1_config.test_ctl_val = 0x00000000;
+		video_cc_pll1_config.test_ctl_hi_val = 0x00000003;
+		video_cc_pll1_config.test_ctl_hi1_val = 0x00009000;
+		video_cc_pll1_config.test_ctl_hi2_val = 0x00000034;
+		video_cc_pll1_config.user_ctl_hi_val = 0x00000005;
+
+		video_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+	}
+
 	clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
 	clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
 
@@ -445,5 +470,5 @@ static struct platform_driver video_cc_sm8450_driver = {
 
 module_platform_driver(video_cc_sm8450_driver);
 
-MODULE_DESCRIPTION("QTI VIDEOCC SM8450 Driver");
+MODULE_DESCRIPTION("QTI VIDEOCC SM8450 / SM8475 Driver");
 MODULE_LICENSE("GPL");
-- 
2.45.2

[PATCH 09/10] dt-bindings: clock: qcom,sm8450-camcc: Add SM8475 CAMCC bindings

[Danila Tikhonov]

Add SM8475 CAMCC bindings, which are simply a symlink to the SM8450
bindings. Update the documentation with the new compatible.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
 Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 2 ++
 include/dt-bindings/clock/qcom,sm8475-camcc.h                  | 1 +
 2 files changed, 3 insertions(+)
 create mode 120000 include/dt-bindings/clock/qcom,sm8475-camcc.h

diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
index f58edfc10f4c..2dea246882c3 100644
--- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
@@ -17,6 +17,7 @@ description: |
   See also:
     include/dt-bindings/clock/qcom,sc8280xp-camcc.h
     include/dt-bindings/clock/qcom,sm8450-camcc.h
+    include/dt-bindings/clock/qcom,sm8475-camcc.h
     include/dt-bindings/clock/qcom,sm8550-camcc.h
     include/dt-bindings/clock/qcom,sm8650-camcc.h
     include/dt-bindings/clock/qcom,x1e80100-camcc.h
@@ -29,6 +30,7 @@ properties:
     enum:
       - qcom,sc8280xp-camcc
       - qcom,sm8450-camcc
+      - qcom,sm8475-camcc
       - qcom,sm8550-camcc
       - qcom,sm8650-camcc
       - qcom,x1e80100-camcc
diff --git a/include/dt-bindings/clock/qcom,sm8475-camcc.h b/include/dt-bindings/clock/qcom,sm8475-camcc.h
new file mode 120000
index 000000000000..45444160d465
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,sm8475-camcc.h
@@ -0,0 +1 @@
+qcom,sm8450-camcc.h
\ No newline at end of file
-- 
2.45.2

[PATCH 10/10] clk: qcom: camcc-sm8450: Add SM8475 support

[Danila Tikhonov]

Add support to the SM8475 camera clock controller by extending the
SM8450 camera clock controller, which is almost identical but has some
minor differences.

Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
---
 drivers/clk/qcom/Kconfig        |   2 +-
 drivers/clk/qcom/camcc-sm8450.c | 231 ++++++++++++++++++++++++++++++--
 2 files changed, 222 insertions(+), 11 deletions(-)

diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig
index 60e70bf69cb9..7a5d47019a45 100644
--- a/drivers/clk/qcom/Kconfig
+++ b/drivers/clk/qcom/Kconfig
@@ -839,7 +839,7 @@ config SM_CAMCC_8450
 	depends on ARM64 || COMPILE_TEST
 	select SM_GCC_8450
 	help
-	  Support for the camera clock controller on SM8450 devices.
+	  Support for the camera clock controller on SM8450 or SM8475 devices.
 	  Say Y if you want to support camera devices and camera functionality.
 
 config SM_CAMCC_8550
diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm8450.c
index 26b78eed15ef..75af91fc160f 100644
--- a/drivers/clk/qcom/camcc-sm8450.c
+++ b/drivers/clk/qcom/camcc-sm8450.c
@@ -54,9 +54,13 @@ static const struct pll_vco rivian_evo_vco[] = {
 	{ 864000000, 1056000000, 0 },
 };
 
+static const struct pll_vco rivian_ole_vco[] = {
+	{ 864000000, 1075000000, 0 },
+};
+
 static const struct clk_parent_data pll_parent_data_tcxo = { .index = DT_BI_TCXO };
 
-static const struct alpha_pll_config cam_cc_pll0_config = {
+static struct alpha_pll_config cam_cc_pll0_config = {
 	.l = 0x3e,
 	.alpha = 0x8000,
 	.config_ctl_val = 0x20485699,
@@ -86,6 +90,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll0_out_even[] = {
 	{ }
 };
 
+static struct clk_init_data cam_cc_pll0_out_even_sm8475_init = {
+	.name = "cam_cc_pll0_out_even",
+	.parent_hws = (const struct clk_hw*[]) {
+		&cam_cc_pll0.clkr.hw,
+	},
+	.num_parents = 1,
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+};
+
 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_even = {
 	.offset = 0x0,
 	.post_div_shift = 10,
@@ -109,6 +123,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll0_out_odd[] = {
 	{ }
 };
 
+static struct clk_init_data cam_cc_pll0_out_odd_sm8475_init = {
+	.name = "cam_cc_pll0_out_odd",
+	.parent_hws = (const struct clk_hw*[]) {
+		&cam_cc_pll0.clkr.hw,
+	},
+	.num_parents = 1,
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+};
+
 static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
 	.offset = 0x0,
 	.post_div_shift = 14,
@@ -127,7 +151,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = {
 	},
 };
 
-static const struct alpha_pll_config cam_cc_pll1_config = {
+static struct alpha_pll_config cam_cc_pll1_config = {
 	.l = 0x25,
 	.alpha = 0xeaaa,
 	.config_ctl_val = 0x20485699,
@@ -157,6 +181,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll1_out_even[] = {
 	{ }
 };
 
+static struct clk_init_data cam_cc_pll1_out_even_sm8475_init = {
+	.name = "cam_cc_pll1_out_even",
+	.parent_hws = (const struct clk_hw*[]) {
+		&cam_cc_pll1.clkr.hw,
+	},
+	.num_parents = 1,
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+};
+
 static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
 	.offset = 0x1000,
 	.post_div_shift = 10,
@@ -175,7 +209,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = {
 	},
 };
 
-static const struct alpha_pll_config cam_cc_pll2_config = {
+static struct alpha_pll_config cam_cc_pll2_config = {
 	.l = 0x32,
 	.alpha = 0x0,
 	.config_ctl_val = 0x90008820,
@@ -198,7 +232,7 @@ static struct clk_alpha_pll cam_cc_pll2 = {
 	},
 };
 
-static const struct alpha_pll_config cam_cc_pll3_config = {
+static struct alpha_pll_config cam_cc_pll3_config = {
 	.l = 0x2d,
 	.alpha = 0x0,
 	.config_ctl_val = 0x20485699,
@@ -228,6 +262,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll3_out_even[] = {
 	{ }
 };
 
+static struct clk_init_data cam_cc_pll3_out_even_sm8475_init = {
+	.name = "cam_cc_pll3_out_even",
+	.parent_hws = (const struct clk_hw*[]) {
+		&cam_cc_pll3.clkr.hw,
+	},
+	.num_parents = 1,
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+};
+
 static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
 	.offset = 0x3000,
 	.post_div_shift = 10,
@@ -246,7 +290,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = {
 	},
 };
 
-static const struct alpha_pll_config cam_cc_pll4_config = {
+static struct alpha_pll_config cam_cc_pll4_config = {
 	.l = 0x2d,
 	.alpha = 0x0,
 	.config_ctl_val = 0x20485699,
@@ -276,6 +320,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll4_out_even[] = {
 	{ }
 };
 
+static struct clk_init_data cam_cc_pll4_out_even_sm8475_init = {
+	.name = "cam_cc_pll4_out_even",
+	.parent_hws = (const struct clk_hw*[]) {
+		&cam_cc_pll4.clkr.hw,
+	},
+	.num_parents = 1,
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+};
+
 static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
 	.offset = 0x4000,
 	.post_div_shift = 10,
@@ -294,7 +348,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll4_out_even = {
 	},
 };
 
-static const struct alpha_pll_config cam_cc_pll5_config = {
+static struct alpha_pll_config cam_cc_pll5_config = {
 	.l = 0x2d,
 	.alpha = 0x0,
 	.config_ctl_val = 0x20485699,
@@ -324,6 +378,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll5_out_even[] = {
 	{ }
 };
 
+static struct clk_init_data cam_cc_pll5_out_even_sm8475_init = {
+	.name = "cam_cc_pll5_out_even",
+	.parent_hws = (const struct clk_hw*[]) {
+		&cam_cc_pll5.clkr.hw,
+	},
+	.num_parents = 1,
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+};
+
 static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
 	.offset = 0x5000,
 	.post_div_shift = 10,
@@ -342,7 +406,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll5_out_even = {
 	},
 };
 
-static const struct alpha_pll_config cam_cc_pll6_config = {
+static struct alpha_pll_config cam_cc_pll6_config = {
 	.l = 0x2d,
 	.alpha = 0x0,
 	.config_ctl_val = 0x20485699,
@@ -372,6 +436,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll6_out_even[] = {
 	{ }
 };
 
+static struct clk_init_data cam_cc_pll6_out_even_sm8475_init = {
+	.name = "cam_cc_pll6_out_even",
+	.parent_hws = (const struct clk_hw*[]) {
+		&cam_cc_pll6.clkr.hw,
+	},
+	.num_parents = 1,
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+};
+
 static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
 	.offset = 0x6000,
 	.post_div_shift = 10,
@@ -390,7 +464,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll6_out_even = {
 	},
 };
 
-static const struct alpha_pll_config cam_cc_pll7_config = {
+static struct alpha_pll_config cam_cc_pll7_config = {
 	.l = 0x2d,
 	.alpha = 0x0,
 	.config_ctl_val = 0x20485699,
@@ -420,6 +494,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll7_out_even[] = {
 	{ }
 };
 
+static struct clk_init_data cam_cc_pll7_out_even_sm8475_init = {
+	.name = "cam_cc_pll7_out_even",
+	.parent_hws = (const struct clk_hw*[]) {
+		&cam_cc_pll7.clkr.hw,
+	},
+	.num_parents = 1,
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+};
+
 static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
 	.offset = 0x7000,
 	.post_div_shift = 10,
@@ -438,7 +522,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll7_out_even = {
 	},
 };
 
-static const struct alpha_pll_config cam_cc_pll8_config = {
+static struct alpha_pll_config cam_cc_pll8_config = {
 	.l = 0x32,
 	.alpha = 0x0,
 	.config_ctl_val = 0x20485699,
@@ -468,6 +552,16 @@ static const struct clk_div_table post_div_table_cam_cc_pll8_out_even[] = {
 	{ }
 };
 
+static struct clk_init_data cam_cc_pll8_out_even_sm8475_init = {
+	.name = "cam_cc_pll8_out_even",
+	.parent_hws = (const struct clk_hw*[]) {
+		&cam_cc_pll8.clkr.hw,
+	},
+	.num_parents = 1,
+	.flags = CLK_SET_RATE_PARENT,
+	.ops = &clk_alpha_pll_postdiv_lucid_ole_ops,
+};
+
 static struct clk_alpha_pll_postdiv cam_cc_pll8_out_even = {
 	.offset = 0x8000,
 	.post_div_shift = 10,
@@ -2817,6 +2911,7 @@ static const struct qcom_cc_desc cam_cc_sm8450_desc = {
 
 static const struct of_device_id cam_cc_sm8450_match_table[] = {
 	{ .compatible = "qcom,sm8450-camcc" },
+	{ .compatible = "qcom,sm8475-camcc" },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table);
@@ -2829,6 +2924,122 @@ static int cam_cc_sm8450_probe(struct platform_device *pdev)
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
+	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-camcc")) {
+		/* Update CAMCC PLL0 Config */
+		cam_cc_pll0_config.config_ctl_hi1_val = 0x82aa299c;
+		cam_cc_pll0_config.test_ctl_val = 0x00000000;
+		cam_cc_pll0_config.test_ctl_hi_val = 0x00000003;
+		cam_cc_pll0_config.test_ctl_hi1_val = 0x00009000;
+		cam_cc_pll0_config.test_ctl_hi2_val = 0x00000034;
+		cam_cc_pll0_config.user_ctl_hi_val = 0x00000005;
+
+		cam_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+
+		cam_cc_pll0_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+		cam_cc_pll0_out_even.clkr.hw.init = &cam_cc_pll0_out_even_sm8475_init;
+		cam_cc_pll0_out_odd.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+		cam_cc_pll0_out_odd.clkr.hw.init = &cam_cc_pll0_out_odd_sm8475_init;
+
+		/* Update CAMCC PLL1 Config */
+		cam_cc_pll1_config.config_ctl_hi1_val = 0x82aa299c;
+		cam_cc_pll1_config.test_ctl_val = 0x00000000;
+		cam_cc_pll1_config.test_ctl_hi_val = 0x00000003;
+		cam_cc_pll1_config.test_ctl_hi1_val = 0x00009000;
+		cam_cc_pll1_config.test_ctl_hi2_val = 0x00000034;
+		cam_cc_pll1_config.user_ctl_hi_val = 0x00000005;
+
+		cam_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+
+		cam_cc_pll1_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+		cam_cc_pll1_out_even.clkr.hw.init = &cam_cc_pll1_out_even_sm8475_init;
+
+		/* Update CAMCC PLL2 Config */
+		cam_cc_pll2_config.config_ctl_val = 0x10000030;
+		cam_cc_pll2_config.config_ctl_hi_val = 0x80890263;
+		cam_cc_pll2_config.user_ctl_val = 0x00000001;
+		cam_cc_pll2_config.user_ctl_hi_val = 0x00000000;
+
+		cam_cc_pll2.vco_table = rivian_ole_vco;
+
+		/* Update CAMCC PLL3 Config */
+		cam_cc_pll3_config.config_ctl_hi1_val = 0x82aa299c;
+		cam_cc_pll3_config.test_ctl_val = 0x00000000;
+		cam_cc_pll3_config.test_ctl_hi_val = 0x00000003;
+		cam_cc_pll3_config.test_ctl_hi1_val = 0x00009000;
+		cam_cc_pll3_config.test_ctl_hi2_val = 0x00000034;
+		cam_cc_pll3_config.user_ctl_hi_val = 0x00000005;
+
+		cam_cc_pll3.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+
+		cam_cc_pll3_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+		cam_cc_pll3_out_even.clkr.hw.init = &cam_cc_pll3_out_even_sm8475_init;
+
+		/* Update CAMCC PLL4 Config */
+		cam_cc_pll4_config.config_ctl_hi1_val = 0x82aa299c;
+		cam_cc_pll4_config.test_ctl_val = 0x00000000;
+		cam_cc_pll4_config.test_ctl_hi_val = 0x00000003;
+		cam_cc_pll4_config.test_ctl_hi1_val = 0x00009000;
+		cam_cc_pll4_config.test_ctl_hi2_val = 0x00000034;
+		cam_cc_pll4_config.user_ctl_hi_val = 0x00000005;
+
+		cam_cc_pll4.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+
+		cam_cc_pll4_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+		cam_cc_pll4_out_even.clkr.hw.init = &cam_cc_pll4_out_even_sm8475_init;
+
+		/* Update CAMCC PLL5 Config */
+		cam_cc_pll5_config.config_ctl_hi1_val = 0x82aa299c;
+		cam_cc_pll5_config.test_ctl_val = 0x00000000;
+		cam_cc_pll5_config.test_ctl_hi_val = 0x00000003;
+		cam_cc_pll5_config.test_ctl_hi1_val = 0x00009000;
+		cam_cc_pll5_config.test_ctl_hi2_val = 0x00000034;
+		cam_cc_pll5_config.user_ctl_hi_val = 0x00000005;
+
+		cam_cc_pll5.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+
+		cam_cc_pll5_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+		cam_cc_pll5_out_even.clkr.hw.init = &cam_cc_pll5_out_even_sm8475_init;
+
+		/* Update CAMCC PLL6 Config */
+		cam_cc_pll6_config.config_ctl_hi1_val = 0x82aa299c;
+		cam_cc_pll6_config.test_ctl_val = 0x00000000;
+		cam_cc_pll6_config.test_ctl_hi_val = 0x00000003;
+		cam_cc_pll6_config.test_ctl_hi1_val = 0x00009000;
+		cam_cc_pll6_config.test_ctl_hi2_val = 0x00000034;
+		cam_cc_pll6_config.user_ctl_hi_val = 0x00000005;
+
+		cam_cc_pll6.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+
+		cam_cc_pll6_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+		cam_cc_pll6_out_even.clkr.hw.init = &cam_cc_pll6_out_even_sm8475_init;
+
+		/* Update CAMCC PLL7 Config */
+		cam_cc_pll7_config.config_ctl_hi1_val = 0x82aa299c;
+		cam_cc_pll7_config.test_ctl_val = 0x00000000;
+		cam_cc_pll7_config.test_ctl_hi_val = 0x00000003;
+		cam_cc_pll7_config.test_ctl_hi1_val = 0x00009000;
+		cam_cc_pll7_config.test_ctl_hi2_val = 0x00000034;
+		cam_cc_pll7_config.user_ctl_hi_val = 0x00000005;
+
+		cam_cc_pll7.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+
+		cam_cc_pll7_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+		cam_cc_pll7_out_even.clkr.hw.init = &cam_cc_pll7_out_even_sm8475_init;
+
+		/* Update CAMCC PLL8 Config */
+		cam_cc_pll8_config.config_ctl_hi1_val = 0x82aa299c;
+		cam_cc_pll8_config.test_ctl_val = 0x00000000;
+		cam_cc_pll8_config.test_ctl_hi_val = 0x00000003;
+		cam_cc_pll8_config.test_ctl_hi1_val = 0x00009000;
+		cam_cc_pll8_config.test_ctl_hi2_val = 0x00000034;
+		cam_cc_pll8_config.user_ctl_hi_val = 0x00000005;
+
+		cam_cc_pll8.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+
+		cam_cc_pll8_out_even.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
+		cam_cc_pll8_out_even.clkr.hw.init = &cam_cc_pll8_out_even_sm8475_init;
+	}
+
 	clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);
 	clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);
 	clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);
@@ -2852,5 +3063,5 @@ static struct platform_driver cam_cc_sm8450_driver = {
 
 module_platform_driver(cam_cc_sm8450_driver);
 
-MODULE_DESCRIPTION("QCOM CAMCC SM8450 Driver");
+MODULE_DESCRIPTION("QCOM CAMCC SM8450 / SM8475 Driver");
 MODULE_LICENSE("GPL");
-- 
2.45.2

Re: [PATCH 01/10] dt-bindings: clock: qcom,gcc-sm8450: Add SM8475 GCC bindings

[Vladimir Zapolskiy]

Hello Danila.

On 7/31/24 20:59, Danila Tikhonov wrote:
> Add SM8475 GCC bindings, which are simply a symlink to the SM8450
> bindings. Update the documentation with the new compatible.
> 
> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>


> diff --git a/include/dt-bindings/clock/qcom,gcc-sm8450.h b/include/dt-bindings/clock/qcom,gcc-sm8450.h
> index 9679410843a0..5f1f9ab71a22 100644
> --- a/include/dt-bindings/clock/qcom,gcc-sm8450.h
> +++ b/include/dt-bindings/clock/qcom,gcc-sm8450.h
> @@ -194,6 +194,8 @@
>   #define GCC_VIDEO_AXI0_CLK					182
>   #define GCC_VIDEO_AXI1_CLK					183
>   #define GCC_VIDEO_XO_CLK					184
> +#define GCC_GPLL2						185
> +#define GCC_GPLL3						186

To avoid any probable confusion related to the list of clocks on SM8450
platform let's add a new header file.

>   /* GCC resets */
>   #define GCC_CAMERA_BCR						0
> diff --git a/include/dt-bindings/clock/qcom,sm8475-gcc.h b/include/dt-bindings/clock/qcom,sm8475-gcc.h
> new file mode 120000
> index 000000000000..daafdd881892
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,sm8475-gcc.h
> @@ -0,0 +1 @@
> +qcom,gcc-sm8450.h
> \ No newline at end of file

Instead of adding a symbolic link to the already existing header file please
create a header file, which includes the old one:

#include "qcom,gcc-sm8450.h"

#define GCC_GPLL2						185
#define GCC_GPLL3						186

In drivers/clk/qcom/gcc-sm8450.c file along with new functional changes
include the new header file instead of the old one.

--
Best wishes,
Vladimir

Re: [PATCH 03/10] dt-bindings: clock: qcom,sm8450-dispcc: Add SM8475 DISPCC bindings

[Vladimir Zapolskiy]

Hello Danila.

On 7/31/24 20:59, Danila Tikhonov wrote:
> Add SM8475 DISPCC bindings, which are simply a symlink to the SM8450
> bindings. Update the documentation with the new compatible.
> 
> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
> ---
>   .../devicetree/bindings/clock/qcom,sm8450-dispcc.yaml        | 5 ++++-
>   include/dt-bindings/clock/qcom,sm8475-dispcc.h               | 1 +
>   2 files changed, 5 insertions(+), 1 deletion(-)
>   create mode 120000 include/dt-bindings/clock/qcom,sm8475-dispcc.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml
> index 4794c53793a8..76f5a8cc42cc 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-dispcc.yaml
> @@ -13,12 +13,15 @@ description: |
>     Qualcomm display clock control module provides the clocks, resets and power
>     domains on SM8450.
>   
> -  See also:: include/dt-bindings/clock/qcom,sm8450-dispcc.h
> +  See also::
> +    include/dt-bindings/clock/qcom,sm8450-dispcc.h
> +    include/dt-bindings/clock/qcom,sm8475-dispcc.h

Here a new header file is not needed.

>   properties:
>     compatible:
>       enum:
>         - qcom,sm8450-dispcc
> +      - qcom,sm8475-dispcc

This added line shall be kept though.

>     clocks:
>       minItems: 3
> diff --git a/include/dt-bindings/clock/qcom,sm8475-dispcc.h b/include/dt-bindings/clock/qcom,sm8475-dispcc.h
> new file mode 120000
> index 000000000000..21a9db2d0f09
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,sm8475-dispcc.h
> @@ -0,0 +1 @@
> +qcom,sm8450-dispcc.h
> \ No newline at end of file

Please remove the symlink, it will not be used.

--
Best wishes,
Vladimir

Re: [PATCH 05/10] dt-bindings: clock: qcom,sm8450-gpucc: Add SM8475 GPUCC bindings

[Vladimir Zapolskiy]

On 7/31/24 20:59, Danila Tikhonov wrote:
> Add SM8475 GPUCC bindings, which are simply a symlink to the SM8450
> bindings. Update the documentation with the new compatible.
> 
> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
> ---
>   Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml | 3 +++
>   include/dt-bindings/clock/qcom,sm8475-gpucc.h                  | 1 +
>   include/dt-bindings/reset/qcom,sm8475-gpucc.h                  | 1 +
>   3 files changed, 5 insertions(+)
>   create mode 120000 include/dt-bindings/clock/qcom,sm8475-gpucc.h
>   create mode 120000 include/dt-bindings/reset/qcom,sm8475-gpucc.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
> index d10bb002906e..608fe63fb43a 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-gpucc.yaml
> @@ -15,8 +15,10 @@ description: |
>   
>     See also::
>       include/dt-bindings/clock/qcom,sm8450-gpucc.h
> +    include/dt-bindings/clock/qcom,sm8475-gpucc.h
>       include/dt-bindings/clock/qcom,sm8550-gpucc.h
>       include/dt-bindings/reset/qcom,sm8450-gpucc.h
> +    include/dt-bindings/reset/qcom,sm8475-gpucc.h
>       include/dt-bindings/reset/qcom,sm8650-gpucc.h
>       include/dt-bindings/reset/qcom,x1e80100-gpucc.h
>   
> @@ -24,6 +26,7 @@ properties:
>     compatible:
>       enum:
>         - qcom,sm8450-gpucc
> +      - qcom,sm8475-gpucc
>         - qcom,sm8550-gpucc
>         - qcom,sm8650-gpucc
>         - qcom,x1e80100-gpucc
> diff --git a/include/dt-bindings/clock/qcom,sm8475-gpucc.h b/include/dt-bindings/clock/qcom,sm8475-gpucc.h
> new file mode 120000
> index 000000000000..2ba622290833
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,sm8475-gpucc.h
> @@ -0,0 +1 @@
> +qcom,sm8450-gpucc.h
> \ No newline at end of file
> diff --git a/include/dt-bindings/reset/qcom,sm8475-gpucc.h b/include/dt-bindings/reset/qcom,sm8475-gpucc.h
> new file mode 120000
> index 000000000000..2ba622290833
> --- /dev/null
> +++ b/include/dt-bindings/reset/qcom,sm8475-gpucc.h
> @@ -0,0 +1 @@
> +qcom,sm8450-gpucc.h
> \ No newline at end of file

Please remove the added symlinks.

--
Best wishes,
Vladimir

Re: [PATCH 07/10] dt-bindings: clock: qcom,sm8450-videocc: Add SM8475 VIDEOCC bindings

[Vladimir Zapolskiy]

On 7/31/24 20:59, Danila Tikhonov wrote:
> Add SM8475 VIDEOCC bindings, which are simply a symlink to the SM8450
> bindings. Update the documentation with the new compatible.
> 
> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
> ---
>   .../devicetree/bindings/clock/qcom,sm8450-videocc.yaml          | 2 ++
>   include/dt-bindings/clock/qcom,sm8475-videocc.h                 | 1 +
>   2 files changed, 3 insertions(+)
>   create mode 120000 include/dt-bindings/clock/qcom,sm8475-videocc.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
> index b2792b4bb554..9186d2ee87f8 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml
> @@ -16,12 +16,14 @@ description: |
>   
>     See also:
>       include/dt-bindings/clock/qcom,sm8450-videocc.h
> +    include/dt-bindings/clock/qcom,sm8475-videocc.h
>       include/dt-bindings/clock/qcom,sm8650-videocc.h

Won't be needed.

>   properties:
>     compatible:
>       enum:
>         - qcom,sm8450-videocc
> +      - qcom,sm8475-videocc
>         - qcom,sm8550-videocc
>         - qcom,sm8650-videocc
>   
> diff --git a/include/dt-bindings/clock/qcom,sm8475-videocc.h b/include/dt-bindings/clock/qcom,sm8475-videocc.h
> new file mode 120000
> index 000000000000..231cd153052c
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,sm8475-videocc.h
> @@ -0,0 +1 @@
> +qcom,sm8450-videocc.h
> \ No newline at end of file

Please remove the added symlink.

--
Best wishes,
Vladimir

Re: [PATCH 09/10] dt-bindings: clock: qcom,sm8450-camcc: Add SM8475 CAMCC bindings

[Vladimir Zapolskiy]

On 7/31/24 20:59, Danila Tikhonov wrote:
> Add SM8475 CAMCC bindings, which are simply a symlink to the SM8450
> bindings. Update the documentation with the new compatible.
> 
> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
> ---
>   Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml | 2 ++
>   include/dt-bindings/clock/qcom,sm8475-camcc.h                  | 1 +
>   2 files changed, 3 insertions(+)
>   create mode 120000 include/dt-bindings/clock/qcom,sm8475-camcc.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
> index f58edfc10f4c..2dea246882c3 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-camcc.yaml
> @@ -17,6 +17,7 @@ description: |
>     See also:
>       include/dt-bindings/clock/qcom,sc8280xp-camcc.h
>       include/dt-bindings/clock/qcom,sm8450-camcc.h
> +    include/dt-bindings/clock/qcom,sm8475-camcc.h

This change won't be needed.

>       include/dt-bindings/clock/qcom,sm8550-camcc.h
>       include/dt-bindings/clock/qcom,sm8650-camcc.h
>       include/dt-bindings/clock/qcom,x1e80100-camcc.h
> @@ -29,6 +30,7 @@ properties:
>       enum:
>         - qcom,sc8280xp-camcc
>         - qcom,sm8450-camcc
> +      - qcom,sm8475-camcc
>         - qcom,sm8550-camcc
>         - qcom,sm8650-camcc
>         - qcom,x1e80100-camcc
> diff --git a/include/dt-bindings/clock/qcom,sm8475-camcc.h b/include/dt-bindings/clock/qcom,sm8475-camcc.h
> new file mode 120000
> index 000000000000..45444160d465
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,sm8475-camcc.h
> @@ -0,0 +1 @@
> +qcom,sm8450-camcc.h
> \ No newline at end of file

Please remove the added symlink.

--
Best wishes,
Vladimir

Re: [PATCH 08/10] clk: qcom: videocc-sm8450: Add SM8475 support

[Dmitry Baryshkov]

On Wed, Jul 31, 2024 at 08:59:17PM GMT, Danila Tikhonov wrote:
> Add support to the SM8475 video clock controller by extending the
> SM8450 video clock controller, which is almost identical but has some
> minor differences.
> 
> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
> ---
>  drivers/clk/qcom/Kconfig          |  2 +-
>  drivers/clk/qcom/videocc-sm8450.c | 31 ++++++++++++++++++++++++++++---
>  2 files changed, 29 insertions(+), 4 deletions(-)
> 
> @@ -420,6 +421,30 @@ static int video_cc_sm8450_probe(struct platform_device *pdev)
>  		return PTR_ERR(regmap);
>  	}
>  
> +	if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-videocc")) {
> +		/* Update VideoCC PLL0 Config */
> +		video_cc_pll0_config.l = 0x1e;
> +		video_cc_pll0_config.config_ctl_hi1_val = 0x82aa299c;
> +		video_cc_pll0_config.test_ctl_val = 0x00000000;
> +		video_cc_pll0_config.test_ctl_hi_val = 0x00000003;
> +		video_cc_pll0_config.test_ctl_hi1_val = 0x00009000;
> +		video_cc_pll0_config.test_ctl_hi2_val = 0x00000034;
> +		video_cc_pll0_config.user_ctl_hi_val = 0x00000005;

Maybe it would be better to define new PLL configs rather than to patch
the existing ones?

> +
> +		video_cc_pll0.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
> +
> +		/* Update VideoCC PLL1 Config */
> +		video_cc_pll1_config.l = 0x2b;
> +		video_cc_pll1_config.config_ctl_hi1_val = 0x82aa299c;
> +		video_cc_pll1_config.test_ctl_val = 0x00000000;
> +		video_cc_pll1_config.test_ctl_hi_val = 0x00000003;
> +		video_cc_pll1_config.test_ctl_hi1_val = 0x00009000;
> +		video_cc_pll1_config.test_ctl_hi2_val = 0x00000034;
> +		video_cc_pll1_config.user_ctl_hi_val = 0x00000005;
> +
> +		video_cc_pll1.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE];
> +	}
> +
>  	clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_config);
>  	clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_config);
>  
> @@ -445,5 +470,5 @@ static struct platform_driver video_cc_sm8450_driver = {
>  
>  module_platform_driver(video_cc_sm8450_driver);
>  
> -MODULE_DESCRIPTION("QTI VIDEOCC SM8450 Driver");
> +MODULE_DESCRIPTION("QTI VIDEOCC SM8450 / SM8475 Driver");
>  MODULE_LICENSE("GPL");
> -- 
> 2.45.2
> 

-- 
With best wishes
Dmitry

Re: [PATCH 01/10] dt-bindings: clock: qcom,gcc-sm8450: Add SM8475 GCC bindings

[Krzysztof Kozlowski]

On 31/07/2024 19:59, Danila Tikhonov wrote:
> Add SM8475 GCC bindings, which are simply a symlink to the SM8450
> bindings. Update the documentation with the new compatible.
> 
> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
> ---
>  .../devicetree/bindings/clock/qcom,gcc-sm8450.yaml        | 8 ++++++--
>  include/dt-bindings/clock/qcom,gcc-sm8450.h               | 2 ++
>  include/dt-bindings/clock/qcom,sm8475-gcc.h               | 1 +
>  3 files changed, 9 insertions(+), 2 deletions(-)
>  create mode 120000 include/dt-bindings/clock/qcom,sm8475-gcc.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
> index d848361beeb3..c7d75ee2a23b 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm8450.yaml
> @@ -13,11 +13,15 @@ description: |
>    Qualcomm global clock control module provides the clocks, resets and power
>    domains on SM8450
>  
> -  See also:: include/dt-bindings/clock/qcom,gcc-sm8450.h
> +  See also::

You can use one : (:: -> :). That was a mistake to use double colons.

> +    include/dt-bindings/clock/qcom,gcc-sm8450.h
> +    include/dt-bindings/clock/qcom,sm8475-gcc.h
>  
>  properties:
>    compatible:
> -    const: qcom,gcc-sm8450
> +    enum:
> +      - qcom,gcc-sm8450
> +      - qcom,sm8475-gcc
>  
>    clocks:
>      items:
> diff --git a/include/dt-bindings/clock/qcom,gcc-sm8450.h b/include/dt-bindings/clock/qcom,gcc-sm8450.h
> index 9679410843a0..5f1f9ab71a22 100644
> --- a/include/dt-bindings/clock/qcom,gcc-sm8450.h
> +++ b/include/dt-bindings/clock/qcom,gcc-sm8450.h
> @@ -194,6 +194,8 @@
>  #define GCC_VIDEO_AXI0_CLK					182
>  #define GCC_VIDEO_AXI1_CLK					183
>  #define GCC_VIDEO_XO_CLK					184
> +#define GCC_GPLL2						185
> +#define GCC_GPLL3						186

Are these valid for sm8450?

>  
>  /* GCC resets */
>  #define GCC_CAMERA_BCR						0
> diff --git a/include/dt-bindings/clock/qcom,sm8475-gcc.h b/include/dt-bindings/clock/qcom,sm8475-gcc.h
> new file mode 120000
> index 000000000000..daafdd881892
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,sm8475-gcc.h

If the bindings are the same... then why having separate header? I
suggest dropping it.

Best regards,
Krzysztof

Re: [PATCH 03/10] dt-bindings: clock: qcom,sm8450-dispcc: Add SM8475 DISPCC bindings

[Krzysztof Kozlowski]

On 31/07/2024 19:59, Danila Tikhonov wrote:
> Add SM8475 DISPCC bindings, which are simply a symlink to the SM8450
> bindings. Update the documentation with the new compatible.
> 
> Signed-off-by: Danila Tikhonov <danila@jiaxyga.com>
> ---

Same comments as for patch #1.

Best regards,
Krzysztof