RE: [RESEND PATCHv2 0/3] Power-domain clk handling

[Kukjin Kim <kgene.kim@samsung.com>]

Arun Kumar K wrote:
> 
> This patch series for clock handling in power domain is
> re-send for merging after rebasing onto latest linux-samsung.git,
> for-next branch.
> Original series and discussion can be found here:
> https://www.mail-archive.com/linux-samsung-soc@vger.kernel.org/msg31550.html
> 
> Arun Kumar K (2):
>   clk: exynos5420: Add IDs for clocks used in PD mfc
>   ARM: dts: Add clock property for mfc_pd in 5420
> 
> Prathyush K (1):
>   ARM: EXYNOS: Add support for clock handling in power domain
> 
>  .../bindings/arm/exynos/power_domain.txt           |   20 +++++++
>  arch/arm/boot/dts/exynos5420.dtsi                  |    3 +
>  arch/arm/mach-exynos/pm_domains.c                  |   61 +++++++++++++++++++-
>  drivers/clk/samsung/clk-exynos5420.c               |    6 +-
>  include/dt-bindings/clock/exynos5420.h             |    2 +
>  5 files changed, 89 insertions(+), 3 deletions(-)
> 
> --
> 1.7.9.5

Yeah, this is required now because regarding clock registers are also powered
down during pd-off on some exynos SoCs as you mentioned. Just note that you
know the registers are moved into pd related register on latest exynos SoC's
anyway. 

OK, I will apply into fixes for 3.16.

Thanks,
Kukjin